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functionality
Collision warning or avoidance
(77-81 GHz) with multiple functions like long-range, short-range and precision
ranging.
Combined radar for ACC, pre-cash sensing and parking support
C = C1 2V
T
The above relationship shows that the emitter-coupled pair by itself can
be used as a simple multiplier (Fig. 10 ).
Figure 10 : The dc transfer characteristics of emitter-coupled pair [26]
With the assumption that the differential input voltage V
id
is much less
than V
T
we can utilize the following approximation
tanh(
V
id
)
V
id
V
id
1 (5)
2V
2V 2V <<
T T T
and equation (4) becomes
I
I (
V
id
) (6)
C EE
2V
T
22
The current I
EE
is the bias current of emitter-coupled pair. With the
addition of more circuitry, we can make I
EE
proportional to second input
voltage V
i2
as shown in Fig. 11.
Figure 11: Two quadrant analog multiplier [26]
Thus, we have
I
EE
=
K
o
(V
i 2
V
BE (on )
)
(7)
Putting equation (7) in (6)
I
K (V V
) (
V
id
) (8)
C
o i 2 BE (on ) 2V
T
23
Under the assumption V
id
is small and V
i2
is greater than V
BE(on)
we
have come up to a relation that shows the multiplier function. The latter
restriction means that the multiplier functions in two quadrants of the V
id
-
V
i2
plane and this type of circuit is known as two-quadrant multiplier.
The restriction to two quadrants of operation is a severe one for many
communications applications, and most practical multipliers allow four-
quadrant operation. The Gilbert multiplier cell is a modification of the
emitter-coupled cell, which allows four-quadrant multiplication. It is the
basis for most integrated-circuit balanced multiplier systems. The series
connection of an emitter-coupled pair with two cross-coupled, emitter
coupled pairs produces a useful transfer function as shown in the next
section.
2.3.2. Gilbert Multiplier Cell
For the Gilbert cell shown in Fig. 12, we assume that all transistors are
identical and output resistances of transistors and that of biasing current
source can be neglected. The collector currents using equation (2) and (3)
are as follows
I
C 3
I
C1
(9)
=
1
V
exp(
1
)
V
+
T
I
C 4
=
I
C1
(10)
1 exp(
V
1
)
+ V
T
Similarly for Q
5
and Q
6
I
C 5
=
I
C 2
(11)
1 exp(
V
1
)
+ V
T
I
C 6
I
C 2
(12)
=
1
V
exp(
1
)
V
+
T
24
Figure 12: Gilbert multiplier circuit
Similarly, I
C1
and I
C2
are related to V
2
I
C1
=
I
EE
1
exp(
V 2
) + V
T
I
C 2
=
I
EE
1 exp(
V
2
)
+
V
T
Putting values of I
C1
and I
C2
into equations (9)-(12)
I
C 3
=
I
EE
[1 exp(
V
1
)][1 exp(
V
2
)]
V
+
V
+
T T
25
(13)
(14)
(15)
I
C 4
=
I
EE
(16)
[1 exp(
V
2
)][1 exp(
V
1
)]
V
+ + V
T T
I
C 5
=
I
EE
(17)
[1 exp(
V
1
)][1 exp(
V
2
)]
+ V
T
+ V
T
I
C 6
=
I
EE
(18)
[1 exp(
V
2
)][1 exp(
V
1
)]
+ V +
V
T T
The differential output current is then given by
I =
I
C 35
I
C 46
=
I
C 3
+
I
C 5
(I
C 4
+
I
C 6
)
I =
(I
C 3
I
C 6
)
(I
C 4
I
C 5
)
(19)
I I tanh(
V
1
) tanh(
V
2
) (20)
EE
2V
= 2V
T T
The dc transfer characteristics, then, is the product of the hyperbolic
tangent of the two input voltages. There are three main applications of the
Gilbert cell depending of the V
1
and V
2
range compared to V
T.
If V1<VT and V2 < VT, the hyperbolic tangent function can be
effectively multiplies the applied small signal by a square wave, and acts as a
modulator.
If both inputs are large compared to V
T
, and all six transistors in
V
k
is offset voltage deriving from the unbalanced constitution and
defined as V
K
= V
T
ln ( K ) .
V
in
is the differential input voltage
Using
1
1 X .....( | X |
| 1 ) , expanding (26)
1 X =
<<
K
1
cosh(
V
in
)
K
2
V
T
I
FD
F
I
o
1
1
1
1
...
=
K
+ K
K
2 + K
Using
cosh(x )
=
1
x
2
x
4
+
.....(x
2
<
)
+ 2 + 12
I
2
I
K
2
1
1
2K
1
V
in
2
V
in
2
... ...
FD
F o
=
( K
2
1)
K
2
1 + 2
V
T
2
+ 12V
T
4
+
+ +
K
2
1
2
4
2
V
in
V
in
I
2
I
K
1 K
K
...
(
K
2
FD
=
F
o
1 )
2
(
)
V
T
2
6V
T
4
+
(27)
(28)
(29)
The differential output current is expressed as a function of the square of
the differential input voltage. Fig. 21 shows dc transfer curves of the
frequency doubler, calculated using (24) with various values of parameter
K. For a small input voltage the transfer curve is approximately a
parabola. Therefore, the input frequency is doubled by this circuit.
40
Figure 21: DC transfer curves of frequency doubler [43]
3.4.2. Optimum value of size ratio K
Size of Q1 and Q4 was selected as 1 m. The optimum value of size ratio K
was found by simulations. The value
o
+
1
+
R
L
+
r
o
If r R , 1 and rR then (30) can be approximated as
S
0
0
L
v
o
g
m
R
L
(31)
v
s
1
+
g
m
R
L
From (31) we infer that the emitter-follower gain is slightly less than
unity. In the current design, two identical emitter-followers have been
used one in each path for differential architecture. The RF port of Gilbert
mixer is buffered by an additional emitter-follower stage that has one
extra resistor between collector and supply voltage to control signal level
at the RF port. Minimum transistor sizing for the emitter-follower circuit
has been used to keep the input impedance high. R
L
has been selected to
match the optimum density of the collector current and thereby to boost
the Gilbert cell performance.
4.6.2. Gilbert Cell
A circuit representing the Gilbert bipolar mixer cell is shown is Fig. 30.
Its application as the frequency multiplier has already been discussed in
Chapter 2.
The following relation for the differential output current holds:
I I
EE
tanh(
V
LO
) tanh(
V
RF
) (32)
= 2V
T
2V
T
Here, both RF and LO ports are fed by the same signal except for the
additional emitter-follower stage in RF path. For simplicity, we assume
the gain of the emitter-followers as unity and take V
LO
=V
RF
=V
in
52
Figure 30 Gilbert mixer
I I tanh
2
(
V
in
) (33)
2V
= EE
T
and the differential voltage across load R
L
is
2
V
) (34) V =
I
EE
R
L
tanh
(
in
2V
T
Hence, the circuit gain is given by
I
R
L
tanh
2
(
V
in
)
EE
V 2V
T
(35)
=
V
in
V
in
53
I
EE
R
L
tanh
2
(
V
in
)
2V
T
G = 20 log
(36)
V
in
For simplicity, we take
I
EE
R
L
= 1 and V
T
= 26 mV (at room temperature)
tanh
2
(
V
in
)
0.052
G 20 log
(37)
=
V
in
The simplified gain expression can be plotted against the input voltage as
shown in Fig. 31. We see that the Gilbert cell gain is nowhere constant
but it has partly parabolic and partly hyperbolic shape. When this circuit
is used in frequency doubler application, the parameters that define
linearity of the circuit like 1dB compression point or IIP3 do not apply
because the gain varies with the input signal level. The input voltage
range over which circuit performance is optimum can be defined.
Figure 31: Variable gain of Gilbert mixer in frequency doubler circuit
54
If we denote gain of the two emitter-follower stages as A
1
the differential output voltage across load R
L
is
AV
in
A A V
V R I
EE
tanh(
1
) tanh(
1 2 in
)
2V
2V
= L
T T
and A
2
then
(38)
4.6.3. Filter
To filter out undesired harmonics, a first order resonant circuit can be
placed at the output of the Gilbert mixer. Its resonant frequency is
matched to 2
nd
harmonic which is 80 GHz for the current design. The
resonant frequency of LC tank is given by
f
1
(39)
= 2 LC
If we take C=50fF and L=80pH, approximate value of resonant
frequency is 80 GHz.
Due to non-availability of inductors in B7HF200 technology, the required
inductive reactances can be realized by short microstrip lines with the
signal line in the fourth metallization layer and the ground plane in the
first or second layer. For lossless transmission lines with a real or virtual
short at its end, the effective inductance is given by [46]
L
Z
O
tan(2
l
) (40)
eff
= 2 f
where l is the line length, is the wavelength, Z
O
the characteristic line
impedance, and f the frequency. A high value of Z
o
(i.e., a thick dielectric
layer between the upper and lower metallization layers) is favourable due
to the reduced line length at given L
eff
. Consequently, the parasitic series
resistance is reduced, resulting in an increased quality factor of the
inductance.
The plot of the effective inductance of a lossless transmission line versus
its length (keeping l ) for different frequencies is shown in Fig. 32.
<< 4
55
Obviously, for l
<<
, L
eff
becomes independent of frequency and
proportional to l .
Transmission Line Effective Inductance
300.00
250.00
20 GHz
L
e
f
f
(
p
H
)
200.00
40 GHz
150.00
60 GHz
100.00
80 GHz
50.00
100 GHz
0.00
0 50 100 150 200 250 300 350
Length (um)
Figure 32: Effective inductance of a lossless transmission line for l< /4
For the current design, differential transmission line used is formed by
top metal (metal-4) and ground metal (metal-2) with Z
o
$s a starting
point, an approximate value for the length of transmission line was
determined equal to 202 um using (41). Each capacitor in the resonant
circuit has a value of 50 fF. The length of differential transmission line
was varied and filtering effect of corresponding resonant circuit was
observed with the help of CAD tool (Cadence). The transmission line
length at which the maximum conversion gain for the
current design was observed is 125 m.
4.6.4. Differential Amplifier
At the output stage, a differential amplifier has been used which is
probably the most often used type of an amplifier in integrated circuits.
The large signal analysis of this circuit (emitter-coupled pair) has been
discussed in Chapter 2. Here, our interest is in small signal behaviour
when the DC differential input voltage is zero. In this case, V
diff
represents the AC signal. In analyzing this circuit, we make the following
assumptions:
56
The magnitude of the input signal Vdiff is small enough that the
r
o
for the transistors is much larger than R
C
and can be ignored in
our analysis.
It is convenient to define the input signal as a sum of two components, a
DC common-mode voltage and an AC differential-mode voltage. We are
interested in differential mode gain given by
A
d
v
od
g
m
R
C
(41)
= v
id
=
Ideally, the differential gain is high while the common-mode gain is zero.
We can get a feel for how close a practical circuit is to the ideal by
evaluating the common-mode rejection ratio.
Figure 33: Differential Amplifier
The differential amplifier circuit used is shown in Fig. 33. A current
mirror circuit is placed at the bottom for biasing. The current of this
circuit is controlled by a limiting resistor R
CM
. Transistor sizes have been
57
selected to match optimum collector current density. The capacitors at the
input are a part of the preceding filter circuit. Due to AC coupling, the
transistor bases are biased through R
B
.
4.6.5. Integrated Circuit
Fig. 34 shows the integrated circuit by connecting together all parts of the
circuit and values of resistors and capacitors are given in Table 6.
Table-6: Design parameter values for 40 GHz frequency doubler circuit
Parameter Value Unit
RB1 300
RC1 200
RE1 100
RE2 200
RB2 10K
RC2 200
RCM1 400
RCM2 400
C
1
, C
2
600 fF
C
3
, C
4
50 fF
C
5
, C
6
300 fF
58
Figure 34: Detailed circuit diagram for frequency doubler at 40 GHz
59
4.7. Layout of the Frequency Doubler Circuit
The layout of the circuit shown in Fig.33 was drawn in Cadence Layout
Editor using Infineons B7HF200 technology with some modifications.
The following modifications to the frequency doubler schematic were
performed.
Resistors RE1, RE2, RCM1 and RCM2 were first realized as poly
The circuit needs some filtering to keep the fundamental tone at the output as
small as possible.
80
The gain of the Gilbert mixer when used in the frequency doubler