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Cheng-Wen Wu
Lab for Reliable Computing Dept. Electrical Engineering National Tsing Hua University
Outline
Introduction to VLSI testing Fault simulation Test pattern generation Design for testability (DFT): scan design Logic built-in self-test (BIST) Memory testing Memory BIST Memory diagnostics Boundary scan (IEEE 1149 family) & board-level test *Analog and mixed-signal circuit testing Core-based system-on-chip (SOC) testing *Delay test *Iddq test Array & FPGA testing *Concurrent error detection Test economics
Cheng-Wen Wu, NTHU 2
intro6.2
Chapter 1: Introduction
Cheng-Wen Wu
Lab for Reliable Computing Dept. Electrical Engineering National Tsing Hua University
Outline
Scope of testing Defect level and fault coverage Fault models
Classical faults Switch-level faults Timing faults Memory faults
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Marking Marking
Shipping Shipping
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Why Testing?
Economics!
Product quality Product reliability
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Test Cost
90 80 70 60 50 40 30 20 10 0 0.5um 0.35um 0.25um 0.18um
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Scope of Testing
Engineering Test
Diagnostic Test Fault location Failure analysis Design and/or process debugging
Manufacturing Test
Characterization Test Performance characterization: parametric test Reliability characterization: bathtub curve (aging) Production Test Simple parametric test Functional test Reliability screening (burn-in)
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Fault
Fault: a physical defect in a circuit/system
Permanent fault: a fault that is continuous and stable, whose
occurring at random moments and affecting the system for finite, but unknown, intervals of time
Transient fault: caused by environmental conditions No well-defined fault model Called soft error in RAM Often assumed no permanent damage was done
Intermittent fault: caused by non-environmental conditions Often repeatable Can use permanent fault models and repeated test with stress
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Error: manifestation of a fault that results in an incorrect module output or system state
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Failure
Failure: deviation of a system from its specified behavior
Fault error failure
Failure mechanism: physical or chemical process that causes devices to malfunction; they manifest themselves on the circuit level as failure modes Failure mode: the cause of rejection of failed device (effect of failure mechanism), such as open/short interconnections, or degraded parameter values
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Yield (Y) is the ratio of the number of good dies per wafer to the number of dies per wafer Fault coverage (FC) is the measure of the ability of a test set T to detect a given set of faults that may occur on the DUT
FC = (#detected faults)/(#possible faults)
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FC refers to the real defect coverage (probability that T detects any possible fault---in F or not) DL is measured in terms of DPM (defects per million), and typical values claimed are less than 200 DPM, or 0.02%
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Y (%)
10
50
90
95
99
FC(%) 99.99
99.97
99.8
99.6
98
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generation)
How is test quality (fault coverage) measured?
(fault simulation)
How are test vectors applied and results evaluated?
(ATE/BIST)
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a 0 0 1 1
b 0 1 0 1
c 0 0 0 1
Single (line) stuck-at fault: line has a constant value (0/1) Multiple stuck fault: several single stuck-at faults occur at the same time
For a circuit with k lines, there are 2k single stuck faults, and 3 -1
k
Test
A test for a fault f in circuit C is an input combination for which the output(s) of C is different when f is present than when it is not
A.k.a. test pattern, test vector, or experiment A test x detects fault f iff C(x)Cf(x)=1
A test set for a class of faults F is a set of tests T such that for any fault fF, there exists tT such that t detects f
intro6.2 Cheng-Wen Wu, NTHU 17
Fault Diagnosis
Fault detection: tells only whether a circuit is fault-free or not Fault identification (location; isolation): provides the location and the type of the detected fault and other related information Fault diagnosis: includes both fault detection and fault identification
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Testing
Testing is a process which includes test pattern generation, test pattern application, and output evaluation
The quality of a test set depends on its fault
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