Symcomponents

CDMA/IS-95
CDMA/IS-95-1
IS-95 Access Channel Block Deinterleaver
IS-95 Access Channel Block Deinterleaver (ACCBD95)

ACCBD95
Property Description Units Default Range/Type
RIN Input impedance Ohm Inf (0, Inf]/Real
ROUT Output impedance Ohm 0 [0, Inf)/Real
Ports
Input Input signal (real)
Output Output signal (real)
Notes
1. This model implements an IS-95 block deinterleaver for the access channel (reference 1).
Netlist Form
ACCBD95:Name n1 n2 [Rin=Val] [Rout=Val]
Netlist Example
ACCBD95:1 1 2
References
1. Mobile-Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellu-
lar System” TIA/EIA/IS-95-A, May 1995.
CDMA/IS-95-2
IS-95 Access Channel Block Interleaver (ACCBI95)
IS-95 Access Channel Block Interleaver (ACCBI95)

ACCBI95
Ports
Notes
1. This model implements an IS-95 block interleaver for the access channel. The first 576 sym-
bols at a fixed rate 4800 Hz is interleaved according to IS-95 specifications (Reference 1)
Netlist Form
ACCBI95:Name n1 n2 [Rin=Val] [Rout=Val]
Netlist Example
ACCBI95:1 1 2
References
1. Mobile-Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular
System” TIA/EIA/IS-95-A, May 1995.
CDMA/IS-95-3
IS-95 Add 8-Bit Tail Bits for Initializing Convolutional
IS-95 Add 8-Bit Tail Bits for Initializing Convolutional Coder

(CCTAIL95)
CCTAIL95
FDR Frame Data Rate Hz 1200 [1200Hz, 9600]/Real
ROUT output Impedance Ohm 0 [0, Inf)/Real
Ports
Notes
1. This model adds the IS-95 tail bits to initialize the convolutional coder (Reference 1). Because
eight tail bits have been added for 9600 Hz, 88 bits for 4800 Hz, 40 bits for 2400 Hz, 16 bits
for 1200 Hz, then the ratio of the output bit rate to input bit rate is 192/184, 96/88, 48/40, 24/16
for 9600Hz, 4800Hz, 2400Hz, and 1200Hz respectively.
Netlist Form
CCTAIL95:Name n1 n2 FDR=val [Rin=Val] [Rout=Val]
Netlist Example
CCTAIL95:1 1 2 FDR=9600Hz
References
CDMA/IS-95-4
IS-95 Add 8-Bit Tail Bits for Initializing Convolutional
CDMA/IS-95-5
IS-95 Finite Impulse Response Filter (FIRIS95)

FIRIS95
Ports
Notes
1. This model implements a 48-tap FIR filter based on the IS-95 specifications (Ref 1).
2. The input signal must have a sampling rate of 4.9152MHz.
3. The filter taps of the impulse response h[n] are given below:
h[0]= h[47] = -0.025288315

h[1]= h[46] = -0.034167931
h[2]= h[45] = -0.035752323
h[3]= h[44] = -0.016733702
h[4]= h[43] = 0.021602514
h[5]= h[42] = 0.064938487
h[6]= h[41] = 0.091002137
h[7]= h[40] = 0.081894974
h[8]= h[39] = 0.037071157
h[9]= h[38] = -0.021998074
h[10]= h[37] = -0.060716277
CDMA/IS-95-6
h[11]= h[36] = -0.051178658

h[12]= h[35] = 0.007874526
h[13]= h[34] = 0.084368728
h[14]= h[33] = 0.126869306
h[15]= h[32] = 0.094528345
h[16]= h[31] = -0.012839661
h[17]= h[30] = -0.143477028
h[18]= h[29] = -0.211829088
h[19]= h[28] = -0.140513128
h[20]= h[27] = 0.094601918
h[21]= h[26] = 0.441387140
h[22]= h[25] = 0.785875640
h[23]= h[24] = 1.0
Netlist Form
FIRIS95:Name n1 n2 [Rin=Val] [Rout=Val]
Netlist Example
FIRIS95:1 1 2
References
CDMA/IS-95-7
IS-95 Frame Quality Indicator (FQI95)
IS-95 Frame Quality Indicator (FQI95)

FQI95
FDR Frame Data Rate Hz 4800 4800 or 9600
Ports
Notes
1. The ratio of output bit rate and input bit rate is 184/172 for 9600Hz, 88/80 for 4800Hz.
2. This model adds the IS-95 frame quality indicator bits to the input signal (reference 1).
Netlist Form
FQI95:Name n1 n2 FDR=val [Rin=Val] [Rout=Val]
Netlist Example
FQI95:1 1 2 FDR=9600Hz
References
1. “Mobile-Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular
CDMA/IS-95-8
IS-95 Forward Traffic Channel Block Deinterleaver
IS-95 Forward Traffic Channel Block Deinterleaver (FTCBD95)

FTCBD95
FDR Frame Data Rate Hz 9600 [1200 9600]/Integer
Ports
Notes
1. This model implements an IS-95 block deinterleaver that only supports the four traffic rates:
1200Hz, 2400Hz, 4800Hz, and 9600Hz. The data at each rate (384 symbols) is deinterleaved
according to IS-95 specifications (Reference 1).
Netlist Form
FTCBD95:Name n1 n2 FDR=val [Rin=Val] [Rout=Val]
Netlist Example
FTCBD95:1 1 2 FDR=9600Hz
References
CDMA/IS-95-9
IS-95 Forward Traffic Channel Block Interleaver
IS-95 Forward Traffic Channel Block Interleaver (FTCBI95)

FTCBI95
FDR Frame Data Rate Hz 9600 [1200 9600]/Integer
ROUT Output Impedance Ohm 0 [0, Inf)/Real
Ports
Notes
1. This model implements an IS-95 block interleaver that only supports the four traffic rates:
1200Hz, 2400Hz, 4800Hz, and 9600Hz. The first 384 symbols at each rate are interleaved
Netlist Form
FTCBI95:Name n1 n2 FDR=val [Rin=Val] [Rout=Val]
Netlist Example
FIRIS95:1 1 2 FDR=9600Hz
References
CDMA/IS-95-10
IS-95 Long Code Generator (LONGCD95)

LONGCD95
NB Number of bits None 100 [0,INF)/Integer
BR Output bit rate MHz 1.2288 [0,INF)/Real
INITIAL_CONTENT Initial contents of the shift None 1 [0,INF)/Integer

register in decimal
File Name of the external file with None Required String

the tap connections of the shift
register
Ports
Notes
1. File name must have a “.dsp” extension (See the Data Formats chapter.)
2. This model implements the IS-95 long code sequence generator.
Netlist Form
LONGCD95:Name n1 NB=val BR=val INITIAL_CONTENT=val
[Rout=Val]
CDMA/IS-95-11
Netlist Example
LONGCD95:1 1 NB=100 BR=1.2288MHz INITIAL_CONTENT=97023
References
CDMA/IS-95-12
IS-95 Reverse Traffic Channel Block Deinterleaver
IS-95 Reverse Traffic Channel Block Deinterleaver (RTCBD95)

RTCBD95
FDR Frame Data Rate Hz 9600 [1200, 9600]/Real
Ports
Notes
1. This model implements an IS-95 block deinterleaver that only supports the four tarffic rates:
1200Hz, 2400Hz, 4800Hz, and 9600Hz. The data at each rate is deinterleaved according to IS-
95 specifications (Reference 1).
Netlist Form
RTCBD95:Name n1 n2 FDR=val [Rin=Val] [Rout=Val]
Netlist Example
RTCBD95:1 1 2 FDR=9600Hz
References
CDMA/IS-95-13
IS-95 Reverse Traffic Channel Block Interleaver
IS-95 Reverse Traffic Channel Block Interleaver (RTCBI95)

RTCBI95
FDR Frame Data Rate Hz 9600 [1200, 9600]/Real
Ports
Notes
1. This model implement an IS-95 block interleaver that only supports the four traffic rates:
1200Hz, 2400Hz, 4800Hz, and 9600Hz. The first 576 symbols at each rate is interleaved
Netlist Form
RTCBI95:Name n1 n2 FDR=val [Rin=Val] [Rout=Val]
Netlist Example
RTCBI95:1 1 2 FDR=9600Hz
References
CDMA/IS-95-14
IS-95 Synchronization Channel Block Deinterleaver
IS-95 Synchronization Channel Block Deinterleaver (SYNCBD95)

SYNCBD95
Ports
Notes
1. This model implements an IS-95 block deinterleaver for the IS-95 synchronization channel
(Reference 1).
Netlist Form
SYNCBD95:Name n1 n2 [Rin=Val] [Rout=Val]
Netlist Example
SYNCBD95:1 1 2
References
CDMA/IS-95-15
IS-95 Synchronization Channel Block Interleaver
IS-95 Synchronization Channel Block Interleaver (SYNCBI95)

SYNCBI95
Ports
Notes
1. This model implements an IS-95 block interleaver for the IS-95 synchronization channel. The
first 128 symbols at a fixed rate 4800Hz are interleaved according to IS-95 specifications (Ref-
erence 1).
Netlist Form
SYNCBI9:Name5 n1 n2 [Rin=Val] [Rout=Val]
Netlist Example
SYNCBI95:1 1 2
References
CDMA/IS-95-16
Walsh Function Demodulator (WALSHDEM)

WALSHDEM
N Walsh Order None 6 [0, Inf)/Integer
RIN Input Ohm Inf (0, Inf]/Real

impedance
ROUT Output Ohm 0 [0, Inf)/Real

impedance
WF_NUM Walsh Function None 0 [0,2N-1)/Real

Number
Ports
Notes
This model interprets the incoming signal as a binary signal. An input greater than 0.5V is inter-
preted as a 1; any other input level is interpreted as a 0. The Walsh function demodulator takes 2N
samples at a time, and correlates (XORs) them with the corresponding 2N Walsh functions speci-
fied by WF_NUM. If the sum of the correlated samples is greater than 2N2, then the output is 1;
otherwise, the output is 0. The time step of the output is 2N times the size of the input step.
Netlist Form
WALSHDEM:Name n1 n2 N=val WF_NUM=val [Rin=val] [Rout=val]
CDMA/IS-95-17
Netlist Example
WALSHDEM:1 1 2 N=6, WF_NUM=24
References
CDMA/IS-95-18
Walsh Function Generator (WALSHGEN)

WALSHGEN
N Number of bits per None 6 [0, Inf)/Integer

modulation symbol
WF_NUM Number of the Walsh None 0 [0,2N-1)/Real

function
NUM_SYMBOLS Number of None 100 [0, Inf)/Integer

modulation symbols
BR Bit rate at the output MHz 1.2288 ([0, Inf)/Real
Ports
Notes
1. This model generates NUM_SYMBOL modulation symbols. Each modulation symbol is
composed of 2N bits. The modulation symbol generated is based on the Walsh function
(Reference 1) number WF_NUM which selects a modulation symbol out of 2N modulation
symbols.
Netlist Form
WALSHGEN:Name n1 N=val WF_NUM=val NUM_SYMBOLS=val BR=val
[Rout=Val]
CDMA/IS-95-19
Netlist Example
WALSHGEN 1 N=6 WF_NUM=0 NUM_SYMBOLS=100 BR=1.2288MHZ
In this example, 20 samples are read from the input signal to Output1 at n = 2 followed by 30
samples to Output2 at n = 3 followed by 20 samples to Output1 and so on until no more sam-
ples exist at the input port.
References
1. “Mobile-Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular
CDMA/IS-95-20
Walsh Function Modulator (WALSHMOD)

WALSHMOD
N Walsh Order None 6 (0, Inf)/Integer
WF_NUM Walsh Function None 0 [0,2N-1)/Real

Number
Ports
Notes
This model interprets the incoming signal as a binary signal. An input greater than 0.5V is inter-
preted as a 1; any other input level is interpreted as a 0. The Walsh Function Modulator divides the
input sample into 2N samples, each with the same amplitude as the input signal, but with a time step
that is reduced 2N times. It then correlates (XORs) them with the corresponding 2N Walsh func-
tions specified by WF_NUM to produce the output.
Netlist Form
WALSHMOD:Name n1 n2 N=val WF_NUM=val [Rin=Val] [Rout=Val]
Netlist Example
WALSHMOD:1 1 2 N=6 WF_NUM=0
CDMA/IS-95-21
References
CDMA/IS-95-22
1
Channels
Channels1-23
Additive White Gaussian Noise, Real (AWGN)

AWGN
SNR The average input dB 10 [-200, 200]/Real

power to average
noise power ratio in
dB
NSAMP The number of None 100 [1, Inf)/Integer

samples used for
signal power
measurement
SEED Random seed None 0 [0, Inf)/Integer
Ports
Notes
1. This model can be used to perform a sample-by-sample addition of a real input signal and a
zero mean White Gaussian noise.
2. Let the discrete input signal a t =lTs (l = 0, 1, 2, ...) be x(l) , where Ts is the sampling interval.
Channels1-24
And let the zero mean White Gaussian noise be n(l). Then the output signal can be expressed
as
z (l ) = x (l ) + n (l ) (1)
3. The average power of the input signal is defined by
1 N −1
∑ [x (l )]
2
Pin =
N l =0 (2)
where N is the number of samples to calculate average power, i.e., the parameter NSAMP of
this model. Thus, the average noise power can be given by
Pin
Pnoise = SNR
10 10 (3)
Therefore, a zero mean noise with variance Pnoise will be randomly generated and added to the
input signal.
Netlist Form
AWGN:NAME n1 n2 SNR=val [NSAMP=val] [SEED=val] [RIN=val]
[ROUT=val]
Example
AWGN:1 1 2 SNR=10
Channels1-25
Additive White Gaussian Noise with Average Input
Additive White Gaussian Noise with Average Input Power, Real

(AWGNIP)
AWGNIP
SNR The average input dB 10 [-200, 200)/Real

power to average
dB
RIN1 Input1 impedance Ohm Inf (0, Inf]/Real
RIN2 Input2 impedance Ohm 0 (0, Inf]/Real
Ports
Input1 Input1 signal (real)
Input2 Average input power (real)
Notes
1. This model can be used to perform a sample-by-sample addition of a real input signal and a
Channels1-26
zero mean White Gaussian noise.

2. Let the discrete input signal at t = lTS (l = 0, 1 2) be x(l), where Ts is the sampling interval. And
let the zero mean White Gaussian noise be n(l). Then the output signal can be expressed as
z (l ) = x (l ) + n (l ) (1)
3. The average power of the input signal can be obtained at the second input. Define that Tp is the
sample interval at this input. Assuming the current sample at the first input is x(l), we use the
kth sample at the second input port as the input power Pin if kTp ≤ l .Ts ≤ (k+1) . Tp. Thus,
the average noise power can be given by
Pin
Pnoise = SNR
10 10 (2)
Therefore, a zero mean noise with variance Tnoise will be randomly generated and added to the
input signal.
Netlist Form
AWGNIP:NAME n1 n2 n3 SNR=val [SEED=val] [RIN1=val] [RIN2=val]
[ROUT=val]
Netlist Example:
AWGNIP:1 1 2 3 SNR=10
Channels1-27
Additive White Gaussian Noise, Complex (CAWGN)

CAWGN
SNR The average input dB 10 [-200, 200]/Real

power to average
dB
NSAMP The number of None 100 [1, Inf)/Integer

samples used for
signal power
measurement
Ports
Input Input signal in complex envelope format (complex)
Output Output signal in complex envelope format (complex)
Notes
1. This model can be used to perform a sample-by-sample addition of a complex input signal and
a complex zero mean White Gaussian noise.
Channels1-28
2. Let the discrete input signal at t = lTS (l = 0, 1 2) be

x(l ) = xr (l ) + jxi (l ) (1)
where Ts is the sampling interval. And let the complex zero mean White Gaussian noise be
n (l ) = nr (l ) + jni (l ) (2)
then the output signal can be expressed as
z (l ) = x (l ) + n (l ) = [x r (l ) + ni (l )] + j[x r (l ) + ni (l )] (3)
3. The average power of the input signal is defined by
∑ {[xr (l )] + [xi (l )] }
1 N −1
2 2
Pin =
Nl =0 (4)
where N is the number of samples to calculate average power, i.e., the parameter NSAMP of
this model. Thus, the average noise power can be given by
Pin
Pnoise = SNR
10 10 (5)
Therefore, a complex noise with zero mean and variance Pnoise will be randomly generated and
added to the complex input signal.
Netlist Form
CAWGN:NAME n1 n2 SNR=val [NSAMP=val] [SEED=val] [RIN=val]
[ROUT=val]
Netlist Example:
CAWGN:1 1 2 SNR=10
Channels1-29
Additive White Gaussian Noise with Average Input Power, Complex

(CAWGNIP)
CAWGNIP
SNR The average input None 10 [-200, 200]/Real

power to average
dB
Ports
Input1 Input signal in complex envelope format (complex)
Input2 Average input power (real)
Notes
1. This model can be used to perform a sample-by-sample addition of a complex input signal and
Channels1-30
a complex zero mean White Gaussian noise.

2. Let the discrete input signal at
t = l Ts (l = 0,1, 2,…) be
x(l ) = xr (l ) + jxi (l ) (1)

where Ts is the sampling interval. And let the complex zero mean White Gaussian noise be
n (l ) = nr (l ) + jni (l ) (2)
then the output signal can be expressed as
z (l ) = x (l ) + n (l ) = [x r (l ) + ni (l )] + j[x r (l ) + ni (l )] (3)
3. The average power of the input signal can be obtained at the second input. Define Ts to be the
sample interval at this input. Assume the current sample at the first input is x(l), we use the kth
sample at the second input port as the input power Pin if kTs ≤ lTs≤ (k+1)Ts. Thus, the aver-
age power of the noise can be given by
Pin
Pnoise = SNR
10 10 (4)
Therefore, a complex noise with zero mean and variance Pnoise will be randomly generated and
added to the input signal.
Netlist Form
CAWGNIP:NAME n1 n2 n3 SNR=val [SEED=val] [RIN1=val]
[RIN2=val] [ROUT=val]
Netlist Example
CAWGNIP:1 1 2 3 SNR=10
Channels1-31
Multipath Channel, Constant Gains and Integer
Multipath Channel, Constant Gains and Integer Delays (MNCH)

MNCH
L Number of paths None 3 [1, 12]/Integer
D1 Delay of first path None 0 [0, Inf)/Integer

(samples)
Gain1 Magnitude of the None 1 [0, Inf)/Real

compex gain factor
for first path
Phase1 Phase of the Degree 0 [-180, 180]/Real

complex gain
factor for the first
path
D2 ~ D12 Multipath delays of None 0 [0, Inf)/Integer

all other paths
(samples)
Gain2 ~ Gain12 Magnitude of the None 0 [0, Inf)/Real

complex gain
factor of all other
paths, in dB
Phase2 ~ Phase of the Degree 0 [-180, 180)/Real

Phase12 complex gain
factor of all other
paths
Channels1-32
Multipath Channel, Constant Gains and Integer
Ports
Output Multipath nonfading signal in complex envelope format

(complex)
Notes
1. This model can be used to simulate a Multipath Nonfading Channel with Integer Delays in
samples.
2. Representing the RF channel as a time-variant channel and using a base-band complex enve-
lope representation, the channel gain factor is specified by:
L−1
h (t ) = ∑ Gaini e j Phasei δ (t − τ i )
i =0 (1 ≤ L ≤ 12) (1)
where L is the number of paths, Gaini and Phasei are magnitude and phase of the complex gain
for the ith path, τi >= 0 is the channel delay which can be expressed by Di samples.
Netlist Form
MNCH:NAME n1 n2 L=val D1=val Gain1=val Phase1=val
[D2=val . . . Phase12=val] +[RIN=val] [ROUT=val]
Netlist Example
MRFCH:1 1 2 L=2 D1=0 Gain1=1.0 Phase1=0DEG D2=2 Gain1=0.2
Phase1=30DEG
Channels1-33
Multipath Rayleigh Fading Channel (MRFC)

MRFC
FD Doppler frequency Hz 1 (0, Inf)/Real
T1 Delay of first path Sec 0 [0, Inf)/Real

in seconds
RP1 Relative power of None -1e+020 (-Inf, 0]/Real

first path in dB
T2, ..., T12 Delay of all other Sec 0 [0, Inf)/Real

paths in seconds
(optional)
RP2, ..., Relative power of None -1e+020 (-Inf, 0]/Real

RP12 all other paths in
dB
Ports
Input Unfaded input signal (complex)
Output Faded output signal (complex)
Channels1-34
Notes
1. This model can be used to simulate a Multipath Rayleigh Fading Channel.
2. In general, let the input signal be given by
Vin (t ) = A(t ) cos(2πf c t + θ (t ) ) (1)
Physically speaking, multipath fading implies that several delayed replicas or “images” of the
above input (transmitted) signal will be received with each image having a different level of
attenuation.
Mathematically, the output signal Vout will be given by (assuming all 12 path delays and rela-
tive powers are specified)
N
Vout (t ) = ∑ α i (t ) A(t - Ti ) cos (2πf c (t − Ti ) + θ (t − Ti ) ) 1 ≤ N ≤ 12
i =1 (2)
where Ti is the delay along the ith path and αi(t) is the attenuation (fading) along the ith path.
The attenuation process αi(t) 1 ≤ i ≤ 12 is a time varying random process and Rayleigh dis-
tributed. The average value of the power loss, i.e., E{α2i (t)} along the ith path is related to the
relative power RPi along this path by the equation
RPi =
{
E α i2 (t ) }
Reference Power Loss (3)
If the reference power loss is assumed to be 0dB, then
{
RPi = E α i2 (t ) }
In addition, this model will always ensure that the combined power loss (along all the specified
fading paths) is normalized to unity, i.e.,
N
∑ RPi = 1, 1 ≤ N ≤ 12
i =1 (4)
3. The remaining discussion will focus on how each of the random attenuation processes ai(t) is
generated.
Two correlated Gaussian noise processes are generated for each fading path (in-phase and
quadrature) by filtering a White Guassian noise process through a filter which has the follow-
ing frequency response:
 1
 f < FD
2

H ( f ) =  4 1 − 
f 

  FD 
 0 elsewhere

Channels1-35
where FD is the Doppler frequency and is related to the receiver's speed Vr by the equation:
Vr = FD x λ , where λ is the wavelength of the carrier frequency (fc), and is given by λ = c/fc,
where c is the speed of light (3 x 108 m/s).
The frequency spectrum of the fading process is S(f) = H(f) H*(f). This frequency response is
generated in the FFT domain using FFTL = 2048 points. Each FFT point (0, j ≤ 1 ≤ FFTL -
1) corresponds to a certain frequency (Freq) by means of the following equation:
f = j ⋅ f s (6)
where fs is the frequency sampling interval typically chosen to be on the order of FD/10. The
above frequency response has an even real part and an odd imaginary part to guarantee that the
filtering process will yield a real in-phase and quadrature correlated Gaussian processes. Each
two generated Gaussian processes are combined to yield a Rayleigh fading process. It is
important to point out that each generated in-phase and quadrature process is correlated but the
two processes are generated independently and therefore, uncorrelated.
Each generated Rayleigh fading process corresponds to a path with a user-specified delay and
relative power (Ti and RPi, 1≤ i≤ 12 ). The expected output along the ith fading path should be
the input signal delayed by Ti seconds and Rayleigh-faded in accordance (and on average) with
the specified ith relative power, RPi. The total average power contribution from all paths is
always normalized to unity. This is accomplished by setting the standard deviation of the ith
generated in-phase and quadrature correlated Gaussian processes to
σ i = (RP i ) σ
, 1 ≤ i ≤ 12 (7)
where
σ =1 2(RP1 + RP2 + ..... + RP12 )
The resolution of the generated fading process is further increased in the time domain to match
the sampling rate of the input signal. This is accomplished by linearly interpolating the fading
process (i.e., inserting fading points between each two originally generated fading points.).
Netlist Form
MRFC:NAME n1 n2 FD=val [SEED=val] T1=val RP1=val
[T2=val . . . RP12=val] [RIN=val] [ROUT=val]
Netlist Example:
MRFC:1 1 2 FD=50Hz SEED=48568 T1=0S RP1=0 T2=5US RP2=-2.0
References
1. W. C. Jakes, Microwave Mobile Communications, New York: Wiley, 1974.
2. T. S. Rappaport, Wireless Communications: Principles and Practice, Prentice-Hall, 1996.
3. W Raymond Steele, Mobile Radio Communications, Pentech Press, 1992.
4. J. I. Smith, "A computer generated multipath fading simulation for mobile radio,” IEEE Trans.
Channels1-36
Vehic Technol., vol. VT-24, no. 3, pp. 39-40, Aug. 1975.
Channels1-37
Multipath Rayleigh Fading Channel, Integer Delays
Multipath Rayleigh Fading Channel, Integer Delays (MRFCH)

MRFCH
L Number of Paths None 3 [1, 12]/Integer
VM Mobile velocity None 12 (0, Inf)/Integer

real in km/hour
D1 Delay of first None 0 [0, Inf)/Integer

path (samples)
P1 Relative of first None -1e+020 (-Inf, 0]/Real

path in dB
D2, ..., D12 Delays of all None 0 [0, Inf)/Integer

other paths
(samples)
P2, ..., P12 Relative power of None -1e +020 (-Inf, 0]/Real
all other paths in
dB
RIN Output Ohm Inf (0, Inf]/Real

impedance

impedance
Channels1-38
Ports
Output Multipath Rayleigh fading signal in complex envelope format

(complex)
Notes
1. This model can be used to simulate a Multipath Rayleigh Fading Channel with Integer Delays
in samples.
2. The Doppler power spectrum for Multipath Rayleigh Fading Channel is given by [1][2]:
−1 2
 3b   f − f c 2 
 1 −    f − fc < fm
S Ez ( f ) =  ω m   f m  

 0 others
(1)
where b is the average received power, fm = ωm/2π is the maximum Doppler shift given by Vm/
2λ where Vm is mobile velocity and λ is the wavelength of the transmitted signal at frequency
fc.
lope representation, the channel impulse response can be expressed as
L −1
h (t ) = ∑ α i (t )e jϕi (t )δ (t − τ i )
i =0 (1 ≤ L ≤ 12) (2)
where L is the number of paths, the amplitude αi(t) for the ith path is a Rayleigh distributed
random variable, the phase shift φi is uniformly distributed,τi > = 0 is the channel delay. Since
the Rayleigh fading processes αi(t) exp[(jφi(t)] is complex, the in-phase process and quadra-
Channels1-39
ture process for each path are implemented separately, as shown in Fig.1.
H( f )
White Gaussian
noise samples FFT IFFT
− fm 0 fm
x (n )
H( f )
White Gaussian
− fm 0 fm
Fig. 1 Block diagram of Rayleigh fading simulator
Based on Eqn.(2), both the in-phase process and the quadrature process can be generated by
passing a White Gaussian noise process through a baseband filter which has the following fre-
quency response:
   f  2  −1 4
 K 1 −    f < fm
H ( f ) =    f m  

 0 others (3)
where Kis constant to normalize the frequency response. The above frequency response is gen-
erated in the frequency domain using FFT with length = 2048 points. Each point (0 ≤ k ≤
length-1) corresponds to a certain frequency (fk) by means of the following equation:
f k = k × f s (4)
where fs is the frequency sampling interval typically chosen to be on the order of fm /10.
The above frequency response has an even real part and an odd imaginary part to guarantee
that the filtering process will generate a real in-phase and quadrature correlated Gaussian pro-
cesses. Each two generated Gaussian processes are combined to generate a Rayleigh fading
process. It is important to point out that whether in-phase process or quadrature process is cor-
related among different points but the two processes are generated independently and there-
fore, uncorrelated.
4. Assume that channel delay for each path can be expressed by Di samples. Each generated Ray-
leigh fading process corresponds to a path with a user-specified delay Di and relative
power Pi, (0 ≤ i ≤ L-1). The expected output along the ith fading path should be the input sig-
Channels1-40
nal delayed by Di samples and Rayleigh-faded with the specified ith relative power Pi. The
total average power contribution from all paths is always normalized to unity. This is accom-
plished by setting the standard deviation of the ith generated in-phase and quadrature corre-
lated Gaussian processes to
P
σi = i
L −1
2∑ Pl
l =0 (5)
These time series of the generated fading process is further increased in the time domain to
match the sampling rate of the input signal. This is accomplished by linearly interpolating the
fading process (i.e., inserting fading points between each two originally generated fading
points).
Netlist Form
MRFCH:NAME n1 n2 L=val VM=val [SEED=val] D1=val P1=val
[D2=val . . . P12=val] [RIN=val] [ROUT=val]
Netlist Example
MRFCH:1 1 2 L=2 D1=0 P1=0 D2=2 P2=-2.0
References
Channels1-41
2
Coders/Decoders
Coders/Decoders2-42
Convolutional Coder (CCOD)

CCOD
N Number of bits to None 2 [1, 8]/Integer

generate at the
output for each K
input bits
K Number of input None 1 [1, 8]/Integer

bits to be shifted
into shift register at
each step.
L Constraint length None 5 [2, Inf)/Integer

of convolutional
coder
T True output value None 1 (-Inf, Inf)/Real
F False output value None 0 (-Inf, Inf)/Real
G1, G2 Generators of None 0 [0, Inf)/Integer

, ..., G8 convolutional
coder (specified in
decimal)
RIN Input impedance Ohm 0 (0, Inf]/Real
Coders/Decoders2-43
Ports
Input Binary input sequence (integer)
Output Convolutionally coded binary sequence (real)
Limits
0 < K × L ≤ 32
Notes
1. This model takes a binary input sequence and outputs a convolutionally encoded binary
sequence according to the specified parameters of the model. In this model, every K input bits
are encoded into N output bits. The length of the shift register in this convolutional coder is
K x L, where L is the constraint length. Therefore, a convolutional coder is always denoted as
CCOD(N, K, L). The rate of the convolutional coder is given by the ratio K/N.
2. The N (N ≤ 8) output bits which are generated from each K input bits are determined by a set of
binary generators G1,G2,...GN (specified in a decimal value).
3. G1 is used to generate the first bit of the N bits, G2 is used to generate the second bit of the N
bits and so on. The binary representation of each generator is the same length as the shift regis-
ter, K x L.
4. For each K input bits, the contents of the K x L shift register are shifted by K bits to the right
and new N bits are generated. The initial content of the shift register is always assumed to be K
x L binary zeros
5. The ratio of the output bit rate to the input bit rate is given by N/K.
Netlist Form
CCOD:NAME n1 n2 N=val K=val L=val [T=val] [F=val] [G1...N=val]
[RIN=val] [ROUT=val]
Netlist Example
CCOD:1 1 2 N=2 K=1 L=7 G1=91 G2=121
References
1. J. G. Proakis, Digital Communications, McGraw-Hill, 2001.
Coders/Decoders2-44
Depuncturer (DPUNC)
Depuncturer (DPUNC)
DPUNC
N Puncturing period None 4 [1, Inf)/Integer
RIN1 Input impedance Ohm Inf (0, Inf]/Real
Ports
Input1 Received signal before depuncturing (real)
Input2 Puncturing pattern (integer)
Output The signal after depuncturing (real)
Notes
1. This model can be used to perform the inverse procedure of “Puncturing”. Depuncturing is
done by simply inserting dummy bits into the locations that were punctured at the output of
convolutional encoder. The value of dummy bits is set to “zero” in this model. Please refer to
the Puncturer model for details.
Netlist Form
DPUNC:NAME n1 n2 n3 N=val [RIN1=val] [RIN2=val] [ROUT=val]
Coders/Decoders2-45
Depuncturer (DPUNC)
Netlist Example
DPUNC:1 1 2 3 N=6
References
Coders/Decoders2-46
Interleaving Pattern Generator (INTLVPTN)

INTLVPTN
TYPE Prime number interleaver {0} None 0 [0, 1]/Integer

3GPP FDD Turbo code interleaver {1}
K Interleaving period None 65536 [2, Inf)/Integer
P Prime number, only for TYPE= 0 None 257 [1, Inf)/Integer
SAMPLE_RATE Output sample rate in Hz Hz 1000 [1, Inf)/Integer
ROUT output Impedance Ohm 0 (0, Inf)/Real
Ports
Output Prime number interleaving pattern sequence (integer)
Notes
1. This model can be used to generate interleaving pattern sequence with the length of K.
2. Denote by i the index of the input sequence before interleaving and f(i) shall be the index of
output sequence after interleaving, then the interleaving pattern sequence is expressed as, f(0),
f(1), f(K-1) .
3. The prime number interleaver is defined by the rule
f (i ) = (P × i ) mod (K ) 0 ≤ i ≤ K − 1
where P is a prime number, K is the interleaving period.
4. The 3GPP FDD Turbo code internal interleaver
Coders/Decoders2-47
The Turbo code internal interleaver consists of bits-input to a rectangular matrix with padding,
intra-row and inter-row permutations of the rectangular matrix, and bits-output from the rect-
angular matrix with pruning. The bits input to the Turbo code internal interleaver are denoted
by x1, x2, x3, ..., xK where K is the integer number of the bits and takes one value of 40 ≤ K ≤
5114. The relation between the bits input to the Turbo code internal interleaver and the bits
input to the channel coding is defined by and K = Ki
Bits-input to rectangular matrix with padding
The bit sequence x1, x2, x3, ..., xK input to the Turbo code internal interleaver is written into
the rectangular matrix as follows.
[1] Determine the number of rows of the rectangular matrix, R, such that:
 5, if ( 40 ≤ K ≤ 159)

R =  10, if ((160 ≤ K ≤ 200) or ( 481 ≤ K ≤ 530))
 20, if ( K = any other value)
The rows of rectangular matrix are numbered 0, 1, …, R - 1 from top to bottom.
[2] Determine the prime number to be used in the intra-permutation, p, and the number of col-
umns of rectangular matrix, C, such that:
If (481 ≤ K ≤ 530) then p = 53 and C = p.

else
Find minimum prime number p from Table 1 such that K ≤ R x (p+1)
and determine C such that:
 p − 1 if K ≤ R × ( p − 1)

C= p if R × ( p − 1) < K ≤ R × p
 p + 1 if R × p < K

The columns of rectangular matrix are numbered 0, 1, …, C - 1 from left to right.
Table 1: List of prime number p and associated primitive root v :

p v p v p v p v p v
7 3 47 5 101 2 157 5 223 3

11 2 53 2 103 5 163 2 227 2
13 2 59 2 107 2 167 5 229 6
17 3 61 2 109 6 173 2 233 3
Coders/Decoders2-48
19 2 67 2 113 3 179 2 239 7

23 5 71 7 127 3 181 2 241 7
29 2 73 5 131 2 191 19 251 6
31 3 79 3 137 3 193 5 257 3
37 2 83 2 139 2 197 2
41 6 89 3 149 2 199 3
43 3 97 5 151 6 211 2
[3]Write the input bit sequence x1, x2, x3, ..., xK into the R X C rectangular matrix row by row
starting with bit y1 in column 0 of row 0:
 y1 y2 y3 … yC 
 y y (C + 2) y ( C + 3) … y 2C 
 (C +1)
 … 
 
 y (( R −1)C +1) y (( R −1)C + 2) y (( R −1)C +3) … y R×C 
where yk = xk for k = 1, 2, …, K and if R X C > K, the dummy bits are padded such that yk = 0
or 1for k = K + 1, K + 2, …, R X C. These dummy bits are pruned away from the output of the
rectangular matrix after intra-row and inter-row permutations.
Intra-row and inter-row permutations
After the bits-input to the R X C rectangular matrix, the intra-row and inter-row permutations
for the R X C rectangular matrix are performed stepwise by using the following algorithm with
steps (1) – (6):
[1] Select a primitive root v from Table 1, which is indicated on the right side of the prime
number p.
[2]Construct the base sequence <s(j)> jε{0, 1, ...,p-2} for intra-row permutation as:
s(j) = (ν x s(j-1))mod p, j = 1, 2,…, (p - 2), and s(0) = 1.
[3] Assign q0 = 1 to be the first prime integer in the sequence <qi>iε{0, 1, ...,R-1} , and determine
the prime integer qi in the sequence <qi>ιε{0, 1, ...,R-1} to be a least prime integer such that
g.c.d(qi, p - 1) = 1, qi > 6, and qi > q(i - 1) for each i = 1, 2, …, R – 1. Here g.c.d. is greatest
common divisor.
[4] Permute the sequence <qi>iε{0, 1, ...,R-1 to make the sequence <ri>iε{0, 1, ...,R-1} such that rT(i)
T (i ) i∈{0,1, , R −1}
= qi, i = 0, 1, …, R - 1, where is the inter-row permutation pattern defined as
Coders/Decoders2-49
the one of the four kind of patterns, which are shown in Table 2, depending on the number of
input bits K.
Table 2: Inter-row permutation patterns for Turbo code internal interleaver

Number of input bits Number of rows Inter-row permutation patterns
K R <T(0), T(1), …, T(R - 1)>
(40≤K≤159) 5 <4, 3, 2, 1, 0>
(160≤K≤200) or (481≤K≤530) 10 <9, 8, 7, 6, 5, 4, 3, 2, 1, 0>
(2281≤K≤2480) or 20 <19, 9, 14, 4, 0, 2, 5, 7, 12, 18, 16,

(3161≤K≤3210) 13, 17, 15, 3, 1, 6, 11, 8, 10>
K = any other value 20 <19, 9, 14, 4, 0, 2, 5, 7, 12, 18, 10,

8, 13, 17, 3, 1, 16, 6, 15, 11>
[5] Perform the i-th (i = 0, 1, …, R - 1) intra-row permutation as:
If (C = p) then
U i ( j ) = s (( j × ri ) mod( p − 1)) , j = 0, 1, …, (p - 2), and U (p - 1) = 0,
i
where Ui(j) is the original bit position of j-th permuted bit of i-th row.
if (C = p + 1) then
U i ( j ) = s (( j × ri ) mod( p − 1)) , j = 0, 1, …, (p - 2). U (p - 1) = 0, and U (p) = p,
i i
where Ui(j) is the original bit position of j-th permuted bit of i-th row,
and if (K = R X C) then exchange UR-1(p) with UR-1(0).
If (C = p - 1) then
U i ( j ) = s(( j × ri ) mod( p − 1)) − 1 ,
j = 0, 1, …, (p - 2),
where Ui(j) is the original bit position of j-th permuted bit of i-th row.
[6] Perform the inter-row permutation for the rectangular matrix based on the pattern
T (i ) i∈{0,1, , R −1}
, where T(i) is the original row position of the i-th permuted row.
Coders/Decoders2-50
Bits-output from rectangular matrix with pruning
After intra-row and inter-row permutations, the bits of the permuted rectangular matrix are
denoted by y'k:
 y '1 y ' ( R +1) y ' ( 2 R +1) … y ' ((C −1) R +1) 
 y' y ' ( R + 2) y ' ( 2 R + 2) … y ' ((C −1) R + 2) 
 2
 … 
 
 y' R y'2R y '3 R … y ' C× R 
The output of the Turbo code internal interleaver is the bit sequence read out column by col-
umn from the intra-row and inter-row permuted R X C rectangular matrix starting with bit y'1
in row 0 of column 0 and ending with bit y'CR in row R - 1 of column C - 1. The output is
pruned by deleting dummy bits that were padded to the input of the rectangular matrix before
intra-row and inter row permutations, i.e. bits y'k that corresponds to bits yk with k > K are
removed from the output. The bits output from Turbo code internal interleaver are denoted by
x'1, x'2, …, x'K, where x'1 corresponds to the bit y'k with smallest index k after pruning, x'2 to the
bit y'k with second smallest index k after pruning, and so on. The number of bits output from
Turbo code internal interleaver is K and the total number of pruned bits is: R X C – K.
Netlist Form
INTLVPTN:NAME n1 [TYPE= val] K=val [P=val] [SAMPLE_RATE=val]
[ROUT=val]
Netlist Example
INTLVPTN:1 1 K = 636 P = 59 SAMPLE_RATE = 1khz
References
3GPP TS 25.212 “Multiplexing and channel coding (FDD)
Coders/Decoders2-51
Puncturer (PUNC)
Puncturer (PUNC)
PUNC
N Puncturing period None 4 [1, Inf)/integer
Ports
Input1 Received signal before puncturing (real)
Output The signal after puncturing (real)
Notes
1. This model can be used to increase coding rate by employing “puncturing”. Puncturing is a
procedure for deleting some of the encoded bits at the output of a convolutional encoder.
2. Puncturing pattern is a N-bit sequence with taking the value 1 or 0. When the value is 1, the
corresponding output of a convolutional encoder is transmitted. When the value is 0, the corre-
sponding output of a convolutional encoder is deleted.
Netlist Form
PUNC:NAME n1 n2 n3 N=val [RIN1=val] [RIN2=val] [ROUT=val]
Coders/Decoders2-52
Puncturer (PUNC)
Netlist Example
PUNC:1 1 2 3 N=6
References
Coders/Decoders2-53
Reed-Solomon Coder (RSCOD)

RSCOD
N Codeword length None 204 [3, 65335]/

Integer
K Data length in each None 188 [1, 65335]/

codeword Integer
M Size of the Galois None 8 [2, 16]/

Field Integer
B0 First root of the None 1 [0, 653345]/

generator Integer
polynomial
P0, P1, ..., Pm Coefficients of the None 101110001 [0, 1]/Integer

primitive
polynomial
Ports
Input Input symbol sequence (integer)
Output Reed Solomon coded output sequence (integer)
Coders/Decoders2-54
Limits
3 ≤ N ≤ 2M − 1
1≤ K ≤ N −2
0 ≤ B0 ≤ N − 1
Notes
This model is used to perform Reed-Solomon (RS) encoding. RS codes are a non-binary sub-
class of the BCH block codes. The code format is RS(n,k) defined on Galois Field (2m). The
error correcting capability of the RS(n,k) code is defined by t = (n-k)/2, which means this code
can correct up to t = (n-k)/2 errors.
The RS coder adds a sequence of 2t parity code symbols to each k input data symbols to form a
codeword with n = 2m-1 symbols. However, RS(n,k) can be shorten into RS(n-j, k-j) by simply
forcing j leading input data symbols to be zeros, and then deleting these zero symbols from a
systematic codeword.
For example, the digital satellite communications Reed-Solomon (RS) coder/decoder

RS(204,188), is the shortened length of the RS(255,239) Reed-Solomon code. This shortened
code is formed by 188 input data symbols, plus 51 additional zero-padded symbols, before
encoding with the RS(255,239). The transmitted codeword doesn’t contain the padding
sequence which is rebuilt in RS decoder.
At the output of the RS coder, the data is left unchanged and the parity codes are appended as
shown in Fig.1. In this model, the parity codes are transmitted first.
2t k
Parity Codes Data
n
Fig.1: Codeword for systematic Reed-Solomon code
(1) Galois Field Arithmetic
Reed-Solomon codes are based on a specific area of mathematics known as Galois Field,
which is set up according to the number of bits per symbol and the number of symbols per
block (i.e., codeword). The elements of the Galois Field GF(2m) are generated from the mth
degree irreducible primitive polynomial with the smallest number of terms. The primitive
polynomial of degree m can be written in the form:
Coders/Decoders2-55
P ( X ) = P0 + P1 X + P2 X 2 + … + Pm X m (1)
Table I. List of primitive polynomials

m m
3 1+X+X3 10 1+X3+X10
4 1+X+X4 11 1+X2+X11
5 1+X2+X5 12 1+X+X4+X6+X12
6 1+X+X6 13 1+X+X3+X4+X13
7 1+X3+X7 14 1+X+X6+X10+X14
8 1+X2+X3+X4+X8 15 1+X+X15
9 1+X4+X9 16 1+X+X3+X12+X16
The elements if Galois Field GF(2m) can have two representations: power representation and
polynomial representations. Let α represent the root of the primitive polynomial P(X). Each
power representation αi, where
0 ≤ i ≤ 2m − 2 ,
for elements of Galois Field GF(2m) can be expressed as
α i = ai 0 + ai1α + ai 2α 2 + … + ai , m −1α m −1
(2)
where the binary vector {ai0, a1i, ..., ai,m-1} is the polynomial representation of αi. The power
representation is convenient for multiplication and the polynomial representation is convenient
for addition.
(2) Generator polynomial
The generator polynomial of Reed-Solomon code is generally defined as
( )( ) (
g ( X ) = X + α b0 X + α b0 +1 … X + α b0 +2 t −1 (3) )
where t is the correctable error number. For the special case of b0 =1, the above equation will
be simplified into
( ) (
g ( X ) = ( X + α ) X + α 2 … X + α 2 t (4) )
The generator polynomial can also be expressed as a 2t order of polynomial
g ( X ) = g 0 + g1 X + g 2 X 2 + … + g 2 t −1 X 2 t −1 + X 2 t (5)
(3) Encoding
2. In the Reed-Solomon code, all generated codewords are exactly divisible by the generator
polynomial. Let
Coders/Decoders2-56
a ( X ) = a0 + a1 X + a 2 X 2 + … + a k −1 X k −1 (6)
be the input data to be encoded, where k= n-2t. The parity check codes will be the coefficients
of the remainder, b(X) = b0 +b1X +...+b2t-1X2t-1 resulting from dividing the input data polyno-
mial X2t a(X) by the generator polynomial g(X). These parity codes are then joined to the data
symbols to form the transmitted codeword. The RS encoding procedure can be accomplished
by using a division circuit as shown in Fig.2
Gate
g0 g1 g 2t −2 g 2 t −1
b0 b1 b2t −2 b2 t −1
Parity
X 2t a ( X )
Codeword
Data
Fig.2 Encoding diagram for systematic Reed-Solomon code

Netlist Form
RSCOD:NAME n1 n2 N=val K=val M =val [B0 =val] [P0=val . . .
PM=val] [RIN=val] [ROUT=val]
Netlist Example
RSCOD:1 1 2 N=204 K=188 M =8 B0 =1 {P0,…P8} =
{1,0,1,1,1,0,0,0,1}
References
1. James J. Spilker, Digital Communications by satellite, Prentice-Hall, 1977.
2. Shu Lin and D.J.Costello, Error Control Coding: Fundamentals and applications, Prentice-
Hall, 1983.
3. Y.Shayan, T.Le-Ngoc and V.Bhargava, “A versatile time-domain Reed-Solomon decoder,”
IEEE Journal on Selected Areas in Communications, vol. 8, No.8, pp.1535-1542, Oct. 1990.
Coders/Decoders2-57
Reed-Solomon Decoder (RSDEC)

RSDEC
N Codeword length None 204 [3, 65335]/Integer
K Data length in each None 188 [1, 65335]/Integer

codeword
M Size of the Galois Field None 8 [2, 16]/Integer
B0 First root of the None 1 [0, 653345]/Integer

generator polynomial
P0, P1, ..., Pm Coefficients of the None 101110001 [0, 1]/Integer

primitive polynomial
RIN Input impedance Ohm Inf [0, Inf)/Real
ROUT1 Output impedance Ohm 0 [0, Inf)/Real
Ports
Input Received signal to be decoded (real)
Output1 Reed-Solomon decoded sequence (integer)
Coders/Decoders2-58
Output2 Error indicator (integer)
Limits
2 ≤ M ≤ 16
3 ≤ N ≤ 2M − 1
1≤ K ≤ N −2
0 ≤ B0 ≤ N − 1
Notes
This model is used to perform Reed-Solomon (RS) decoding. A systematic RS(n,k) code,
which is defined on Galois Field (2m), consists of k input data symbols and (n-k) parity code
symbols. For details about RS coding, please refer to the rscod model. A general architecture
for RS decoder is shown in Fig.1
Error Error
r( X ) Syndrome Si Polynomial σ ( X ) Locations βl Error e jl Error c( X )
Input Calculation Berlekamp's Chien Values Correction Output
Algorithm Search
Fig.1: Codeword for systematic Reed-Solomon coder
r(x) Received codeword

βl Error locations
Si Syndromes
eji Error values
σ(X) Error location polynomial
c(x) Corrected codeword
A Reed-Solomon decoder attempts to identify the positions and values of up to

t = (n-k)/2 errors and then correct the errors. In case of shortened codes, the appropriate
sequence of zero-padding is first rebuilt so that the codeword is equal to 2m-1.
Let v(x) be the transmitted code vector,
Coders/Decoders2-59
v ( X ) = v0 + v1 X + v2 X 2 + … + vn −1 X n −1 (1)
and r(x) be the corresponding received vector,
r ( X ) = r0 + r1 X + r2 X 2 + … + rn −1 X n −1 (2)
The error pattern, e(X) ,is added by the channel,
e( X ) = r ( X ) − v ( X ) = e0 + e1 X + e2 X 2 + … + en −1 X n −1 (3)
where e(X) is an element from GF(2m). Considering the number of elements, ν, in the error
pattern, e(X), at the location Xj1,Xj2 , …,Xjν with 0<= jν <= n-1, we have
e( X ) = e j1 X j1
+ e j2 X j2
+ … + e jν X jν
(4)
Explanation of decoding process for RS codes:
(1) Syndrome Calculation
A Reed-Solomon codeword has 2t syndromes, which can be calculated by substituting the 2t
roots of the generator polynomial g(X) into r(X), i.e., Si = r(ab0 +i -1), where i= 1,2,...2t.
(2) Determination of the error-location polynomial

The syndromes are used to find the error-location polynomial. The error location polynomial is
defined as
σ (X ) = σ 0 + σ 1 X + … + σν X ν (5)
The error location polynomial has ν roots, the inverses of which indicate the error locations.
σ(X) is an undetermined polynomial and its coefficients must be determined. The Berlekamp’s
iterative algoithm is used to construct this polynomial, which is the key to RS decoding.
Now we consider the minimum degree polynomial determined at the µ-th step of iteration.
σ (µ ) ( X ) = 1 + σ 1(µ ) X + σ 2(µ ) X 2 … + σ l(µ ) X lµ

µ
(6)
where lµ is the degree of s(µ)(X) To determine σ(µ+1)(X), we compute the following quantity:
d µ = S µ +1 + σ 1(µ )S µ + σ (2µ )S µ −1 … + σ (l µ )S µ +1− l µ

µ
(7)
This quantity dµ is called the µ-th discrepancy.
To carry out the iteration of finding σ(X), we begin with Table I and proceed to fill out this
Coders/Decoders2-60
table. Assuming that we have filled out all rows up to and including theΧ row, we fill out the
µ+1-th row as follows:
(a) If dµ= 0, then σ(µ+1)(X) = σ(µ)(X) and lµ+1 = lµ
(b) If dµ is not equal to 0, find another row,ρ, prior to the µ-th row such that dρ does not equal
zero, and the number ρ-lρ in the last column of the table has the largest value. Then, σ(µ+1)(X)
is given by the following two equations:
σ (µ +1) ( X ) = σ (µ ) ( X ) + d µ d ρ−1 X (µ − ρ )σ ( ρ ) ( X )
(8) and
lµ +1 = max (lµ , l ρ + µ − ρ )
(9)
And for both cases:

d µ +1 = S µ +2 + σ 1(µ +1)S µ +1 + … + σ l(µ +1)S µ +2−lµ
µ +1
(10)
Table 1: Iterative Table for Berlekamp Algorithm (First Two Rows Filled In)
µ σ(µ)(X) dµ lµ µ - lµ
-1 1 1 0 -1
0 1 S1 0 0
... ... ... ... ..
... ... ... ... ..
... ... ... ... ..
... ... ... ... ..
Rows in this table after the first two are generated by iteratively applying the equations given
above.
If the order of the polynomial is greater than t, which means the received codeword has more
than t errors, the errors cannot be corrected and the received vector r(X) is output as is, error
indicator is set to -1. Otherwise, error indicator is the number of errors.
Coders/Decoders2-61
(3) Determination of the error-location numbers

The error location numbers βl (1<= l <= µ) are the inverses of the roots of σ(X). The roots of
σ(x) can be found simply by substituting 1, α, α2, ...αn−1 (n = 2m-1) into σ(X). Therefore, if αl
is a root of σ(X), α(n-l) is an error location number and the received rn-l is an error symbol.
(4) Calculation of the error values and correcting the received codeword
The error value at location βl = αjl is calculated based on the following equation:
e jl = β l(1− b0 )
( )
Z β l−1
∏ (1 + β i β l−1 )
ν
i =1, i ≠ l
(11)
where
Z ( X ) = 1 + (S1 + σ 1 ) X + (S 2 + σ 1S1 + σ 2 )X 2 + … + (Sν + σ 1Sν −1 + σ 2 Sν − 2 + … + σ ν )X ν

(12)
Finally, the decoding procedure is completed by the subtraction of the received vector r(X) and
the error vector e(X).
Netlist Form
RSDEC:NAME n1 n2 n3 N=val K=val M =val [B0 =val] [P0=val . . .
PM=val] +[RIN=val] [ROUT1=val] [ROUT2=val]
Netlist Example
RSDEC:1 1 2 3 N=204 K=188 M =8 B0 =1 {P0,…P8} =
{1,0,1,1,1,0,0,0,1}
References
1. Shu Lin and D.J.Costello, Error Control Coding: Fundamentals and applications, Prentice-
Hall, 1983.
2. Elwyn Berlekamp, Algebraic Coding Theory, McGraw-Hill, New York, 1968.
3. Y.Shayan, T.Le-Ngoc and V.Bhargava, “A versatile time-domain Reed-Solomon decoder,”
IEEE Journal on Selected Areas in Communications, vol. 8, No.8, pp.1535-1542, Oct. 1990.
Coders/Decoders2-62
Reed-Solomon Addition (RSERRADD)

RSERRADD
N Codeword length None 204 [3, 65535]/Integer
K Data length in each None 188 [1, 65535]/Integer

codeword
M Size of the Galois None 8 [2, 16]/Integer

Field
ERR_K Number of errors to None 0 [0, 65533]/Integer

be set in data length
ERR_T Number of errors to None 0 [3, 65534]/Integer

be set in parity
code
Seed Start value of the None 0 [0, Inf)/Integer

random number
generator
RIN Input impedance Ohm Inf (0, Inf)/Real
Ports
Input Input sequence (real)
Output Output sequence (real)
Coders/Decoders2-63
Limits
2 ≤ M ≤ 16
3 ≤ N ≤ 2M − 1
1≤ K ≤ N −2
0 ≤ B0 ≤ N − 1
0 ≤ ERR _ K ≤ K
0 ≤ ERR _ T ≤ N − K
Notes
1. This model is used to randomly set error locations and values in Reed-Solomon (RS) code-
word.
Netlist Form
RSERRADD:NAME n1 n2 N=val K=val M =val [ERR_K =val] [ERR_T
=val] [SEED =val]+ [RIN=val] [ROUT=val]
Netlist Example
RSERRADD:1 1 2 N=204 K=188 M =8 ERR_K =0 ERR_T =0
Coders/Decoders2-64
Turbo Coder with PCCC (TCODPCCC)

TCODPCCC
K Number of information bits None 65536 [1, Inf)/integer

in each code block
L1 Constraint length in the first None 5 [2, 32)/integer

RSC coder
L2 Constraint length in the None 5 [2, 32)/integer

second RSC coder
G1 Denominator of generator for None 19 [1, 4294967295)/integer

the first RSC coder in
decimal value
G2 Numerator of generator for None 25 [1, 4294967295)/integer

the first RSC coder in
decimal value

the second RSC coder in
decimal value
G4 Numerator of generator for None 25 [1, 4294967295)/integer

decimal value
PUNCTURING No {0} None 0 [0, Inf)/Integer

Puncturing period {>0}
Coders/Decoders2-65
TERMINATION No {0} None 0 [0, 3]/Integer

1st RSC only {1}
2d RSC only{2}
Both RSC {3}
OUT_TYPE Output value with 0 or 1 {0} None 0 [0, 1]/Integer

Output value with -1 or 1 {1}
RIN1 Input impedanc1e Ohm Inf (0, Inf]/Real
RIN2 Input impedance2 Ohm Inf (0, Inf]/Real
RIN3 Input impedance3 Ohm Inf (0, Inf]/Real
Ports
Input1 Binary input sequence (integer)
Input2 Interleaving pattern (integer)
Output Turbo decoded binary sequence (real)
Limits:
K ≥1
L1 ≥ 2
L2 ≥ 2
G1 , G2 , …G4 ≥ 0
Notes
1. This model is used for Turbo Coder with Parallel Concatenated Convolutional Code (PCCC).
Kis number of information bits in each code block
2. Turbo Coder Structure: Fig.1 shows the diagram of Turbo Coder with PCCC. The encoder
consists of two recursive systematic convolutional (RSC) encoders with rate 1/2 which are sep-
arated by an K-bit interleaver, together with an optional puncturing procedure. Clearly, with-
Coders/Decoders2-66
out the puncturer, the encoder is rate 1/3, mapping Kdata bits to 3K code bits. In the K-bit
interleaver, denote by i the index of the input sequence before interleaving and f(t) is the index
of output sequence after interleaving, the interleaving pattern sequence is given by f(0) f(1) ...
f(K-1) .
uk xk ,1 = uk
Input1
RSC1 g 2 (D ) xk , 2
xk ,1 , xk , 2 , xk′ , 2
puncturer
g1 (D )
K-bit Output
Interleaver
RSC2 g 4 (D ) xk′ , 2
uk′
g 3 (D )
Fig.1 Turbo Coder with PCCC
xk ,1 = uk
g11 g12 = 0 g13 = 0 g14

uk
D D D D
g 20 g 21 = 0 g 22 g 23 g 24
xk , 2
Fig.2 Recursive Systematic Convolutional (RSC) Encoder with G1 = 31 , G2 = 27
3. RSC Encoder: The RSC code with rate 1/2 has the generator matrix
 g 2 (D ) 
G (D ) = 1 
 g1 (D )  (1)
In the above equation, the polynomials g1(D) and g2(D are given by
L −1
g1 (D ) = ∑ g1i D i
i =0 g1i = {0,1} (2)
Coders/Decoders2-67
L −1
g 2 (D ) = ∑ g 2 i D i
i =0 g 2i = {0, 1} (3)
with L is the constraint length of the RSC code. In this model, g1(D) and g2(D) are expressed
in octal form G1(D) and G2(D), respectively. For example, if G1(D) = 1 + D + D4 and G2(D)
= 1 + D2 + D3 + D4, the octal forms are G1 = 31, G2 = 27, as shown in Fig.2.
4. When Puncturing is set to 0, no puncturing is considered. Otherwise, some output bits are
deleted according to a chosen puncturing pattern from the third input port. The number of bits
in the puncturing pattern is called puncturing length. If the element of the pattern is 1, the cor-
responding output bit is transmitted. If the element of the pattern is 0, the corresponding output
bit is omitted.
5. In this model, we can choose whether termination of each RSC encoder to the zero state or not.
The termination method can be found in [2], as shown in Fig.2. For each RSC encoder, L-1 bits
are needed for termination, with L is the constraint length of the RSC code. Therefore, without
the puncturer, we set Termination to 3, the number of output bits is given by
3K + 2(L1 − 1) + 2(L1 − 1) = 3K + 2 L1 + 2 L2 − 2 (4)
with L1 and L2 is the constraint length of the first RSC code and of the second RSC code,
respectively.
6. If Out_Type is set to 0, the output of the true value and the false value are 1 and 0, respectively.
If Out_Type is set to 1, the output of the true value and the false value are 1 and -1, respec-
tively.
Netlist Form:
TCODPCCC:NAME n1 n2 n3 n4 K=val L1=val L2=val G1=val G2=val
G3=val G4=val [PUNCTURING=val]
+ [TERMINATION =val] [OUT_TYPE =val] [RIN1=val] [RIN2=val]
Netlist Example
TCODPCCC:1 1 2 3 4 K=636 L1=5 L2=5 G1=19 G2=31 G3=19 G4=31
PUNCTURING=6 +TERMINATION=3 OUT_TYPE=1
References
1. C. Berrou and A. Glavieux, “Near optimum error correcting coding and decoding: Turbo-
codes,” IEEE Trans. Commun., vol. 44, no. 10, pp. 1261–1271, 1996.
D. Divsalar and F. Pollara, “Turbo codes for PCS applications,” Proc. 1995 Int. Conf. Comm.,
pp54-59.
Coders/Decoders2-68
Turbo Decoder with PCCC (TDECPCCC)

TDECPCCC
ALGORITHM BCJR-MAP {0} None 3 [0, 4]/integer

Max-Log-MAP {1}
Log-MAP Eexact) {2}
Log-MAP {3}
SOVA {4}
K Number of information bits in None 65536 [1, Inf)/integer

each code block
L1 Constraint length in the first None 5 [2, 32)/integer

RSC coder
L2 Constraint length in the second None 5 [2, 32)/integer

RSC coder

the first RSC coder in decimal
value
G2 Numerator of generator for the None 25 [1, 4294967295)/integer

first RSC coder in decimal
value

decimal value
Coders/Decoders2-69
G4 Numerator of generator for the None 25 [1, 4294967295)/integer

second RSC coder in decimal
value
PUNCTURING No {0} None 0 [0, Inf)/Integer

TERMINATION No {0} None 3 [0, 3]/Integer

1st RSC only {1}
2d RSC only{2}
Both RSC {3}
ITERATION Number of iterations None 8 [1, Inf]/Integer
TRELLIS_DEPTH Trellis depth of SOVA None 25 [1, Inf)/Integer

algorithm
A Fading amplitude (A = 1 for None 1 [0, Inf)/Real

nonfading AWGN channel)
EBNOR Transmitted energy per None 1 (-Inf, 100]/Real

information bit to noise
spectral density ratio in dB
FEEDBACK Feedback factor for extrinsic None .8 (0, 1]]/Real

information
Ports
Input1 Received signal to be decoded (real)
Input2 Interleaving pattern (integer)
Coders/Decoders2-70
Output Turbo decoded binary sequence (integer)
Limits
K ≥1
L1 ≥ 2
L2 ≥ 2
G1 , G2 , …G4 ≥ 0
Iteration ≥ 1
0 ≤ Feedback ≤ 1
Notes
1. This model is used for Turbo Decoder with Parallel Concatenated Convolutional Code
(PCCC). K is number of information bits in each code block
2. Turbo Coder Structure: Fig.1 shows the diagram of Turbo Coder with PCCC. The encoder
consists of two recursive systematic convolutional (RSC) encoders with rate 1/2 which are sep-
arated by an K-bit interleaver, together with an optional puncturing procedure. For details of
the encoder, please refer to the model Turbo Coder with PCCC.
uk xk ,1 = uk
Input1
RSC1 g 2 (D ) xk , 2
xk ,1 , xk , 2 , xk′ , 2
puncturer
g1 (D )
K-bit Output
Interleaver
RSC2 g 4 (D ) xk′ , 2
uk′
g 3 (D )
Fig.1 Turbo Coder with PCCC
3. Iterative Turbo Decoder Structure: The diagram of iterative Turbo Decoder with PCCC is
shown in Fig.2. It should be noted that the turbo decoder must insert zeros in the soft channel
output for these punctured bits. In addition, a Feedback Factor ( 0 < Feedback ≤ 1 ) is used to
Coders/Decoders2-71
multiply the extrinsic information for stability with a typical value 0.8.
Feedback Factor
Le, 2 K-bit
RSC1 Le,1 K-bit Deinterleaver
xk , 2
Decoder Interleaver RSC2
xk ,1 = uk Decoder ûk
K-bit
K-bit Deinterleaver decision
LLR
Interleaver
xk′ , 2
Fig.2 Iterative Turbo Decoder with PCCC
4. RSC Decoder: In this model, each of the five typical algorithms (BCJR-MAP, Max-Log-
MAP, Log-MAP (Exact), Log-MAP and SOVA) can be chosen used in RSC Decoder, which
is the core of the iterative Turbo Decoder. The five algorithms are described in [3]. Please refer
to [3] for details.
Netlist Form
TDECPCCC:NAME n1 n2 n3 n4 [ALGORITHM=val] K=val L1=val L2=val
G1=val G2=val G3=val G4=val
+ [PUNCTURING=val] [TERMINATION =val] [ITERATION=val]
[TRELLIS_DEPTH=val] [A =val]
+ [EBN0R=val] [FEEDBACK =val] [RIN1=val] [RIN2=val] [RIN3=val]
[ROUT=val]
Netlist Example
TDECPCCC:1 1 2 3 4 ALGORITHM = 3 K=636 L1=5 L2=5 G1=19 G2=31
G3=19 G4=31
+ PUNCTURING=6 TERMINATION=3 ITERATION=6 TRELLIS_DEPTH =50
A=1.0
+ EbN0R=2 FEEDBACK=0.8
References
1. C. Berrou and A. Glavieux, “Near optimum error correcting coding and decoding: Turbo-
codes,” IEEE Trans. Commun., vol. 44, no. 10, pp. 1261–1271, 1996.
2. J. Hagenauer, E. Offer, and L. Papke, “Iterative decoding of binary block and convolutional
codes,” IEEE Trans. Inform. Theory, pp. 429–445, Mar. 1996.
3. J. P. Woodard and L. Hanzo, “Comparative Study of Turbo Decoding Techniques: An Over-
Coders/Decoders2-72
view,” IEEE Transactions on Vehicular Technology, vol. 49, no. 6, pp. 2208-2233, Nov. 2000.
4. D. Divsalar and F. Pollara, “Turbo codes for PCS applications,” Proc. 1995 Int. Conf. Comm.,
pp54-59.
5. L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal decoding of linear codes for minimiz-
ing symbol error rate,” IEEE Trans. Inform. Theory, vol. vol. IT-20, pp. 284–287, Mar. 1974.
6. W. Koch and A. Baier, “Optimum and sub-optimum detection of coded data disturbed by time-
varying inter-symbol interference,” IEEE Globecom, pp. 1679–1684, Dec. 1990.
7. J. A. Erfanian, S. Pasupathy, and G. Gulak, “Reduced complexity symbol detectors with paral-
lel structures for ISI channels,” IEEE Trans. Commun., vol. 42, pp. 1661–1671, 1994.
8. P. Robertson, E. Villebrun, and P. Hoeher, “A comparison of optimal and sub-optimal MAP
decoding algorithms operating in the log domain,” in Proc. Int. Conf. Communications, June
1995, pp. 1009–1013.
9. J. Hagenauer and P. Hoeher, “A Viterbi algorithm with soft-decision outputs and its applica-
tions,” IEEE Globecom, pp. 1680–1686, 1989.
10. J. Hagenauer, “Source-controlled channel decoding,” IEEE Trans. Commun., vol. 43,
pp. 2449–2457, Sept. 1995.
Coders/Decoders2-73
Viterbi Decoder (VDEC)

VDEC
N Number of bits to None 2 [1, 8]/Integer

generate at the output
for each K input bits
K Number of input bits to None 1 [1, 8]/Integer

be shifted
into shift register at
each step.
L Constraint length of None 5 [2, Inf)/Integer

convolutional
coder
Decision Hard decision {0} None 0 [0, 1]/Integer

Soft decision {1}
Puncturing No {0} None 0 [0, Inf)/Integer

Trellis_ Trellis depth of Viterbi None 25 (0, Inf)/Integer

Depth decoder
Coders/Decoders2-74
G1, G2 Generators of None 0 [0,

, ..., G8 convolutional coder 4294967295]/
(specified in decimal) Integer
(optional)
Ports
Output The convolutionally decoded binary sequence (real)
Limits
0 < K × L ≤ 32
Notes
1. This model is Viterbi decoder for a convolutional code. In order to provide the correct decod-
ing process, the parameters which are shared by a Convolutional Coder and corresponding
Viterbi Decoder must be identical except the two parameters: T and F. These identical param-
eters are N, K, L, G1,G2,...GN with N ≤ 8. Please refer to the list of parameters given for the
Convolutional Coder model.
2. This model takes a received input sequence (which may contain errors when compared to the
sequence originally transmitted by the Convolutional Coder model) and optimally decodes
this sequence using Viterbi Algorithm (VA) (Please refer to [1] for more details). This model
can perform hard decision or soft decision, the corresponding metric may be either a Hamming
metric or a Euclidean metric, respectively.
3. Puncturing is a procedure for omitting some of the encoded bits in the transmitter (thus reduc-
ing the number of transmitted bits and increasing the coding rate) and inserting a dummy
“zero” into the convolutional decoder in the receiver in place of the omitted bits. If the param-
eter Puncturing is set to a positive integer, the corresponding puncturing pattern (the number
of samples equals Puncturing period) is obtained from the second input port. For the values of
the pattern sequence, please refer to the Puncturer model and Depuncturer model.
4. At the Trellis_Depth stage, this model starts to output the optimally decoded binary data only
Coders/Decoders2-75
after receiving N x Trellis_Depth input bits. That means if the total number of bits present at
the input port is less than N x Trellis_Depth, no bits will be decoded and sent to the output port.
5. After receiving N x Trellis_Depth input bits, this model would have generated 2K(L-1) possible
decoded sequences. The model then chooses the decoded sequence that most likely corre-
sponds to the originally transmitted sequence at the output of the Convolutional Coder model
and outputs K optimally decoded bits at each stage in the decoding process. Note that the first
optimally decoded K output bits will appear at the output port only after N x Trellis_Depth
input bits have been received. Then as each new N bits are received at the input port, the opti-
mally decoded K bits (i.e., the bits that were received in Trellis_Depth stages) are sent to the
output and so on. Finally, the model decodes the remaining (N-1) x Trellis_Depth input bits
using Viterbi Algorithm (VA), chooses (K-1) x Trellis_Depth output bits that most likely cor-
responds to the originally transmitted sequence at the output of the Convolutional Coder
model.
6. At the beginning of the decoding process, it is always assumed that this model starts in the all
zero state (i.e., the content of the K x L shift register is binary zero).
7. The ratio of the output bit rate to the input bit rate is K/N.
Netlist Form
VDEC:NAME n1 n2 n3 N=val K=val L=val [DECISION=val]
[PUNCTURING=val] TRELLIS_DEPTH =val + [T=val] [F=val]
[G1...N=val] [RIN1=val] [RIN2=val] [ROUT=val]
Netlist Example
VDEC:1 1 2 3 N=2 K=1 L=7 DECISION = 0 PUNCTURING = 6
TRELLIS_DEPTH = 35 G1=91 G2=121
References
Coders/Decoders2-76
Viterbi Decoder with Packet Transmission (VDECPT)

VDECPT
N Number of bits to be None 2 [1, 8]/Integer

generated at the output
for each K input bits
K Number of input bits to None 1 [1, 8]/Integer

be shifted into shift
register at each step.
L Constraint length of None 5 [2, Inf)]/Integer

convolutional coder
Decision Hard decision {0}, None 0 [0, 1]/Integer

Soft decision {1}
Puncturing No {0} None 0 [0, Inf)/Integer

Msg_Length Message length None 100 [1, Inf)/Integer
Pkt_Length Packet length None 100 [1, Inf)/Integer
Trellis_Depth Trellis depth of Viterbi None 25 (0, Inf)/Integer

decoder
Coders/Decoders2-77
G1, G2, ..., G8 Generators of None 0 [0, 4294967295]/

convolutional coder Integer
(specified in decimal)
(optional)
Ports
Output The convolutionally decoded binary sequence (real)
Limits
0 < K × L ≤ 32
Pkt _ Length ≥ Trellis _ Depth
Pkt _ Length ≥ Msg _ Length
Notes/Equations
1. This model is Viterbi decoder for a convolutional code with packet transmission. In order to
provide the correct decoding process, the parameters which are shared by a Convolutional
Coder and corresponding Viterbi Decoder with packet transmission must be identical
except the two parameters: T and F and . These identical parameters are N, K, L, G1,G2, ...GN
with N <= 8. Please refer to the list of parameters given for the Convolutional Coder model.
2. This model takes a received input sequence (which may contain errors when compared to the
sequence originally transmitted by the Convolutional Coder model) and optimally decodes
this sequence using Viterbi Algorithm (VA) (Please refer to [1] for more details). This model
can perform hard decision or soft decision, the corresponding metric may be either a Hamming
metric or a Euclidean metric, respectively.
3. Puncturing is a procedure for omitting some of the encoded bits in the transmitter (thus reduc-
ing the number of transmitted bits and increasing the coding rate) and inserting a dummy
Coders/Decoders2-78
“zero” into the convolutional decoder in the receiver in place of the omitted bits. If the param-
eter Puncturing is set to a positive integer, the corresponding puncturing pattern (the number
of samples equals Puncturing period) is obtained from the second input port. For the values of
the pattern sequence, please refer to the Puncturer model and Depuncturer model.
4. Msg_Length and Pkt_Length are the length of Message and Packet, respectively. It should be
noted that each packet includes K x Pkt_Length bits at the input of the Convolutional Coder
model and is formed by appending “zero” bits to each K x Msg_Length massage bits.
5. At the Trellis_Depth stage, this model starts to output the optimally decoded binary data only
after receiving N x Trellis_Depth input bits. That means if the total number of bits present at
the input port is less than N x Trellis_Depth, no bits will be decoded and sent to the output port.
6. After receiving N x Trellis_Depth input bits, this model would have generated 2K(L-1) possible
decoded sequences. The model then chooses the decoded sequence that most likely corre-
sponds to the originally transmitted sequence at the output of the Convolutional Coder model
and outputs K optimally decoded bits at each stage in the decoding process. Note that the first
optimally decoded K output bits will appear at the output port only after N x Trellis_Depth
input bits have been received. Then as each new N bits are received at the input port, the opti-
mally decoded K bits (i.e., the bits that were received in Trellis_Depth stages) are sent to the
output and so on.
Finally, the model decodes the remaining (N-1) x Trellis_Depth input bits using Viterbi Algo-
rithm (VA), chooses (K-1) x Trellis_Depth output bits that most likely corresponds to the orig-
inally transmitted sequence at the output of the Convolutional Coder model.
7. At the beginning of the decoding process, it is always assumed that this model starts in the all
zero state (i.e., the content of the K x L shift register is binary zero). The contents of this shift
register can be reinitialized (i.e., set to binary zero) by properly specifying the parameter
Pkt_Length (which must always be greater than or equal to Trellis_Depth). In other words,
after receiving N x Pkt_Length bits, this model would have outputted K x Pkt_Length opti-
mally decoded bits, after which the contents of the shift register are reinitialized.
8. The ratio of the output bit rate to the input bit rate is K/N.
Netlist Form
VDECPT:NAME n1 n2 n3 N=val K=val L=val [DECISION=val]
[PUNCTURING=val] MSG_LENGTH =val + PKT_LENGTH =val
TRELLIS_DEPTH =val [T=val] [F=val] [G1=val . . . GN=val]
+[RIN1=val] [RIN2=val] [ROUT=val]
Netlist Example
VDECPT:1 1 2 3 N=2 K=1 L=7 DECISION = 0 PUNCTURING = 6
MSG_LENGTH = 118
+PKT_LENGTH= 120 TRELLIS_DEPTH = 35 G1=91 G2=121
Coders/Decoders2-79
References
Coders/Decoders2-80
3
Data Converters
Data Converters3-81
Serial Analog to Digital Converter (ADC)

ADC
NBITS Number of bits per None 8 (0, Inf)/Real

sample
VL Minimum input Volt -1.0 (-Inf, Inf)/Real

voltage, in voltage units
VH Maximum input Volt 1.0 (-Inf, Inf)/Real

voltage (any number),
in voltage units
Ports
Input2 Input2 clock signal (real)
Data Converters3-82
Notes
1. The output of this ADC is a serial bit stream representing the amplitude of the input signal at
the sampling instances. The input voltage Range/Type from Vl to Vh is partitioned into 2nbits
values. Each interval is indexed by an integer value ranging between 0 and 2nbits–1. The inter-
vals are labeled according to the offset binary format; that is, the interval corresponding to Vl
is encoded at 00 … , 0; the next largest voltage interval is encoded as 00… ,01 etc.; and, the
interval corresponding to Vh is encoded as 111 … , 11.
2. At every positive clock edge, the ADC samples the input signal, determines the interval in
which the sample lies, and outputs the corresponding index of that interval. The output is a
serial bit stream; each bit is placed on the output pin for one clock period—the LSB is output
first and the MSB is output last. At the end of nbits clocks, all bits have been transmitted and
the input voltage is sampled again.
3. In the following illustration, a signal is the input into the ADC element, which has as its
parameter values Nbits=8, vl = -1V and Vh = 1V. The ADC is clocked at a rate of 0.015625
µs.
Netlist Form
ADC:Name n1 n2 n3 NBITS=val Vl=val Vh=val [Rin1=val]
[Rin2=val][Rout=val]
Data Converters3-83
Netlist Example
ADC:1 1 2 3 Nbits=8 Vl=-1 Vh=1
Data Converters3-84
Binary to M-ary Coder (BMEN)
Binary to M-ary Coder (BMEN)

BMEN
NB Number of bits to group None 1 [1, 31]/Integer

into one symbol
Ports
Input Input signal of bits, starting with LSB (real)
Output Output signal of symbols (real)
Notes
1. This model outputs integer symbols in the Range/Type of 0, ...., 2NB – 1 from an integer input
signal made up of 0's and 1's.
2. Each incoming NB bits are grouped and mapped to one of the corresponding above symbols
(BMEN interprets the value of each bit as follows: V<0.5 : binary 0, V>=0.5 : binary 1).
3. The ratio of the output symbol rate to that of the input bit rate is 1/NB.
Netlist Form
BMEN:Name n1 n2 NB=val [Rin1=val] [Rin2=val][Rout=val]
Netlist Example
BMEN:1 1 2 NB=2
Data Converters3-85
Binary to NRZ Converter (BTONRZ)

BTONRZ
TYPE Type of mapping:{0} / {1} None 0 [0, 1]/Integer
Ports
Input Input signal (complex)
Output Output Signal (real)
Notes
1. This model converts binary bits to non-return zero signal. If TYPE is set to 0, a binary bit 0 is
mapped to +1 and a binary bit 1 is mapped to -1. Otherwise, a binary bit 0 is mapped to -1 and
a binary bit 1 is mapped to +1. The relation of the output z and the input x is given by
− 1 x ≥ 0.5
z=
 1 x < 0.5 for TYPE = 0 (1)
 1 x ≥ 0.5
z=
− 1 x < 0.5 for TYPE = 1 (2)
Netlist Form
BTONRZ:NAME n1 n2 [TYPE=val] [RIN=val] [ROUT=val]
Data Converters3-86
Netlist Example:
BTONRZ:1 1 2
Data Converters3-87
Complex to Magnitude & Phase Converter (CTOMP)
Complex to Magnitude & Phase Converter (CTOMP)

CTOMP
ROUT1 Output1 impedance Ohm 0 [0, Inf)/Real
Ports
Outpu1t Output1 Signal (real)
Output2 Outpu2t Signal (real)
Notes
1. This model converts a complex signal to two real signals. The first output signal is the magni-
tude of the input signal and the other is the phase of the input signal, in radians.
Netlist Form
CTOMP:NAME n1 n2 n3 [RIN=val] [ROUT1=val] [ROUT2=val]
Netlist Example
CTOMP:1 1 2 3
Data Converters3-88
Complex to Real Converter (CTOR)
Complex to Real Converter (CTOR)

CTOR
Phase Phase for transforming Deg 0 [-180, 180]/Real

input signal
Ports
Output Output Signal (real)
Notes
This model converts the complex input signal Vin(t) into a real output signal Vout(t) accroding to
the following equation:
Vout(t) = Re{Vin(t)} cos(PHASE) + Im{Vin(t)}sin(PHASE)
For PHASE = 0deg, the output will equal the real part of the input signal, and for PHASE = 90 deg
the output will equal the imaginary part of the input signal .
Netlist Form
CTOR:Name n1 n2 PHASE=val [Rin1=val] [Rin2=val][Rout=val]
Netlist Example
CTOR:1 1 2 PHASE=90DEG
Data Converters3-89
Complex to Real & Imaginary Converter (CTORI)
Complex to Real & Imaginary Converter (CTORI)

CTORI
Ports
Output1 Output1 Signal (real)
Output2 Output2 Signal (real)
Notes
1. This model converts a complex signal to two real signals. The first output signal is the real part
of the input signal and the other is the imaginary part.
Netlist Form:
CTORI:NAME n1 n2 n3 [RIN=val] [ROUT1=val] [ROUT2=val]
Netlist Example:
CTORI:1 1 2 3
Data Converters3-90
Serial Digital to Analog Converter (DAC)

DAC
NBITS Number of bits None 8 (0, Inf)/Real
VH Maximum output Volt -1V (-Inf, Inf)/Real

VL Minimum output Volt 1V (-Inf, Inf)/Real

Ports
Input1 Input1 bit stream (real)
Input2 Input2 clock input (real)
Notes
1. This DAC accepts a serial binary input and converts it into the appropriate analog voltage. At
Data Converters3-91
each positive clock edge (when the clock voltage becomes greater than 0.5V) the input signal
is sampled and compared to 0.5V to determine if it is a logic 0
or 1. Once nbits bits are clocked into the DAC, the output voltage is calculated. It is assumed
that the LSB is clocked in first and the MSB is clocked in last.
2. The figure below shows outputs for an ADC and A DAC with Nbit s= 4, VL = -1V and l = 1V.
The clock has a rate of 0.015625 µs, thus, the DAC element outputs a new analog sample every
0.125 µs.
Netlist Form
DAC:Name n1 n2 n3 NBITS=val VL=val VH=val [Rin1=val]
Netlist Example
DAC:1 1 2 3 NBITS=4 VL=-1 VH=1
Data Converters3-92
M-ary to Binary Decoder (MBEN)

MBEN
NB Number of bits to None 2 [1, 32]/Integer

group into one
symbol
Ports
Input Input signal of symbols (real)
Output Output signal of bits, LSB first (real)
Notes
1. This model converts the M-ary input signal into a binary output signal of 0's and 1's.
2. The input signal is made of symbols (voltages) in the Range/Type of (0,...., 2NB –1).
3. The ratio of the output bit rate to the input symbol rate is given by NB. For example, with
NB=5, the MBEN expects an input voltage in the range [0,31]V. For an input of 0V, the 5-bit
MBEN outputs 00000. For an input of 31V, the 5-bit MBEN outputs 11111.
4. For negative input voltages, the MBEN outputs NB bits of zeros.
5. For voltages above (2NB –1), the MBEN outputs NB bits of ones (i.e., the maximum value).
Netlist Form
MBEN:Name n1 n2 NB=val [Rin1=val] [Rin2=val][Rout=val]
Data Converters3-93
Netlist Example
MBEN:1 1 2 NB=4
Data Converters3-94
Magnitude & Phase to Complex Converter (MPTOC)
Magnitude & Phase to Complex Converter (MPTOC)

MPTOC
Ports
Input1 Input signal (real)
Output Output Signal (complex)
Notes
1. This model converts two real signals to a complex signal. The first input signal is treated as the
magnitude and the other as the phase of the output signal in radians.
Netlist Form
MPTOC:NAME n1 n2 n3 [RIN1=val] [RIN2=val] [ROUT=val]
Netlist Example
MPTOC:1 1 2 3
Data Converters3-95
NRZ to Binary Converter (NRZTOB)

NRZTOB
TYPE Type of mapping:{0} / {1} None 0 [0, 1]/Integer
Ports
Notes
1. This model converts non-return zero signal to binary bits. The relation of the output z and the
input x is given by
0 x ≥ 0
z=
1 x < 0 for TYPE = 0 (1)
1 x ≥ 0
z=
0 x < 0 for TYPE = 1 (2)
Netlist Form
NRZTOB:NAME n1 n2 [TYPE=val] [RIN=val] [ROUT=val]
Data Converters3-96
Netlist Example:
NRZTOB:1 1 2
Data Converters3-97
Parallel Analog to Digital Converter (PADC)

PADC
NBITS Number of bits per None 8 [1, 32]/Integer

sample
VL Minimum input Volt -1 (-Inf, Inf)/Real

voltage
VH Maximum input Volt 1 (-Inf, Inf)/Real

voltage
Ports
Input1 Input signal (real)
Data Converters3-98
Limits
1. VH> VL
Notes
1. The first input is supposed to be the analog signal to be sampled and quantized, while the sec-
ond input is the clock signal. On the rising edge of the digital clock input to the parallel ADC,
the input waveform is sampled and quantized. The number of quantization levels is equal to
2^nbits, with the range of input values being determined by vl and vh. Input signal values out-
side of this range will output 0 on the low side and (2^nbits-1) on the high side.
Netlist Form
PADC:NAME n1 n2 n3 nbits=val vl=val vh=val [Rin1=val]
[Rin2=val] [Rout=val]
Netlist Example
PADC:1 1 2 3 nbits = 8 vl = 0 vh = 1
Data Converters3-99
Parallel Digital to Analog Converter (PDAC)

PDAC
NBITS Number of bits per None 8 [1, 32]/Integer

sample
VL Minimum output Volt -1 (-Inf, Inf)/Real

voltage
VH Maximum output Volt 1 (-Inf, Inf)/Real

voltage
Ports
Input2 Input2 clocksignal (real)
Data Converters3-100
Limits
1. VH > VL
Notes
1. On the rising edge of the digital clock input to the parallel DAC, the input digital signal is con-
verted to analog. The number of quantization levels is equal to 2^nbits. The range of ouput val-
ues are determined by vl and vh. The output value is calculated like this:
vin (n)
vout (n) = * (v h − vl ) + vl
2 nbits
2. The input signal is assumed to be in the range of [0, 2^nbits-1], if the input signal is out of this
range, then it will be regarded as 0 for those less than 0, and 2^nbits-1 for those greater than
2^nbits-1.
3. The clock signal is assumed to be shresholded at 0.5.
Netlist Form
PDAC:NAME n1 n2 n3 nbits=val vl=val vh=val [Rin1=val]
Netlist Example
PDAC:1 1 2 3 nbits = 8 vl = 0 vh = 1
Real & Imaginary to Complex Converter (RITOC)
Real & Imaginary to Complex Converter (RITOC)

RITOC
Ports
Output Output Signal (complex)
Notes
1. This model converts two real signals to a complex signal. The first input signal is treated as the
real part and the other as the imaginary part.
Netlist Form:
RITOC:NAME n1 n2 n3 [RIN1=val] [RIN2=val] [ROUT=val]
Netlist Example:
RITOC:1 1 2 3
Real Input to Complex Output (RTOC)

RTOC
Phase Phase for Deg 0 [-180, 180]/Real

transforming input
signal
Ports
Output Output signal (complex)
Notes
1. This model converts the real input signal Vin(t) into a complex output signal Vout(t) according
to the following equation:
Re{Vout(t)} = Vin(t) cos(PHASE)
Im{Vout(t)} = Vin(t) sin(PHASE)
For PHASE = 0deg, the output is real and equals the input signal (i.e., imaginary part is zero)
and for PHASE = 90deg the output is pure imaginary and equals Vin(t) (i.e., real part is zero).
Netlist Form
RTOC:Name n1 n2 PHASE=val [Rin1=val] [Rin2=val][Rout=val]
Netlist Example
RTOC:1 1 2 PHASE=90DEG
4
Demodulators
Demodulators4-104
Synchronous Amplitude Demodulator (AMDEM)

AMDEM
SEN Demodulation sensitivity, None 1V [-1e6, 1e6)/Real

in voltage units per volt
PHAS Carrier phase offset Deg 0 [-180, 180]/Real
TYPE Type of Synchronous AM None 1 [1, 2]/Integer

demodulator
1: In-phase AM
demodulator
2: Quad-phase AM
demodulator
Ports
Input The input AM modulated signal (complex)
Output The output of AM demodulator (complex)
Notes
1. This model performs AM demodulation. The input to this model is assumed to be an AM mod-
ulated bandpass signal with in-phase and quad-phase envelopes vin,i(t) and vin,q(t). The output
is a baseband signal.
Demodulators4-105
There are two different AM demodulators. The output quad-phase is always 0, and the in-
phase signal is given as follows, respectively
(1) TYPE = 1 for In-phase AM demodulator, vout,i(t) = SEN • I(t)

(2) TYPE = 2 for Quad-phase AM demodulato, vout,i(t) = SEN • Q(t)
where
I(t) = vin,i(t) • cos(θ) + vin,q(t) • sin(θ)
Q(t) = -vin,i(t) • sin(θ) + vin,q(t) • cos(θ)
θ = PHAS • π / 180
Netlist Form
AMDEM:Name n1 n2 SEN=val [PHAS=val] [TYPE=val] [Rin=Val]
[Rout=Val]
Netlist Example
AMDEM:1 1 2 SEN=1.2 PHAS=0DEG TYPE=1
Demodulators4-106
Complex Multiplier (CMULT)

CMULT
TYPE Type of multiplier: None 1 [1, 2]/Integer

1: High side multiplier
2: Low side multiplier
Ports
Input1 Input1 signal (complex)
Notes
1. This model performs complex multiplication. If both inputs to this model are baseband signals
Demodulators4-107
vin,1(t) and vin,2(t), the output is baseband signal. The output quad-phase is 0, and in-phase sig-
nal is given as follows
vout,i(t) = vin,1,i(t) • vin,2,i(t)
If both the inputs to this model are bandpass signals with the in-phase and quad-phase enve-
lopes vin,1,i(t), vin,1,q(t) and vin,2,i(t), vin,2,q(t), the output is bandpass signal and has the differ-
ent output carrier frequency. The output carrier frequency, in-phase and quad-phase envelopes
are given as follows, respectively
1. TYPE = 1 for high side multiplier

fout = fin,1 + fin,2
vout,i(t) = vin,1,i(t) • vin,2,i(t) - vin,1,q(t) • vin,2,q(t)
vout,q(t) = vin,1,i(t) • vin,2,q(t) + vin,1,q(t) • vin,2,i(t)
2. TYPE = 2 for low side multiplier

if fin,1 > fin,2
fout = fin,1 - fin,2
vout,i(t) = vin,1,i(t) • vin,2,i(t) + vin,1,q(t) • vin,2,q(t)
vout,q(t) = -vin,1,i(t) • vin,2,q(t) + vin,1,q(t) • vin,2,i(t)
if fin,1 = fin,2
fout = 0
vout,i(t) = vin,1,i(t) • vin,2,i(t) - vin,1,q(t) • vin,2,q(t)
vout,q(t) = 0
if fin,1 < fin,2
fout = fin,2 - fin,1
vout,i(t) = vin,1,i(t) • vin,2,i(t) + vin,1,q(t) • vin,2,q(t)
vout,q(t) = vin,1,i(t) • vin,2,q(t) - vin,1,q(t) • vin,2,i(t)
Netlist Form
CMULT:Name n1 n2 n3 [TYPE=val] [Rin1=Val] [Rin2=Val]
[Rout=Val]
Netlist Example
CMULT:1 1 2 3 TYPE=2
Demodulators4-108
PI/4DQPSK Demodulator (DQPSKDEM)

DQPSKDEM
Ports
Input1 in-phase input (real)
Input2 Quadrature input (real)
Output Demodulated output symbols (real)
Notes
1. This model performs PI/4DQPSK demodulation. The in-phase and quadrature inputs to this
model (ri(n) and rq(n), n ≥ 0) are assumed to have been modulated by the model PI/4DQPSK.
Since the input to the modulator PI/4DQPSK is assumed to be the symbol values A(n) = 0, 1,
2, 3, n ≥ 0, the recovered symbol values at the output of the demodulator B(n) are also 0, 1, 2,
3, for n ≥ 0.
Let the received complex (in-phase + quadrature) symbols be r(n) = ri(n) + j rq(n), n ≥ 0. The
Demodulators4-109
demodulation process is performed as follows for n ≥ 0:

B(n) = 0, Re{r(n)r*(n-1)} > 0, Im{r(n)r*(n-1)} > 0
B(n) = 1, Re{r(n)r*(n-1)} < 0, Im{r(n)r*(n-1)} > 0
B(n) = 2, Re{r(n)r*(n-1)} > 0, Im{r(n)r*(n-1)} < 0
B(n) = 3, Re{r(n)r*(n-1)} < 0, Im{r(n)r*(n-1)} < 0
where r*(n-1) is the complex conjugate of r(n-1), and Re{.} and Im{.} denote the real and
imaginary operators respectively. The following initial condition is always assumed:
r(-1) = cos(PI/4) + j sin(PI/4)

Netlist Form
DQPSKDEM:Name n1 n2 n3 [Rin1=Val] [Rin2=Val] [Rout=Val]
Netlist Example
DQPSKDEM:1 1 2 3
Demodulators4-110
Edge Demodulator (EDGEDEM)

EDGEDEM
DECISION Hard{0}/soft{1} None 0 [0, 1]/Integer

output selection
Ports
Input1 The FM modulated I-input signal (complex)
Input2 The FM modulated Q-input signal (complex)
Output The output of FM demodulator (complex)
Notes
1. This element converts received I/Q signal stream into bit stream based on the EDGE 8PSK
modulation. Each three output bits correspond to a pair of in-phase and quadrature input sig-
nals. Depending upon DECISION=0 or DECISION=1, the output can be either hard (e.g.,
0,1,1,0,0,1,…) or soft (e.g., -0.21, 1.13, 0.82, -1.33, -0.78, 1.41, …). Performance can be max-
imized when the soft output in conjunction with channel coding are employed.
2. Let <θn> be the estimated signal phase with removal of the additional phase shift θn., offset ,
corresponding to the time index n. The hard-output decision rule (i.e., the mapping of <θn>
onto output bits) follows:
Demodulators4-111
π π π ˆ 3π
− < θˆn ≤ → 111 < θn ≤ → 011
8 8 , 8 8 ,
3π 5π 5π 7π
< θˆn ≤ → 010 < θˆn ≤ → 000
8 8 , 8 8 ,
7π 9π 9π 11π
< θˆn ≤ → 001 < θˆn ≤ → 101
8 8 , 8 8 ,
11π 13π 13π 15π
< θˆn ≤ → 100 < θˆn ≤ → 110
8 8 , 8 8 .
In contrast with the hard-output demodulation, the soft-output demodulation uses a bit-by-bit
decision rule called maximum a posteriori (MAP). For any given time index, let X = xI + j . xQ,
|X| = 1, be a signal taken from the normal 8PSK signal set S, represent the binary bit triplet
mapping onto a 8PSK signal, and Y= yI + j . yQ, be received baseband signal with removal of
the additional phase shift. The soft-output value <bk> (corresponding to bk), k = 1,2,3..., is
given by
~    
bk = ln  ∑ Pr( X | Y ) − ln  ∑ Pr( X | Y ),
 X ∈S ,bk =1   X ∈S ,bk =0  k = 1,2,3
If the channel noise is AWGN, it can be proved that probability Pr(X|Y) in above equation can
be expressed as
[
Pr( X | Y ) = C ⋅ exp ( x I ⋅ y I + xQ ⋅ yQ ) ⋅ α / σ 2 ],
where Cis a constant, α is received signal amplitude and σ2 denotes the noise power. For sim-
plification, factor α/σ2 is not taken into account inside this demodulator, and ,bk> is actually
computed by using equation
~    
bk = ln  ∑ exp( x I ⋅ y I + xQ ⋅ yQ ) − ln  ∑ exp( x I ⋅ y I + xQ ⋅ yQ ),
 X ∈S ,bk =1   X ∈S ,bk =0  k = 1,2,3
which implies that, in the case that the channel is fading, the input signal should be weighted
by instantaneous amplitude α to achieve better performance. Note that this modification in cal-
culating the soft-output values will not degrade BER performance when a Viterbi decoder fol-
lowing the demodulator is used at the receiver.
Additional details about the EDGE 8PSK modulation can be found in [1]. For soft-output pro-
cessing, refer to [2]-[4].
Netlist Form
EDGEDEM:Name n1 n2 n3 DECISION=val [Rin1=val], [Rin2=val],
[Rout=val]
Demodulators4-112
Netlist Example
EDGEDEM:1 1 2 3 DECISION=0
References
1. GSM 05.04 (i.e., ETSI EN 300 959): “Digital cellular telecommunications system (Phase 2+);
Modulation”
2. R. Herzog, A. Schmidbauer and J. Hagenauer, “Iterative decoding and dispreading improves
CDMA-system using M-ary orthogonal modulation and FEC.”
3. L. R. Bahl, J. Cocke, F. Jelinek and J. Ravivo, “Optimal decoding of linear codes for minimiz-
ing symbol error rate,” IEEE Trans. Inform. Theory, vol. IT-20, pp. 284-287, Mar. 1974.
4. H. H. Zeng, Y. Li and J. H. Winters, “Improved spatial-temporal equalization for EDGE: a fast
selective-direction MMSE timing recory algorithm and two-stage soft-output equalizer,” IEEE
Trans. Commun., vol. 49, pp. 2124-2134, Dec. 2001.
Demodulators4-113
Envelope Detector (ENVELOPE)

ENVELOPE
SEN Demodulation sensitivity, in None 1V [-1e6, 1e6]/Real

voltage units per volt
TYPE Detection type option (optional): None 1 [1, 3]/Integer

1: Full rectified envelope
2: In-phase rectified envelope
3:Quadrature-phase rectified
envelope
Ports
Input The input AM modulated signal (complex)
Output The output of envelope detector (complex)
Notes
1. This model performs envelope detection. The input to this model is assumed to be an AM
modulated bandpass signal with in-phase and quad-phase envelopes vin,i(t) and vin,q(t). The
output is a baseband signal.
There are three different envelope detectors. The output quad-phase is always 0, and the in-
Demodulators4-114
phase signal is given as follows, respectively
TYPE = 1 for full rectified envelope vout,i(t) = SEN • SQRT(I(t)2 + Q(t)2)

TYPE = 2 for in-phase rectified envelope vout,i(t) = SEN • SQRT(I(t)2)
TYPE = 3 for quadrature-phase rectified envelope vout,i(t) = SEN • SQRT(Q(t)2), where
θ = PHAS • π / 180
Netlist Form
ENVELOPE:Name n1 n2 SEN=val [PHAS=val] [TYPE=val] [Rin=Val]
[Rout=Val]
Netlist Example
ENVELOPE:1 1 2 SEN=1.2 PHAS=0DEG TYPE=1
Demodulators4-115
Frequency Demodulator (FMDEM)

FMDEM
SEN Frequency demodulation None 0 [-1e6 1e6]/Real

sensitivity, in voltage units per
Hz
Ports
Input The input FM modulated signal (complex)
Output The output of FM demodulator (complex)
Notes
1. This model performs FM demodulation. The input to this model is assumed to be an FM mod-
ulated bandpass signal with in-phase and quad-phase envelopes vin,i(t) and vin,q(t). The output
is a baseband signal. The output quad-phase is 0, and the in-phase signal is given as follows
vout,i(t) = SEN • (I(t) • d[Q(t)]/dt - Q(t) • d[I(t)]/dt) / (2π •(I(t)2 + Q(t)2)) where
θ = PHAS • π / 180
Demodulators4-116
Netlist Form
FMDEM:Name n1 n2 SEN=val [PHAS=val] [Rin=Val] [Rout=Val]
Netlist Example
FMMOD:1 1 2 SEN=1.2 PHAS=90DEG
Demodulators4-117
I-Q Demodulator (IQDEM)

IQDEM
S Sensitivity None 1 [-1e6, 1e6]/Real
P Phase reference Deg 0 [-180, 180]/Real
PHIQ I-Q phase imbalance Deg 0 [180, 180]/Real
Ports
Output1 in-phase output signal (real)
Output2 Quadrature output signal (real)
Notes
1. For a given input signal
Vin (t ) = A(t ) cos(2πf c t + θ (t ))
Demodulators4-118
the baseband in-phase output signal is computed as:
VIout (t ) = S {A(t ) cos(θ (t )) cos( P) − A(t ) sin(θ (t )) sin( P + PHIQ)}

and the baseband quadrature output signal is computed as:
VQout (t ) = S {A(t ) cos(θ (t )) sin( P ) + A(t ) sin(θ (t ) cos( P + PHIQ )}

The output signal is always assumed to be baseband (i.e. fc=0) regardless of the input carrier
frequency.
Netlist Form
IQDEM:Name n1 n2 n3 S=val P=val PHIQ=val [Rin=val]
[Rout=val]
Netlist Example
IQDEM:1 1 2 3 S=1 P=0DEG PHIQ=0DEG
Demodulators4-119
Logarithmic Detector (LOGDET)

LOGDET
SEN Log sensitivity, in voltage units None 0 [0, Inf)/Real

per dB
PL Low input power Watt 0W [1e-23, 1e7]/Real
E Peak log error, in dB dB 0 [0, 200]/Real
EC Log error cycle, in dB dB 1 [0, 200]/Real
Ports
Input The input signal (complex)
Output The output signal (complex)
Notes
1. This model performs logarithmic detection. The input to this model is assumed to be a band-
pass signal with in-phase and quad-phase envelopes vin,i(t) and vin,q(t). The output is a base-
band signal. The output quad-phase is 0, and the in-phase signal is given as follows
vout,i(t) = M2(t) where
A1(t) = SQRT(vin,i(t)2 + vin,q(t)2)
M2(t) = 20 • SEN • LOG10(A1(t)/VL)+ SEN • E • sin(θ) for A1(t) > VL
M2(t) = 0 for A1(t) ≤ VL
Demodulators4-120
VL = SQRT(2 • 50 • PL)
θ = 2 • π • (PA - 10 • LOG10(PL))/EC
PA = 10 • LOG10(A1(t)2/(2 • 50))
Netlist Form
LOGDET:Name n1 n2 SEN=val PL=val E=val EC=val [Rin=val]
[Rout=val]
Netlist Example
LOGDET:1 1 2 SEN=1.2 PL=10W E=0.75dB EC=10dB
Demodulators4-121
Phase Demodulator (PMDEM)

PMDEM
SEN Phase demodulation None 1 [-1e6, 1e6]/Real

sensitivity, in voltage
units per degree
Ports
Input The input PM modulated signal (complex)
Output The output of PM demodulator (complex)
Notes
1. This model performs PM demodulation. The input to this model is assumed to be a PM modu-
lated bandpass signal with in-phase and quad-phase envelopes vin,i(t) and vin,q(t). The output is
a baseband signal. The demodulated quad-phase is 0, and the in-phase signal is given as fol-
lows
vout,i(t) = SEN • ATAN2[Q(t), I(t)] • 180 / π, where
Demodulators4-122
θ = PHAS • π / 180
Netlist Form
PMDEM:Name n1 n2 SEN=val [PHAS=val] [Rin=Val] [Rout=Val]
Netlist Example
PMDEM:1 1 2 SEN=1.2 PHAS=0DEG
Demodulators4-123
Phase Shift Keying Demodulator (PSKDEM)

PSKDEM
M The order of the signal space. None 2 [2, 128]/Integer

M = 2: BPSK,
M = 4: QPSK, etc.
Ports
Input1 Real part of the complex input signal (real)
Input2 Imaginary part of the complex input signal (real)
Output Output signal of symbols in the Range/Type 0,....., M -1 (real)
Notes
1. This model maps each pair of samples (one from each input signal) into one symbol k, where k
is in the Range/Type 0,...., M - 1. This model is normally used in conjunction with the model
PSKMOD (Phase Shift Keying Modulator). The symbol which corresponds to the minimum
Demodulators4-124
Euclidean distance from the received complex symbol is written to the output.
Netlist Form
PSKDEM:Name n1 n2 n3 M=val [Ri1=val] [Rin2=val] [Rout=val]
Netlist Example
PSKDEM:1 1 2 3 M=4
Demodulators4-125
QAM Demodulator (QAMDEM)

QAMDEM
M Order of constellation space None 4 (0, Inf)/Integer
Ports
Notes
1. This model outputs N bits for each incoming in-phase and quadrature input samples, where
N = Log 2 ( M ), and
M is the order of the constellation space (i.e. M=4 for 4-QAM and M=16 for 16-QAM …)
For a given M, this model determines the constellation point (in the I  Q signal space) with
the minimum metric distance to a given complex (in-phase and quadrature) input sample.
Once the constellation point is determined, its N-bit binary representation is then transmitted.
Demodulators4-126
If this model is immediately preceded by the QAMMOD model, then its output should be iden-
tical to the input of the QAMMOD model. The output bit rate is equal to N times the input (I
and Q) symbol rate.
Netlist Form
QAMDEM:Name n1 n2 n3 M=val [Rin1=Val] [Ri2 n=Val] [Rout=Val]
Netlist Example
QAMDEM:1 1 2 3 M=4
Demodulators4-127
5
Digital Filters
Digital Filters5-128
Complex Integrator (CINTG)
Complex Integrator (CINTG)

CINTG
Ports
Notes
1. For a given input signal, Vin(t) = X(t) cos (2πfc t + θx (t))
the output signal will be given by Vout(t) = Y(t) cos (2πfc t + θy (t)), where
jθ ( t ) t
Y(t )e y = ∫ X(τ )e jθ x (τ ) dτ
0
The above continuous time integration is actually computed in discrete fashion based on the
time step of the complex input envelope, X(t) . exp [j θx (t)]
Netlist Form
CINTG:Name n1 n1 NUM_OF_SAMPLES=val [Rin=val] [Rout=val]
Netlist Example
CINTG:1 1 2 NUM_OF_SAMPLES=100
Integrator with Clock (CLKINTG)

CLKINTG
Ports
Notes
1. This element performs an integration on the input signal during the time interval determined by
the clock signal. Let T0, T1, T2, … be the time instances with the positive edges of the input
clock, V2(t), occur (a positive edge occurs at the instant when the clock voltage, V2(t), crosses
a threshold of 0.5V). The output signal V3(t) is then determined by the following equations in
terms of input signal V1(t).
t
V3 (t ) = ∫ V1 (t)dt Tk < t ≤ Tk +1
Tk
The integration is performed using the trapezoidal rule. The input signal, clock signal, and out-
put signal voltages of the CLKINTG element are shown in the figure.
Netlist Form
CLKINTG:Name n1 n2 n3 [Rin1=val] [Rin2=val][Rout=val]
Netlist Example
CLKINTG:1 1 2 3
Finite Impulse Response Filter (FIR)

FIR
n1 n3
FIR
n2
FILE External filename None <Project> String
TRAN 0 = Discard None 0 [0, 1]/Integer

transient samples,
1 = Retain samples
RIN1 Input 1 impedance Ohm Inf (0, Inf]/Real
Ports
Input2 Input2 clock signal (real, optional)
Output The output signal (real)
Notes
1. This model implements FIR filter. The transfer function is of the form
M
H (Z ) = ∑ bk Z −k
k =0
2. The filter tap coefficients are provided in the data block in two-column XY DSP format. Each
(X,Y) entry indicates the tap index and the corresponding tap coefficient (k, bk).
3. The second input is optional. If it is connected, this model operates as an edge triggered device,
with the trigger level 0.5V.
Netlist Form
FIR:NAME n1 n2 n3 FILE=”filename.dsp” [Rin1=val] [Rin2=val]
+ [Rout=val] [TRAN=val]
Netlist Example
FIR:1 1 2 3 FILE="firdata.dsp"
Gaussian Low Pass Filter (GLPF)

GLPF
FB Effective Bandwidth Frequency Hz 50000 (0, Inf)/Real
FILT_LENGTH Number of filter coefficients None 16 [8, Inf)/Integer
TRAN 0 = Discard transient samples, None 0 [0, 1]/Integer

1 = Retain samples
Ports
Output Filtered output signal (real)
Notes
1. This is a lowpass filter model which has the following transfer function
H(f) = sqrt (2) exp [-ln (2) * (f 2/FB) ] for - Inf < f < Inf
where FB is the effective 3dB bandwidth of the filter.
2. The impulse response of the filter is obtained by implementing the above function in the FFT
domain (taking the input sampling frequency (FS) into consideration) and then using an
inverse FFT of length FFTL which must be a power of 2. This FFTL is given by:
FFTL = Minimum power of 2 larger than 2 x FILT_LENGTH.
3. Note that the above frequency response must be truncated in the frequency domain since it has
an infinite duration. This means that there will always be aliasing regardless of the FFT length
chosen. Upon finding the impulse response, the filter is made causal by delaying the impulse
response.
For a more accurate impulse response, the user must make sure
FILT_LENGTH ≥ 5.0(FS/FB)
4. The program will not issue a warning message if this condition is not met.
Form
GLPF:Name n1 n2 FB=val FILT_LENGTH=val [Rin=val]
[Rout=val] [TRAN=val]
Example
GLPF:1 1 2 FB=100KHZ FILT_LENGTH=32
Infinite Impulse Response Filter (IIR)

IIR
n1 n3
IIR
n2
FILE File name None <Project> String
Ports
Input1 Input 1 signal (real)
Input2 Input 2 clock signal (real, optional)
Notes
1. This model implements IIR filter. I can be either clocked or non-clocked. If non-clocked, the
second input port should be left open. The transfer function is of the form
M
∑ bk Z −k
H (Z ) = k =0
N
∑ a k Z −k
k =0 (1)
2. The filter tap coefficients are provided in the data block in two-column XY DSP format. Each
(X,Y) entry indicates the coefficients (ak, bk).
Netlist Form
IIR:NAME n1 n2 n3 FILE=”filename.dsp” [RIN1=val] [RIN2=val]
+ [ROUT=val]
Netlist Example
IIR:1 1 2 3 FILE="iirdata.dsp"
Integrate and Dump (INTDUMP)

INTDUMP
Num_of_Samples Number of samples None 1 [1, Inf)/Integer

to integrate over
each invocation
Ports
Input The input signal (real)
Notes
1. This model implements an integrate and dump filter. Each output sample y(n) is computed as:
NumOfSamples – 1
1
y ( n ) = ----------------------------------------
NumOfSamples
- ∑ x ( NumOfSamples ( n + 1 ) – m )
m=0
where x(n) is the input sequence

Netlist Form
INTDUMP:name n1 n2 NUM_OF_SAMPLES=val [Rin=val] [Rout=val]
Example
INTDUMP 1 2 NUM_OF_SAMPLES=100
Root Raised Cosine Filter (RRCF)

RRCF
FC 3 dB Cutoff_Frequency Hz 50 (0, Inf)/Real
BETA Rolloff factor None 0.5 [0, 1]/Real
FILT_LENGTH Number of filter None 16 [9, Inf]/Integer

coefficients
TRAN 0 = Discard transient None 0 [0, 1]/Integer

samples,
1 = Retain samples
Ports
Notes
2. This is a lowpass filter model which has the following transfer function:
H(f) = 1, for 0 ≤ |f| ≤ (1 - BETA)* FC

H(f) =sqrt (0.5 * (1 - sin (pi * (|f| - FC)/(2 * FC * BETA))))

for (1 - BETA) * FC ≤ |f| ≤ (1 + BETA) * FC
H(f) = 0, for |f| ≥ (1 + BETA) * FC

where FC is the 3 dB cutoff frequency and BETA is the rolloff factor.
3. The impulse response of the filter is obtained by implementing the above function in the FFT
domain (taking the input sampling frequency (FS) into consideration) and then using an
inverse FFT of length FFTL. This length is given by
FFTL = Minimum power of 2 larger than 2 x FILT_LENGTH.
Upon finding the impulse response, the filter is made causal by delaying the impulse response.
For a more accurate impulse response, the user must make sure
FILT_LENGTH ≥ 5.0(FS/(1+BETA)FC
and to avoid aliasing, the user must ensure that
FS => 2 . (1+ BETA) FC
4. The model will not issue warning messages if these conditions are not met.
Netlist Form
RRCF:Name 1 2 FC=val BETA=val FILT_LENGTH=val [Rin=val]
[Rout=val] [TRAN=val]
Netlist Example
RRCF:1 1 2 FC=100KHZ BETA=.75 FILT_LENGTH=32
References
Sinc Filter (SINC)
Sinc Filter (SINC)

SINC
n1 n3
SINC
n2
M Filter order None 35 [1, Inf)/Integer
K Number of stages None 1 [1, Inf)/Integer
Ports
Notes
1. This model implements Sinck Filter. I can be either clocked or non-clocked. If non-clocked,
the second input port should be left open. The transfer function is of the form
K
1  1 − Z −M 
H (Z ) =   −1

 M  1− Z 
Sinc Filter (SINC)
Netlist Form
SINC:NAME n1 n2 n3 M=val [K=val] [RIN1=val] [RIN2=val]
+ [ROUT=val]
Netlist Example
SINC:1 1 2 3 M=10 K=2
Z-Domain Differentiator with Order M (ZDIFF)

ZDIFF
n1 n3
1-Z-M
n2
M Filter order None 35 [1, Inf]/integer
Ports
Notes
1. This model implements Z-Domain Differentiator with order M. I can be either clocked or non-
clocked. If non-clocked, the second input port should be left open. The transfer function is of
the form
H (Z ) = 1 − Z − M (1)
Netlist Form
ZDIFF:NAME n1 n2 n3 M=val [RIN1=val] [RIN2=val] [ROUT=val]
Netlist Example
ZDIFF:1 1 2 3 M=10
Z-Domain Differentiator with Order M, K Stages
Z-Domain Differentiator with Order M, K Stages (ZDIFFK)

ZDIFFK
n1 n3
(1-Z-M)K
n2
M Filter order None 35 [1, Inf)/Integer
Ports
Notes
1. This model implements Z-Domain Differentiator with order M and K stages. I can be either
clocked or non-clocked. If non-clocked, the second input port should be left open. The transfer
function is of the form
(
H (Z ) = 1 − Z − M )
K
Z-Domain Differentiator with Order M, K Stages
Netlist form:
ZDIFFK:NAME n1 n2 n3 M=val [K=val] [RIN1=val] [RIN2=val]
+ [ROUT=val]
Netlist Example:
ZDIFFK:1 1 2 3 M=10 K=2
Z-Domain Integrator (ZINTEG)
Z-Domain Integrator (ZINTEG)

ZINTEG
n1 1 n3
1-Z-1
n2
Ports
Notes
1. This model implements Z-Domain Integrator. I can be either clocked or non-clocked. If non-
clocked, the second input port should be left open. The transfer function is of the form
1
H (Z ) =
1 − Z −1
Netlist Form
ZINTEG:NAME n1 n2 n3 [RIN1=val] [RIN2=val] [ROUT=val]
Netlist Example
ZINTEG:1 1 2 3
Z-Domain Integrator, K Stages (ZINTEGK)

ZINTEGK
n1 1 K n3
( )
1-Z-1
n2
Ports
Notes
1. This model implements Z-Domain Integrator with K stages. I can be either clocked or non-
clocked. If non-clocked, the second input port should be left open. The transfer function is of
the form
K
 1 
H (Z ) =  −1 
1− Z 
Netlist Form
ZINTEGK:NAME n1 n2 n3 [K=val] [RIN1=val] [RIN2=val] [ROUT=val]
Netlist Example
ZINTEGK:1 1 2 3 K=2
6
Digital Logic
Digital Logic6-151
AND Gate (AND)
AND Gate (AND)

AND
Ports
Notes
 1 when V1 (t ) ≥ 0.5 and V2 ( t ) ≥ 0.5

V3 ( t ) = 
 0 otherwise
Netlist Form
AND:Name n1 n2 n3 [Rin1=val] [Rin2=val][Rout=val]
Digital Logic6-152
AND Gate (AND)
Netlist Example
AND:1 1 2 3
Digital Logic6-153
D Flip-Flop--Edge Triggered (DFF)

DFF
R
n1
C Q
n2
DFF n5
D Q
n3 n6
S
n4
Range/
Property Description Units Default
Type
Ports
Input1 The reset/clear signal (real, inverted)
Input2 The clock signal (real)
Input3 The D input signal (real)
Input4 The Preset signal (real, inverted)
Digital Logic6-154
Output1 The non-inverted output signal (real)
Output2 The inverted output signal (real)
Notes
Function Table
Input Output
R (1) C (n2) D (3) S (n4) Q (n5) NQ (n6)
H x x L H L
L x x H L H
L x x L H H
H UP H H H L
H UP L H L H
H L x H Q0 NQ0
S = input preset, active with low level

R = input clear, active with logic low level
C = input clock, active with low to high transition
x = don’t care state
L = logic low level. Input: < 0.5; Output: 0.0
H = logic high level. Input: > 0.5; Output 1.0
UP = low-to-high transition
Q0 = previous state
NQ inverted Q state
NQ0 = previous inverted Q state
Digital Logic6-155
The input, output and clock signal voltages of the DFF element, with S (n4) and R (n1)
both tied to a high logic level (1.0 V), are shown in the figure below.
Netlist Form
DFF:Name n1 n2 n3 n4 n5 n6 [Rin1=val] [Rin2=val][Rin3=val]
[Rin4=val][Rout1=val][Rou2t=val]
Netlist Example
DFF:1 1 2 3 4 5 6
Digital Logic6-156
Divide by N Counter (DIVN)

DIVN
N Divide by factor None 1 (0, Inf)/Integer
N0 Initial counter value None 1 (0, N-1)/

Integer
Ports
Notes
1. This element is a model of a positive edge-triggered, modulo N down counter. The input to the
element is a clock signal and the output is a signal that is high or low, depending on whether
the current counter value is greater or less than floor (N/2). Note that the counter value itself is
not available as an output.
Let M(k) denote the counter value after the kth positive clock edge. Then
M(0) = N0
Digital Logic6-157
M(k) = (M(k-1) -1) modulo N, k ≥ 1

  N
 0 if M(k) ≥ floor  2 
V2 (t ) = 
1 if M(k) < floor  N 
  2
2. The initial counter value N0 is limited to the range [0, N-1] where N is the divide-by factor.
3. The input and output signal voltages of the DIVN element, with parameters N=7 and N0=1,
are shown. Output is low until the first positive clock edge occurs at time 10 msec. Output
jumps to high level at 10 msec, since initial counter N0=1 (< floor (7/2) ).
4. Note that the period of the input signal is 10µsec and the period of the output period is 70µsec,
which yields the signal frequency divided by 7 after the element.
Netlist Form
DIVN:Name n1 n2 [Rin1=Val] [Rout=Val]
Netlist Example
DIVN:1 1 2
Digital Logic6-158
Inverter (INV)
Inverter (INV)
INV
Range/
Type
Ports
Input Input signal
Output Output signal
Notes
0 when V1 (t) ≥ 0.5
V2 (t) = 
1 when V1 (t) < 0.5
Netlist Form
INV:Name n1 n2 [Rin1=val] [Rin2=val][Rout=val]
Netlist Example
INV:1 1 2
Digital Logic6-159
J-K Flip-Flop (JKFF)

JKFF
Ports
Input1 The reset/clear signal (real)
Input2 The K input signal (real)
Input3 The Clock signal (real)
Digital Logic6-160
Input4 The J input (real)
Input5 The preset signal (real)
Output1 Output1 signal (real)
Output2 The inverted output signal (real)
Notes
Functional Table
Input Output
R (n1) K (n2) C (n3) J (n4) S (n5) Q (n6) NQ (n7)
L x x x L H H
H x x x L H L
L x x x H L H
H L UP L H Q0 NQ0
H L UP H H H L
H H UP L H L H
H H UP H H Toggle
Digital Logic6-161
CLK = input clock, active with low to high transition

S = input preset, active with logic low level
R = input clear, active with logic low level
L = logic low level; Inputs: <0.5; Outputs: 0.0
H = logic high level; Inputs: >0.5; Outputs : 1.0
UP = low-to-high transition
Q0 = previous Q state
NQ = inverted Q state
1. Initially, at time equal to 0 time units, the outputs Q and NQ are equal to L and H, respectively.
2. The input (C, K, J) and output (Q) signal voltages of the JKFF element, with S and R both tied
to a high logic level (1.0V), are shown.
Digital Logic6-162
Netlist Form
JKFF:Name n1 n2 n3 n4 n5 n6 n7 [Rin1=Val] [Rin2=Val]
[Rin1=Val] [Rin3=Val] [Rin4=Val] [Rin5=Val][Rout1=Val]
[Rout2=Val]
Netlist Example
JKFF:1 1 2 3 4 5 6 7
Digital Logic6-163
Latch (LATCH)
Latch (LATCH)
LATCH
Ports
Input2 The clock signal (real)
Digital Logic6-164
Latch (LATCH)
Notes
Function Table
Input (n1) Clock (n2) Output (n3)
L H L
H H H
x L Q0

L = logic low level; Inputs: <0.5; Outputs: 0.0
H = logic high level; Inputs: >0.5; Outputs : 1.0
Q0 = previous Q state
1. Initially, at time equal to 0 time units, the output Q is equal to L.

2. This element is clock level sensitive. If the user prefers a clock edge-triggered latch, the DFF
element can be used with S=R=H.
3. The input, clock, and output signal voltages of the LATCH elements are shown.
Digital Logic6-165
Latch (LATCH)
Netlist Form
LATCH:Name n1 n2 n3 [Rin1=val] [Rin2=val][Rout=val]
Netlist Example
LATCH:1 1 2 3
Digital Logic6-166
Linear Feedback Shift Register (LFSR)

LFSR
SR_LENGTH Length of Shift None 5 [0,32)/Integer

Register
TAP_CONNECTIONS Tap connections None 1 [0,Inf)/Integer

of the shift
register
INITIAL_CONTENT Initial contents of None 1 [0,Inf)/Integer

the shift register
in decimal
Ports
Notes
1. The linear feedback shift register element can be used to generate PN sequences with user-
defined recurrence relations. The input to the LFSR is a clock signal; with each positive clock
edge the next output bit is calculated according to user provided initial value and tap connec-
Digital Logic6-167
tion value.
2. The initial output from the LFSR is zero until the first rising clock edge.
3. Input and output signals to/from LFSR is shown in the figure below. The LFSR used in the
example has register length of 5, initial value 31, and tap_connection of 24.
4. The element uses decimal values to represent initial values and tap connections to the shift reg-
ister. For a certain SR_LENGTH value, only the least significant SR_LENGTH bits of
INITIAL_CONTENT and TAP_CONNECTIONS will be used to perform the calculation. For
the above example, we have a register with 5 stages, initially loaded with 5 bits of information
11111 (31 = 16 + 8 + 4 + 2 + 1) and non-zero feedback coefficient C5 = 1 and C4 = 1 (since
24 = 16 + 8). Note that, the MSB bit will be first shifted out once a positive edge is detected.
Netlist Form
LFSR:Name n1 n2 SR_LENGTH=val TAP_CONNECTIONS=val
INITIAL_CONTENT=val [Rin=Val] [Rout=Val]
Netlist Example
LFSR: 1 2 SR_LENGTH=10 TAP_CONNECTIONS=340
INITIAL_CONTENT=457
Digital Logic6-168
NAND Gate (NAND)
NAND Gate (NAND)

NAND
Ports
Input1 The first input signal (real)
Input2 The second input signal (real)
Notes
 0 when V1 (t) ≥ 0.5 and V2 (t) ≥ 0.5
V3 (t) = 
 1 otherwise
Netlist Form
NAND:Name n1 n2 n3 [Rin1=val] [Rin2=val ][Rout=val]
Netlist Example
NAND:1 1 2 3
Digital Logic6-169
NOR Gate (NOR)
NOR Gate (NOR)

NOR
Range/
Type
Ports
Notes
 1 when V1 (t) < 0.5 and V2 (t) < 0.5

V3 (t) = 
 0 otherwise
Netlist Form
NOR:Name n1 n2 n3 [Rin1=val] [Rin2=val][Rout=val]
Digital Logic6-170
NOR Gate (NOR)
Netlist Example
NOR:1 1 2 3
Digital Logic6-171
OR Gate (OR)
OR Gate (OR)
OR
Ports
Notes
 0 when V1 (t) < 0.5 and V2 (t) < 0.5
V3 (t) = 
 1 otherwise
Netlist Form
OR:Name n1 n2 n3 [Rin1=val] [Rin2=val][Rout=val]
Digital Logic6-172
OR Gate (OR)
Netlist Example
OR:1 1 2 3
Digital Logic6-173
Two-Bit Demultiplexer (TBDMUX)

TBDMUX
Ports
Output1 The output I signal (real)
Output2 The output Q signal (real)
Notes
Functional Table
Digital Logic6-174
D C I Q
(n1) (n2) (n3) (n4)
L L L H
H L H H
L H H L
H H H H
L = logic low level input: < 0.5; output: 0.0

H = logic high level input: > 0.5; output: 1.0
Netlist Form
TBDMUX:Name n1 n2 n3 n4 [Rin1=val] [Rin2=val ][Rout1=val]
[Rout2=val]
Netlist Example
TBDMUX:1 1 2 3 4
Digital Logic6-175
Two-Bit Multiplexer (TBMUX)

TBMUX
Ports
Input1 Input1 signal, Q (real)
Input2 Input2 signal, I (real)
Input3 Clock signal, C (real)
Digital Logic6-176
Notes
Functional table
Q (n1) I (n2) C (n3) D (n4)
L L L L
L L H L
L H L L
L H H H
H L L H
H L H L
H H L H
H H H H
L = logic low level input: < 0.5; output: 0.0

H = logic high level input: > 0.5; output: 1.0
Netlist Form
TBMUX:Name n1 n2 n3 n4 [Rin1=val] [Rin2=val][Rin3=val]
[Rout=Val]
Netlist Example
TBMUX:1 1 2 3 4
Digital Logic6-177
Exclusive OR Gate (XOR)
Exclusive OR Gate (XOR)

XOR
RIN2 Input2 impedance Ohm Inf (0, Inf]/Real/Real
Ports
Notes
 1 when V1 (t) ≥ 0.5 and V2 (t) < 0.5 or when V1 (t) < 0.5 and V2 (t) ≥ 0.5
V3 (t) = 
 0 otherwise
Netlist Form
XOR:Name n1 n2 n3 [Rin1=val] [Rin2=val ][Rout=val]
Netlist Example
XOR:1 1 2 3
Digital Logic6-178
7
Equalizers
Equalizers7-180
Least Mean Square Equalizer, Complex (CLMSE)

CLMSE
NTAPS The number of filter coefficients None 4 (-Inf, Inf)/Integer
DELTA The LMS algorithm step size None 1 (-Inf, Inf)/Real
RIN4 Input4 impedance Ohm Inf (0, In]f
Ports
Input3 Real part of the error signal (real)
Equalizers7-181
Input4 Imaginary part of the error signal (real)
Output1 Real part of the complex output signal (real)
Output2 Imaginary part of the complex output signal (real)
Notes
1. This model updates the filter coefficients of the equalizer based on the input signal and the
error signal (i.e., the difference between the output of the equalizer and the actual desired out-
put). The update is based on minimizing the mean square error.
2. Let X(n) and h(n) denote the complex input signal vector and the vector of the complex filter
coefficients respectively at time instant n. Each vector is assumed to be of length NTAPS (i.e.,
number of filter taps). The update of the filter coefficients is done according to
h(n+1) = h(n) + DELTA * e(n) * conj(X(n))
where: conj(X(n)) is the complex conjugate of the vector X(n) and e(n) = d(n) - y(n), where
d(n) is the desired output and y(n) is the equalizer output at time instant n.
3. The complex output of the equalizer at instant n + 1 is given by
y(n+1) = transpose(X(n+1)) * h(n+1)
4. The following initial conditions are always assumed:
h(-1) = 0, X(-1) = 0
Netlist Form
CLMSE:NAME n1 n2 n3 n4 n5 n6 NTAPS=val DELTA=val [RIN1=val]
[RIN2=val] [RIN3=val] [RIN4=val] [ROUT1=val] [ROUT2=val]
Netlist Example
CLMSE:1 1 2 3 4 5 6 NTAPS=6 DELTA=.005
References
1. G. Proakis, Digital Communications, McGraw-Hill, 1989.
2. G. Proakis and D. G. Manolakis, Digital Signal Processing, Macmillan, 1988.
Equalizers7-182
Recursive Least Square Equalizer, Complex
Recursive Least Square Equalizer, Complex (CRLSE)

CRLSE
NTAPS The number of filter None 4 (-Inf, Inf)/Integer

coefficients
DELTA Inverse correlation None 0.0005 (-Inf, Inf)/Real

matrix initialization
factor
LAMBDA Forgetting factor of None 1 [0, 1]/Real

the RLS algorithm
Ports
Equalizers7-183
Input3 Real part of the error signal (real)
Input4 Imaginary part of the error signal (real)
Output1 Real part of the complex output signal (real)
Output2 Imaginary part of the complex output signal (real)
Notes
This model updates the filter coefficients of the equalizer based on the complex input and error sig-
nals (i.e., the difference between the output of the equalizer and the actual desired output). The
update is based on the recursive least square algorithm [1], [2].
Let X(n) and h(n) denote the input signal vector and the vector of the complex filter coefficients
respectively at time instant n. Each vector is assumed to be of length NTAPS (i.e., number of filter
taps). In addition, let K(n) denote the NTAPS x 1 complex Kalman gain vector and let the NTAPS
x NTAPS inverse of the complex correlation matrix of the input signal be denoted by P(n).
The recursive least square algorithm is given by the following 5 steps:
1. Compute the filter output:
y(n) = trans(X(n)) * h(n-1)
2. Compute the error:
e(n) = d(n) - y(n), where d(n) is the desired output
3. Compute the NTAPS x 1 Kalaman gain vector:
K(n) = [P(n-1) * conj(X(n))] / [LAMBDA + trans(X(n)) * P(n-1) * conj(X(n))]
4. Update the inverse of the complex correlation matrix:
P(n) = (1/LAMBDA) [P(n-1) - K(n) * trans(X(n)) * P(n-1)]
5. Update the coefficients of the complex filter:
h(n) = h(n-1) + K(n) * e(n)
The following initial conditions are always assumed:
P(-1) = (1/DELTA) * I, where DELTA is a small positive number and I is the NTAPS x NTAPS
identity matrix. e(-1) = 0, and h(-1) = 0.
Equalizers7-184
Netlist Form
CRLSE:NAME n1 n2 n3 n4 n5 n6 NTAPS=val DELTA=val LAMBDA=val
[RIN1=val] [RIN2=val] [RIN3=val] [RIN4=val] [ROUT1=val]
[ROUT2=val]
Netlist Example
CRLSE:1 1 2 3 4 5 6 NTAPS=6 DELTA=.005 LAMBDA=.999
References
2. J. G. Proakis and D. G. Manolakis, Digital Signal Processing, Macmillan, 1988.
Equalizers7-185
Least Mean Square Equalizer (LMSE)

LMSE
NTAPS The number of filter None 16 (-Inf, Inf)/Integer

coefficients
DELTA The LMS algorithm None 0.01 (-Inf, Inf)/Real

step size
Ports
Input2 Input2 Error signal (real)
Output Output of the equalizer (real)
Notes
This model updates the filter coefficients of the equalizer based on the input signal and the error
signal (i.e., the difference between the output of the equalizer and the actual desired output). The
Equalizers7-186
update is based on minimizing the mean square error (i.e., minimizing the absolute value of the
error signal).
Let X(n) and h(n) denote the input signal vector and the vector of filter coefficients respectively at
time instant n. Each vector is assumed to be of length NTAPS (i.e., number of filter taps). The
update of the filter coefficients is done according to
h(n+1) = h(n) + DELTA * e(n) * X(n)
where e(n) = d(n) - y(n), where d(n) is the desired output and y(n) is equalizer output. The output of
the equalizer at instant n + 1 is given by
y(n+1) = trans(X(n+1)) * h(n+1)
Where trans(.) denotes the transpose operator. The following initial conditions are always assumed:
h(-1) = 0, X(-1) = 0
Netlist Form
LMSE:NAME n1 n2 n3 NTAPS=val DELTA=val [RIN1=val] [RIN2=val]
Netlist Example
LMSE:1 1 2 3 NTAPS=8 DELTA=.005
References
Equalizers7-187
Recursive Least Square Equalizer (RLSE)

RLSE
NTAPS The number of filter None 4 (-Inf, Inf)/

coefficients Integer
DELTA Inverse correlation None 0.0005 (-Inf, Inf)/Real

matrix initialization
factor
LAMBDA Forgetting factor of None 1 [0, 1]/Real

the RLS algorithm
Ports
Equalizers7-188
Notes
This model updates the filter coefficients of the equalizer based on the input signal and the error
signal (i.e., the difference between the output of the equalizer and the actual desired output). The
update is based on the recursive least square algorithm [1], [2].
Let X(n) and h(n) denote the input signal vector and the vector of the real filter coefficients respec-
tively at time instant n. Each vector is assumed to be of length NTAPS (i.e., number
of filter taps). In addition, let K(n) denote the NTAPS x 1 Kalman gain vector and let the NTAPS x
NTAPS inverse of the correlation matrix of the input signal be denoted by P(n).
The recursive least square algorithm is given by the following 5 steps:
1. Compute the filter output:
y(n) = tran(X(n)) * h(n-1
2. Compute the error:
e(n) = d(n) - y(n), where d(n) is the desired output
3. Compute the NTAPS x 1 Kalman gain vector:
K(n) = [P(n-1) * X(n)]/[LAMBDA + tran(X(n)) * P(n-1) * X(n)]
4. Update the inverse of the correlation matrix:
P(n) = (1/LAMBDA) [P(n-1) - K(n) * tran(X(n)) * P(n-1)]
5. Update the coefficients of the filter:
h(n) = h(n-1) + K(n) * e(n)
The following initial conditions are always assumed:
P(-1) = (1/DELTA) * I, where DELTA is a small positive number and I is the NTAPS x NTAPS
identity matrix, e(-1) = 0, and h(-1) = 0.
Netlist Form
RLSE:NAME n1 n2 n3 NTAPS=val DELTA=val LAMBDA=val
[RIN1=val] [RIN2=val] [ROUT=val]
Netlist Example
RLSE 1 2 3 NTAPS=8 DELTA=.005 LAMBDA=0.999
References
2. J. G. Proakis and D. G. Manolakis, Digital Signal Processing, Macmillan, 1988
Equalizers7-189
GMSK Viterbi Equalizer (VEGMSK)

VEGMSK
NB Number of bits per None 1 (0, 8])/Integer

symbol
(integer)
V The number of None 4 (-Inf, Inf)/Integer

VEGMSK equalizer
states in symbols
(integer)
M MODULATION_I None M = 2, (1, Inf)/Integer

NDEX = M/P P=4
(Refer to GMSK
modulator)
(integers)
P MODULATION_I None M = 2, (1, Inf)/Integer

NDEX = M/P P=4
(Refer to GMSK
modulator)
(integers)
NUM_ Number of samples None 2 [10e-7, 10e7]/Integer

SAMPLES per symbol (integer)
Equalizers7-190
NORMALIZED_ Normalized None 0.3 (-Inf, Inf).Real

BW bandwidth of
Gaussian filter
(real)
RESPONSE_LENGTH Length of Gaussian None 4 (0, Inf)/Integer

filter impulse
response in symbols
(integer)
VE_DEPTH Number of symbols None 100 (-Inf, Inf)/Integer

to receive prior to
resetting memory
(integer)
Ports
Input1 Received in-phase samples (real)
Input2 Received quadrature samples (real)
Input3 Received in-phase channel information (i.e., in-phase impulse

response) (real)
Input4 Received quadrature channel information (i.e., quadrature

impulse response) (real)
Output Equalized output symbols in the range 0, 1, ..., M -1 (real)
Notes
This model equalizes (or demodulates) the received GMSK-modulated in-phase and quadrature
input signals using the in-phase and quadrature channel information. The equalization algorithm
Equalizers7-191
used is based on Maximum Likelihood Sequence Estimation (MLSE) and the Viterbi Algorithm
(VA) [1], [2].
The received input signals are assumed to have been modulated by a GMSK modulator prior to
transmission. the parameters shared by the GMSK modulator used in the transmitter and its corre-
sponding Viterbi Equalizer at the receiver, namely, NB, NUM_SAMPLES,
NORMALIZED_BW, RESPONSE_LENGTH, and the MODULATION_INDEX = M/P must
be identical. This must be the case since the VEGMSK model uses these parameters to locally gen-
erate all possible received data sequences (using the channel information) and determine the most
probable transmitted sequence.
The number of states for equalization in the VEGMSK is determined by the integer V. In addition,
the number of the internally generated states depends on the integers M and P, where M and P are
relative prime numbers. If M is even, the VEGMSK will have P * 2V-1 states, and if M is odd, the
VE will 2 * P * 2V-1 states instead.
In other words, if M is even, the number of phase states in the VEGMSK model is P, otherwise, the
number of phase states will be 2 * P.
It's important to keep in mind that for a given MODULATION_INDEX at the GMSK transmit-
ting modulator, the M and P that must be properly specified by the user if proper equalization is to
be performed. For example, a MODULATION_INDEX of 0.5 at the GMSK modulator implies
that the number of phase states in the modulator is 4 (0, PI/2, PI, 3*PI/2). This implies that the cor-
responding number of phase states in the VEGMSK model at the receiver must be 4 and the modu-
lation index must be 0.5. These two conditions can be simultaneously satisfied if M = 1 and P = 2,
or M = 2, and P = 4.
V is the number of equalization states in symbols and is always assumed to be equal to the sum of
the GMSK modulator's impulse response length (i.e. RESPONSE_LENGTH) and the length of
the channel's impulse response (in symbols too). In other words
V = RESPONSE_LENGTH + Lc,
where Lc is the length of the channel's impulse response in symbols. For example, if
RESPONSE_LENGTH = 3 symbols, and V was chosen to equal 5 symbol states, this implies the
VEGMSK model will assume the channel information is contained in an impulse response of
length 2 symbols. The VEGMSK model always assumes that the length of the corresponding
impulse response in samples is given by RESPONSE_LENGTH * NUM_SAMPLES and Lc *
NUM_SAMPLES + 1 for the GMSK modulator and the channel, respectively.
For example, if V = 5, RESPONSE_LENGTH = 3, and NUM_SAMPLES = 2, then the
VEGMSK model assumes that the transmitting GMSK modulator's impulse response (in samples)
is (please refer to the GMSK model):
q[0], q[1], q[2], q[3], q[4], q[5]
and the channel's impulse response in samples is:
h[0], h[1], h[2], h[3], h[4]
If V is equal to or greater than the sum of actual lengths of the two impulse responses (i.e., the
impulse response of the GMSK modulator used at the transmitter and the actual impulse response
of the channel), then full equalization is possible, otherwise, the equalization process is hindered.
Equalizers7-192
The VEGMSK model uses q[i], 0 ≤ i ≤ RESPONSE_LENGTH * NUM_SAMPLES -1 and h[i],

0 ≤ i ≤ Lc * NUM_SAMPLES to generate all possible received sequences and then decides in
favor of the most probable transmitted sequence using MLSE and the VA ([1], [2]).
Since the input to the transmitting GMSK modulator (please refer to GMSK model) is assumed to
be the symbols Ai, where Ai = 0, 1, ..., M -1, and M = 2NB, the symbols recovered at the output of
the VEGMSK model are also in the range 0, 1, ...., M - 1. If NB = 1, then the VEGMSK model
would perform equalization on binary symbols (i.e., each symbol conveys a one-bit information),
other wise equalization will be performed on M-ary data (where each symbol conveys the informa-
tion of NB-bits, NB > 1).
The maximum number of equalization states that can be accommodated by this model is V = 32/
NB. For example, for a 16-ary data (NB = 4), the maximum number of allowable states is V = 8
symbol states (with each symbol conveying the information of 4 bits). Keep in mind that each sym-
bol may be represented by an arbitrary NUM_SAMPLES.
Observe that an increase in V, NB, or NUM_SAMPLES will increase the processing time inside
the VEGMSK model.
The VEGMSK model also assumes that it begins in the zero internal state and one of the P or 2 * P
possible phase states. This means that the first received in-phase and quadrature input samples that
go into the VEGMSK model are assumed to have been preceded by V - 1 0 symbol values at the
GMSK modulator. This is done to reduce the equalization's probability of making errors which
would be the case had we assumed all possible internal states for the beginning state.
Upon receiving VE_DEPTH symbols (i.e., VE_DEPTH * NUM_SAMPLES samples), the
VEGMSK model outputs VE_DEPTH equalized symbols (in the range 0, 1, ..., M -1) then resets
its memory to the zero state. This means the next stream of received input symbols is also assumed
to have been preceded by V - 1 0 symbols at the GMSK modulator and so on.
Netlist Form
VEGMSK:NAME n1 n2 n3 n4 n5 NB=val M=val P=val
+ NUM_SAMPLES=val RESPONSE_LENGTH=val
+ NORMALIZED_BW=val V=val VE_DEPTH=val [RIN1=val] [RIN2=val]
Netlist Example
VEGMSK 1 2 3 4 5 NB=1 M=1 P=2 NUM_SAMPLES=2
+ RESPONSE_LENGTH=3 NORMALIZED_BW=0.3 V=6 VE_DEPTH=100
This equalizer corresponds to the first example used in the GMSK modulator model (The
GSM example). Note that the equalizer may use M = 2 and P = 4 as well and still yield the
same performance. This example assumes that the channel's information (i.e., impulse
response) is entirely contained in (V - RESPONSE_LENGTH) * NUM_SAMPLES + 1
samples = 7 samples. As mentioned above, it is always assumed that the first input symbol
(i.e., NUM_SAMPLES samples) to the VEGMSK model has been preceded by V - 1 = 5
zero symbol values at the transmitting GMSK modulator. This means that the input to the
Equalizers7-193
GMSK modulator should have been 0, 0, 0, 0, 0, followed by arbitrary symbols which

will be fed into the VEGMSK model at the receiver. This implies that the first received (V
- 1) * NUM_SAMPLES samples = 10 samples must be discarded, and the next samples
(10, 11, ....) are fed to the VEGMSK model (i.e., the 10th sample (counting from 0) is
actually the first input sample that should be applied to the input of VEGMSK model).
References
2. Raymond Steele, Mobile Radio Communications, Pentech Press, 1992.
Equalizers7-194
8
Fixed-Point
Fixed-Point8-195
Complex to Fixed-Point Converter (CTOFXT)

CTOFXT
Property Description Units Default Range/type
outW Word length of the output None 32 [1, 32]/Integer

fixed point number
outD Precision of the output fixed None 0 [0, 32]/Integer

point number
ovf Overflow characteristic: None 0 [0, 2]/Integer

0 for wrapped,
1 for saturate,
2 for zero saturate
IorQ In-phase or quadrature None 0 [0, 1]/Integer

component:
0 for in-phase,
1 for quadrature
quant Quantization characteristic: None 0 [0, 2]/Integer

0 for truncated,
1 for rounded,
2 for truncated 0
ArithType Arithmetic type: 0 for signed, None 0 [0 ,1]/Integer

1 for unsigned
Rin Input impedance Ohm Inf (0, Inf]/Real
Fixed-Point8-196
Rout Output impedance Ohm 0 [0, Inf)/Real
Ports
Input Input signal (floating point complex number)
Output Output signal (fixed point real number)
Limits
outW > outD for signed arithmetic
Notes
This model converts the complex floating point signal to a real fixed-point signal. If IorQ is set to
0, the output is from the real part of the input signal (in-phase component); else, if IorQ is equal to
1, the output is from the imaginary part of the input signal (quadrature component). The format of
the output signal is set by the parameters: outW, outD, ovf, quant, arithtype, where ovf defines
the overflow characteristics, quant defines the quantization characteristics and arithtype defines
the arithmetic type. The following plot shows the relationship between the word length and the pre-
cision.
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Netlist Form
CTOFXT:NAME n1 n2 [outW=val] [outD=val] [ovf=val] [quant=val]
[IorQ=val] [arithtype=val] [Rin=val] [Rout=val]
Example
CTOFXT:1 1 2 outW=16 outD=4 ovf=1 quant=1 IorQ=1
Fixed-Point8-197
Fixed-Point Accumulator (FXTACCUM)

FXTACCUM
useInAsOut Use the input precision as the None 1 [0, 1]/Integer

output precision:
1: Use
0: Do not use

fixed point number

point number
ovf Overflow characteristic: 0 for None 0 [0, 2]/Integer

wrapped, 1 for saturate, 2 for
zero saturate

0 for truncated,
1 for rounded,
2 for truncated 0
Fixed-Point8-198
Arithtype Arithmetic type: 0 for signed , None 0 [0, 1]/Integer

1 for unsigned
Rin1 Input1 impedance Ohm Inf (0, Inf]/Real
Rout1 Output1 impedance Ohm 0 [0, Inf)/Real
Ports
Input1 Input1 clock signal (floating point real number, optional)
Input2 Input2 signal (fixed point real number)
Output1 Output1 signal (fixed point real number)
Output2 Output2 signal (floating point real number)
Limits
Notes
1. This model is a fixed point accumumlator. It can be either clocked or non-clocked. If non-
clocked, simply leave the clock signal port (the first input) open. When clocked, it is a rising
edge triggered device. The trigger level is set to be 0.5 inside this model; therefore, care must
be taken to make sure the input signal level is in accordance, a scaler may be needed to scale
the incoming signal down in some cases.
2. The parameters outW, outD, ovf, quant, and arithtype are used to define the output format of
the fixed point number. Note that, when the parameter useInAsOut is turned on, the previ-
ously mentioned parameters will be ignored; instead, the format of the output signal will be the
same as the format of the input signal. That is to say, if one wants to use a different output for-
mat than the input format, he/she has to set useInAsOut to 0, and set the corresponding for-
mat.
3. The first output is the accumulated output signal, while the second output is the overflow out-
put. When an overflow occurs during one accumulation step, a logic sigal “1” will be written to
the second output to indicate an overflow.
Fixed-Point8-199
4. The following plot shows the relationship between word length and precision.
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Netlist Form
FXTACCUM:NAME n1 n2 n3 n4 [useInAsOut=val] [outW=val]
[outD=val] [ovf=val] [quant=val] [arithtype=val] [Rin1=val]
[Rin2=val] [Rout1=val] [Rout2=val]
Netlist Example
FXTACCUM:1 1 2 3 4 outW=10 outD=10 ovf=0 quant=1 arithtype=1
Fixed-Point8-200
Fixed-Point Finite Impulse Response Filter (FXTFIR)

FXTFIR

output precision:
1 for used,
0 for not used
coefW Word length of fixed point None 32 [1, 32]/Integer

coefficient
coefD Precision of the fixed point None 0 [0, 32]/Integer

coefficient

fixed point number

point number

0 for wrapped,
1 for saturate,
2 for zero saturate

0 for truncated,
1 for rounded,
2 for truncated
Fixed-Point8-201
file Name of the external file None Required String

(required)
ArithType Arithmetic type: 0 for signed, None 0 [0, 1]/Integer

1 for unsigned
Rin Input impedance Ohm 32 (0,Inf]/Real
Ports
Input Input signal (fixed point real number)
Output Output signal (floating point real number)
Limits
1. outW > outD, coefW > coefD for signed arithmetic
Notes
1. This model implements an FIR filter based on filter tap coefficients provided by the two-col-
umn XY format data block in the external file. Each (X,Y) entry indicates the tap number and
the corresponding tap coefficient. The coefficients are floating point numbers. They are con-
verted to fixed-point number according to the parameters: coefW, coefD, ovf, quant, arith-
type. The format of the output signal is specified by the parameters: outW, outD, ovf, quant,
arithtype. Note that if useInAsOut is set to 1, the format of the fixed output number is set to
be the format of the input fixed point number, ignoring the parameters outW, outD, ovf,
quant, arithtype.
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Netlist Form
FXTFIR:NAME n1 n2 [useInAsOut=val] [coefW=val] [coefD=val]
[outW=val] [outD=val] [ovf=val] [quant=val] [file=val]
[arithtype=val] [Rin=val] [Rout=val]
Fixed-Point8-202
Example
FXTFIR:1 1 2 useInAsOut=0 coefW=16 coefD=4 outW=24 outD=8 ovf=1
quant=1 file=”filename”
Fixed-Point8-203
Fixed-Point IIR Filter (FXTIIR)

FXTIIR
useInAsOut Use the input precision as the output None 1 [0, 1]/Integer
precision:
1 for used,
0 for not used
coefW Word length of fixed point coefficient None 32 [1, 32]/Integer
coefD Precision of the fixed-point coefficient None 0 [0, 32]/Integer
outW Word length of the output fixed-point None 32 [0, 32]/Integer

number
outD Precision of the output fixed-point None 0 [0, 32]/Integer

number

0 for wrapped,
1 for saturate,
2 for zero saturate

0 for truncated,
1 for rounded,
2 for truncated 0
file Name of the external file None Required String
Fixed-Point8-204
ArithType Arithmetic type: 0 for signed, 1 for None 0 [0, 1]/Integer

unsigned
Ports
Limits
1. outW > outD, coefW > coefD for signed arithmetic
Notes
1. This model implements IIR filter based on the following system function:
M
–k
∑ bk z
k=0
H ( z ) = -------------------------------
-
N
–k
1+ ∑ ak z
k=1
or equivalently, the difference equation:
N M
y(n) = – ∑ ak y ( n – k ) + ∑ bk x ( n – k )
k=1 k=0
The system parameters (ak) and (bk) and are provided by a two-column XY format data block
in an external file. The first column is the (ak) value. The second column is the (bk) value. The
coefficients are floating point numbers. They are converted to fixed point number according to
the parameters: coefW, coefD, ovf, quant, arithtype. The format of the output is specified by
the parameters: outW, outD, ovf, quant, arithtype. Note that if useInAsOut is set to 1, the
format of the fixed output number is set to be the format of the input fixed point number. That
Fixed-Point8-205
is to say, the values outW, outD, ovf, quant, arithtype are ignored in this case.
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Netlist Form
FXTIIR:NAME n1 n2 [useInAsOut=val] [coefW=val] [coefD=val]
[outW=val] [outD=val] [ovf=val] [quant=val] [file=val]
Netlist Example
FXTIIR:1 1 2 useInAsOut=0 coefW=16 coefD=4 outW=24 outD=8 ovf=1
quant=1 file=”filename”
Fixed-Point8-206
Fixed-Point Real Adder (FXTRADD)

FXTRADD

output precision:
1 for use,
0 for not use

fixed point number

point number
ovf Overflow characteristic: 0 for None 0 [0, 2]/Integer

wrapped, 1 for saturate, 2 for
zero saturate

0 for truncated,
1 for rounded,
2 for truncated 0
ArithType Arithmetic type: 0 for signed, None 0 [0, 1]/Integer

1 for unsigned
Fixed-Point8-207
Ports
Limits
1. outW > outD for signed arithmetic
Notes
1. This model produces the result of the sum of two input fixed point real signals. It is assumed
that the user will assign the same format for the two inputs. The fixed point output signal for-
mat is the same as the input signal format when the parameter useInAsOut is set to be 0, in
which case parameters outW, outD, ovf, quant and arithtype will be ignored; otherwise, the
format is set by outW, outD, ovf, quant and arithtype.
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Netlist Form
FXTRADD:NAME n1 n2 n3 [useInAsOut=val] [outW=val] [outD=val]
[ovf=val] [quant=val] [arithtype=val] [Rin1=val] [Rin2=val]
[Rout=val]
Example
FXTRADD:1 1 2 3 useInAsOut=0, outW=16, outD=4, ovf=1, quant=1
Fixed-Point8-208
Fixed-Point Real Delay Element (FXTRDELAY)

FXTRDELAY
n1 n2
FXTRDELAY
changeIn_Prec Change the incoming precision None 0 [0, 1]/Integer

of the signal:
0 for no change,
1 for change
outW Word length of the output fixed None 32 [0, 1]/Integer

point number

point number

0 for wrapped,
1 for saturate,
2 for zero saturate

0 for truncated,
1 for rounded,
2 for truncated 0
D Number of delay None 1 [1, Inf)/Integer
ArithType Arithmetic type: 0 for signed, 1 None 0 [0, 1]/Integer

for unsigned
Fixed-Point8-209
Ports
Limits
Notes
1. This model delays a fixed-point real signal by a specified number of samples set by the param-
eter D. It will effectively place D zeros at the beginning of the output signal. The output signal
will follow the same format as the input signal if changeInPrec is set to 0, or the output fixed-
point format will be set by the user through the parameters outW, outD, ovf, quant, arith-
type.
2. The following plot shows the relationship between worldlength and precision.
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Netlist Form
FXTRDELAY:NAME n1 n2 [changeInPrec=val] [outW=val] [outD=val]
[ovf=val] [quant=val] [D=val] [arithtype=val] [Rin=val]
[Rout=val]
Example
FXTRDELAY:1 n1 n2 changeInPrec=1 outW=16 outD=4 ovf=1 quant=1
D=2
Fixed-Point8-210
Fixed-Point Real Multiplier (FXTRMULT)

FXTRMULT
n1
n3
FXTRMULT
n2
useInAsOut Use the input precision as None 1 [0, 1]/Integer

the output precision: 1 for
use, 0 for not use 1

fixed point number 32
outD Precision of the output None 0 [0, 32]/Integer

fixed point number

0 for wrapped,
1 for saturate,
2 for zero saturate
quant Quantization None 0 [0, 2]/Integer

characteristic:
0 for truncated,
1 for rounded,
2 for truncated 0
ArithType Arithmetic type: 0 for None 0 [0, 1]/Integer

signed, 1 for unsigned
Fixed-Point8-211
Ports
Input1 Input1 signal (fixed point number)
Input2 Input2 signal (fixed point number)
Output Output signal (fixed point number)
Limits
Notes
1. This model produces the result of the multiplication of two input fixed point signals. It is
assumed that the user will assign the same format for the two inputs. The fixed point output
signal format is the same as the input signal format when the parameter useInAsOut is set to
be 0, in which case outW, outD, ovf, quant and arithtype ignored; otherwise, the format is
set by outW, outD, ovf and quant, arithtype.
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Netlist Form
FXTRMULT:NAME n1 n2 n3 [useInAsOut=val] [outW=val] [outD=val]
[Rout=val]
Netlist Example
FXTRMULT:1 1 2 3 useInAsOut=0 outW=16 outD=4 ovf=1 quant=1
Fixed-Point8-212
Fixed-Point Real Scaler (FXTRSCALE)

FXTRSCALE
useInAsOut Use the input precision as None 1 [0, 1]/Integer

the output precision: 1 for
use, 0 for not use
coefW Word length of fixed None 32 [1, 32]/Integer

point coefficient
coefD Precision of the fixed None 0 [0, 32]/Integer

point coefficient

fixed point number

fixed point number

0 for wrapped,
1 for saturate,
2 for zero saturate

characteristic:
0 for truncated,
1 for rounded,
2 for truncated 0
Fixed-Point8-213
gain Gain of the scaler None 1 (Inf, -Inf)/Real

Ports
Limits
outW > outD, coefW > coefD for signed arithmetic
Notes
1. This model produces the result of the multiplication of the input signal with the coefficient.
The coefficient is a fixed-point number converted from the parameter value “gain” according
to the user defined format coefW, coefD, ovf, quant, arithtype. The fixed point output signal
format is the same as the input signal format when the parameter useInAsOut is set to be 0, in
which case outW, outD, ovf, quant and arithtype ignored. Otherwise, the output format is set
by outW, outD, ovf, quant and arithtype.
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Netlist Form
FXTRSCALE:NAME n1 n2 [useInAsOut=val] [coefW=val] [coefD=val]
[outW=val] [outD=val] [ovf=val] [quant=val] gain=val
Netlist Example
FXTRSCALE:1 1 2 useInAsOut=0 coefW=16 coefD=4 outW=24 outD=8
ovf=1 quant=1 gain=2.34
Fixed-Point8-214
Fixed-Point Real Subtractor (FXTRSUB)

FXTRSUB

output precision: 1 for use, 0
for not use

fixed point number

point number

0 for wrapped,
1 for saturate,
2 for zero saturate

0 for truncated,
1 for rounded,
2 for truncated 0
ArithType Arithmetic type: 0 signed, 1 None 0 [0, 1]/Integer

for unsigned
Fixed-Point8-215
Ports
Limits
Notes
1. This model produces the result of the subtraction of two input fixed point real signals. It is
assumed that the user will assign the same format for the two inputs. The fixed point output
signal format is the same as the input signal format when the parameter useInAsOut is set to
be 0, in which case parameters outW, outD, ovf, quant and arithtype will be ignored; other-
wise, the format is set by outW, outD, ovf, quant and arithtype.
xxxx.xxxxxxxx
d
w
Netlist Form
FXTRSUB:NAME n1 n2 n3 [useInAsOut=val] [outW=val] [outD=val]
[Rout=val]
Example
FXTRSUB:1 1 2 3 useInAsOut=0 outW=16 outD=4 ovf=1 quant=1
Fixed-Point8-216
Sampling Rate Decimator for Fixed-Point Real Signal
Sampling Rate Decimator for Fixed-Point Real Signal (FXTSRD)

FXTSRD
DF The factor by None 1 [1, Inf)/Integer

which the input
signal is
decimated
Rout Output Ohm 0 [0, Inf)/Real

impedance
Ports
Notes
This model decimates a fixed point input signal. Beginning with the first input sample, only each
DFth sample is written to the output port. The format of the output signal remains the same as the
format of the input signal.
Netlist Form
FXTSRD:NAME n1 n2 DF=val [Rin=val] [Rout=val]
Netlist Example
FXTSRD:1 1 2 DF=2
Fixed-Point8-217
Sampling Rate Expander for Fixed-Point Real Signal
Sampling Rate Expander for Fixed-Point Real Signal (FXTSRE)

FXTSRE
EF The factor by None 1 [1, Inf)/Integer

which the input
signal is expanded
Ports
Notes
This model expands a fixed point input signal. Beginning with the first input sample, each input
sample followed by EF – 1 zeros are written to the output port. The format of the output signal
remains the same as the format of the input signal.
Netlist Form
FXTSRE:NAME n1 n2 EF=val [Rin=val] [Rout=val]
Netlist Example
FXTSRE:1 1 2 EF=2
Fixed-Point8-218
Fixed-Point to Complex Converter (FXTTOC)

FXTTOC
IorQ In-phase quadrature None 0 [0, 1]/Integer

component:
0 for in-phase,
1 for quadrature
Ports
Output Output signal (floating point complex number)
Notes
This model converts the real fixed point signal to a complex floating point signal. The fixed-point
input signal is transformed to the real part if IorQ is 1; otherwise, it is transformed to the imaginary
part.
Netlist Form
FXTTOC:NAME n1 n2 [IorQ=val] [Rin=val] [Rout=val]
Fixed-Point8-219
Netlist Example
FXTTOC:1 1 2 IorQ=1
Fixed-Point8-220
Fixed-Point to Fixed-Point Converter (FXTTOFXT)

FXTTOFXT
Properties Description Units Default Range/type
outW Word length of the None 32 [1, 32]/Integer

output fixed point
number

fixed point number

0 for wrapped,
1 for saturate,
2 for zero saturate

characteristic:
0 for truncated,
1 for rounded,
2 for truncated 0

Ports
Fixed-Point8-221
Input Input signal : (fixed point real number)
Limits
Notes
This model converts the real fixed point input signal to a real fixed-point signal of a different for-
mat. The output format is set by the user specified parameters: outW, outD, ovf , quant and arith-
type, where ovf defines the overflow characteristics, quant defines the quantization characteristics
and arithtype defines the arithmetic type. The following plot shows the relationship between the
word length and the precision.
xxxx.xxxxxxxx
d
w
Netlist Form
FXTTOFXT:NAME n1 n2 [outW=val] [outD=val] [ovf=val] [quant=val]
Netlist Example
FXTTOFXT:1 1 2 outW=24 outD=4 ovf=1 quant=1
Fixed-Point8-222
Fixed-Point to Real Converter (FXTTOR)
Fixed-Point to Real Converter (FXTTOR)

FXTTOR
Rout Output Ohm 0 [0, Inf)/Real

impedance
Ports
Input Input signal ( fixed point real number)
Notes
This model converts the real fixed point input signal to a real floating-point signal.
Netlist Form
FXTTOR:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FXTTOR:1 1 2
Fixed-Point8-223
Real to Fixed-Point Converter (RTOFXT)

RTOFXT

fixed-point number
outD Precision of the output fixed- None 0 [1, 32]/Integer

point number

0 for wrapped,
1 for saturate,
2 for zero saturate

0 for truncated, 1 for rounded, 2
for truncated 0
ArithType Arithmetic type: 0 for signed, 1 None 0 [0, 1]/Integer

for unsigned
Ports
Input Input signal (floating point real number)
Fixed-Point8-224
Limits
Notes
This model converts the real floating point input signal to real fixed-point signal. The output format
is set by the user specified parameters: outW, outD, ovf, quant and arithtype, where ovf defines
the overflow characteristics, quant defines the quantization characteristics and arithtype defines
the arithmetic type. The following plot shows the relationship between the word length and the pre-
cision.
xxxx.xxxxxxxx
d
w
Netlist Form
RTOFXT:NAME n1 n2 [outW=val] [outD=val] [ovf=val] [quant=val]
Example
RTOFXT:1 1 2 outW=16 outD=4
Fixed-Point8-225
9
Frequency Synthesizers
Frequency Synthesizers9-226
Charge Pump (CPUMP)
Charge Pump (CPUMP)

CPUMP
n1
CPUMP n3
n2
I_UP Up current uA 160 [0, Inf)/Real
UP_NFLOOR Up current noise floor in None 1e-25 [0, Inf)/Real

A^2/Hz
UP_FC Up current flicker corner Hz 10000 (0, Inf)/Real

frequency
UP_NOISE Up current noise: 1 for On, None 1 [0, 1]/Integer

0 for Off
I_DOWN Down current uA 160 [0, Inf)/Real
DOWN_NFL Down current noise floor A^2/Hz 1e-25 [0, Inf)/Real

OOR in A^2/Hz
DOWN_FC Down current flicker Hz 10000 (0, Inf)/Real

corner frequency
DOWN_NOI Down noise: 1 for On, 0 None 1 [0, 1]/Integer

SE for Off
STARTTIME Start time for pumping Sec 0 [0, Inf)/Real

total output current
STOPTIME Stop time for pumping Sec Inf [0, Inf)/Real

total output current
Charge Pump (CPUMP)
I_TRICKLE Trickle current Current 40uA (0, Inf)/Real
TRICKLE_NF Trickle current noise floor A^2/Hz 1e-25 (0, Inf)/Real

LOOR in A^2/Hz
TRICKLE_FC Trickle current flicker Hz 10000 (0, Inf)/Real

corner frequency
TRICKLE_N Trickle current noise: 1 for None 1 [0, 1]/Integer

OISE On, 0 for Off
Ports
Notes
1. This element models the behavior of the charge pump device.
2. Let the first input signal be Vup ( t ) , the second input signal be V
down
(t) , and the output signal be
V ( t ) , the output signal is calculated like this:
out
V out ( t ) = ( I up V up ( t ) – I down V down ( t ) + I trickle + I noise ) • Rout
3. In the above equation, the term Inoise is formed by two parts: one part is the noise from the
trickle current, the other part is the noise either from the up current or from the down current
depending on which one is active at that time instance. The user has the option to turn off the
noise for the three noise sources, if any of the noise sources is turned off, no noise will be gen-
Charge Pump (CPUMP)
erated for that source. Note that noise simulation is expensive, turning off the noise option will
speed up the simulation.
4. In general, for typical PLL applications, the two input impedances should be set to default
(INF), and the output impedance should be set to a large value, normally 1e10 is good enough.
Netlist Form
CPUMP:Name n1 n2 n3 [I_UP=val] [UP_NFLOOR=val] [UP_FC=val]
+[UP_NOISE=val][I_DOWN=val] [DOWN_NFLOOR=val] [DOWN_FC=val]
+[DOWN_NOISE=val] [STARTTIME=val] [STOPTIME=val]
+[I_TRICKLE=val] [TRICKLE_NFLOOR=val] [TRICKLE_FC=val]
+[TRICKLE_NOISE=val] [SEED=val] [RIN1=val] [RIN2=val]
+[ROUT=val]
Netlist Example
CPUMP:1 1 2 3 IUP=160uA IDOWN=160uA ITRICKLE=40uA FC=1000Hz
Frequency Divider (FREQDIV)

FREQDIV
N Frequency Division Factor None 1 (0, Inf)/Integer
FLOOR Noise floor in dB None -500 (-Inf, Inf)/Real
FLICKER Divider flicker corner Hz 10000 (0, Inf)/Real

frequency
NOISEON Noise: 1 for ON, 0 for OFF None 1 [0, 1]/Integer
WAVETYPE Incoming signal waveform None 0 [0, 1]/Integer

type: 0 for sinusoid, 1 for
sawtooth
VPIN Incoming signal peak voltage Volt 1 (0, Inf)/Real

value (valid for sawtooth
option)
Ports
Notes
1. This component models the frequency divider device. The division ratio is determined by the
parameter N.
2. The input signal can be either of base-band sawtooth waveforms or envelope signals. When it
is a sawtooth input signal, the user has to specify the corresponding peak voltage value
“VPIN” of the incoming signal to make the model behave properly.
3. The parameters “FLOOR” and “FLICKER” are used to specify the noise characteristic of the
divider device. When not needed, the noise simulation should be turned off by setting
“NOISEON” to 0, this will normally speed up the simulation since it is expensive to simulate
noise statistically.
4. In typical PLL applications, this model is used together with the reference oscillator to divide
down the reference frequency (called R divider). Note, however, that using this component as
a reference divider requires the use of base-band sawtooth waveforms.
Netlist Form
FREQDIV:Name n1 n2 N=val [SEED=val] [FLOOR=val] [FLICKER=val]
[NOISEON=val] [WAVETYPE=val] [VPIN=val] [RIN=val]
+ [ROUT=val]
Netlist Example
FREQDIV:1 1 2 N=10 FLOOR=-160dB FLICKER=15000Hz WAVETYPE=1
Phase and Frequency Comparator (PFCOMP)

PFCOMP
VL Low voltage level Volt 0 (-Inf, Inf)/Real
VH High voltage level Volt 1 (-Inf, Inf)/Real
Ports
Limits
1. VL < VH
Notes
1. PFCOMP acts like an exclusive OR gate with settable levels. This is the same as Phase Com-
parator on the MC14046 IC.

2. Let VTH = (VL + VH)/2
Vh if V1 (t) ≤ VTH and V2 (t) > VTH

Vh if V1 (t) > VTH and V2 (t) ≤ VTH

V3 ( t ) = 
 V1 if V1 (t) ≤ VTH and V2 (t) ≤ VTH
 V1 if V1 (t) > VTH and V2 (t) > VTH
where V1(t) and V2(t) are two input signals and V3(t) is the output signal.
3. The two input signal voltages to the PFCOMP element are shown; PFCOMP parameters are
VL=3 and VH=5.
Netlist Form
PFCOMP:Name n1 n2 n3 VL=val VH=val [Rin1=val] [Rin2=val]
[Rout=val]
Netlist Example
PFCOMP:1 1 2 3 VL=3 VH=5
Tri-State Phase Frequency Detector (PFDET)

PFDET
VLin Input low voltage level Volt 0 (-Inf, Inf)/Real
VHin Input high voltage level Volt 1 (-Inf, Inf)/Real
VLout Output low voltage level Volt 0 (-Inf, Inf)/Real
VHout Output high voltage level Volt 1 (-Inf, Inf)/Real
AMMOD Amplitude modulation: None 0 [0, 1]/Integer

0: Without modulation
1: With modulation
NC Noise constant in dB dB -500 (-Inf, Inf)/Real
Fr Reference frequency Hz 1 (0, Inf)/Real
Seed Random seed None 0 [0, Inf)/Integer
NoiseOn Noise: 1 for On, 0 for Off None 1 [0, 1]/Integer
Ports
Notes
1. This element models the digital behavior of common D flip-flop type tri-state phase-frequency
detectors often used in phase-locked loops.
2. The parameters VLin and VHin define the voltage level of the input signal. If an input signal is
below VLin, it will be limited to VLin. If the signal is higher than VHin, it will be assumed to
be VHin. The output level is set by VLout and VHout in a similar fashion.
3. The threshold at which the phase detector is triggered is determined by (VLin + VHin)/2.
4. This model can handle any type of input signals. The two inputs are usually from a reference
oscillator and a divided VCO signal for phase-locked-loop applications.
5. In order to avoid large amount of time jitter and phase noise that would normally be introduced
by not using a high enough sampling rate (higher sampling rate means slower simulation), the
two output signals can be chosen to be amplitude modulated by setting AMMOD to 1. The so-
called amplitude modulation works as follows: if based on the threshold-crossing line, the
pulse width should be 1ms but the simulation timestep is 100ms, then the output amplitude or
that timestep would be 1% of the VHout value. In detecting the pulse width, linear interpola-
tion is used. Therefore, sawtooth waveforms are recommended.
6. The power spectrum of the noise contribution follows the equation L = Nc+ 10log(Fr) [1],
where Fr is the reference frequency in PLL applications and Nc is a constant that is equivalent
to the phase frequency detector noise with Fr = 1Hz.
7. When the parameter “NoiseOn” is set to 1, noise will be simulated. Otherwise, noise will not
be incorporated.
Netlist Form
PFDET:Name n1 n2 n3 n4 VLin=val VHin=val VLout=val VHout=val
+ [AMMOD=Val] [Nc=Val] [Fr=Val] [Seed=Val] [RIN1=Val]
+ [RIN2=Val] [ROUT1=Val] [ROUT2=Val]
Netlist Example
PFDET:1 1 2 3 4 VLin=-1 VHin=1 VLout=0 VHout=1
References
1. Ulrich L. Rohde, David P. Newkirk, “RF/Microwave Circuit Design for Wireless Applica-
tions.”
Voltage Controlled Oscillator (VCO)

VCO
FLO Center frequency MHz 800 (0, Inf)/Real
FC Flicker frequency of the Hz 1000 (0, Inf)/Real

semiconductor
QLOAD Loaded Q of the tuned circuit None 200 (0, Inf)/Real
F Noise factor None 10 (0, Inf)/Real
PSAV Average available power dBm 0 [0, Inf)/Real
R Equivalent noise resistance of Ohm 5000 (0, Inf)/Real

tuning diode
K Oscillator voltage gain Hz/V 1000 (0, Inf)/Real
T Temperature Cel 27 (0, Inf)/Real
FDEV Maximum phase noise frequency Hz 100 (0, Inf)/Real

offset from carrier
Seed Random seed None 0 [0, Inf)/Integer
Wavetype Output wave type None 0 [0, 1]/Integer

0: Sinusoid
1: Sawtooth
Ports
Notes
1. This is a Voltage Controlled Oscillator model. It can either output sinusoidal signal or sawtooth
signal depending on how the parameter “WAVETYPE” is set.
2. Suppose the output waveform is sinusoid, the relationship between the input and the output is
then given by
V out ( t ) = A cos ( 2 π f 0 t + θ ( t ) )
where A = 4R out P sav for evenlope analysis, or A = 8R out P sav for instantaneous
t
time t.
∫
analysis, and θ ( t ) = θ n ( t ) + 2 π K V in ( t ) dτ , θ n ( t ) is the random phase component at
0
3. If the user sets the output waveform option to be sawtooth, then sawtooth signal will be sent to
the output with the peak value “A” and the same phase information as the sinusoidal option.
4. The power spectral density for this random phase noise process is given by [1]
 f b2 f FkT 2kTRK 2 
-  1 + ----c- ------------- + -------------------- 
L ( F m ) = 10 log  1 + ---------------------------
 ( 2f m q load ) 2 f m 2p sav f m2 
A random phase noise process θ n (t ) is generated by filtering a white Gaussian random sequence
through a filter with a frequency response H ( f m ) , where H ( f m ) = L ( f m ) with
1 ≤ f m ≤ FDEV
If required, linear interpolation is applied in the time domain on the generated phase noise process
θ n (t ) to ensure it has the same sampling rate as that of the input signal. In general, the random
phase noise process θ (t ) is a slowly time-varying process.
n
5. To avoid aliasing the VCO output signal, the simulation sample rate should be set to twice the
maximum swing of the VCO. This swing is based on the Oscillator Voltage Gain parameter [K] and
the maximum allowed tuning voltage of the design.
SampleRate = 2 × Vmax × K
The VCO output must be a complex envelope signal so you have to also have to make sure your
sample rate is less than twice your VCO center frequency [FLO]. In general, your sample rate
should be in the range of:
10 × FREF < SampleRate < min{2 × FLO,2 × Vmax × K }
If you are limited by the FLO parameter, you will not be able to simulate the high-end of your tun-
ing voltage range.
Netlist Form
VCO:Name n1 n2 FLO=val [FC=val] [QLOAD=val] [F=val]
+ [PSAV=val] [R=val] K=val T=val [FDEV=val] [Seed=val]
+ [Wavetype=val] [Rin=Val] [Rout=Val]
Netlist Example
VCO:1 1 2 FLO=800MHZ FC=1KHZ QLOAD=200 F=10 PSAV=0dBm
+ R=5000OH K=1000 T=300DEG FDEV=100KHZ
References
1. Ulrich L. Rohde, J. Whitaker, and T.T.N. Bucher, “Communications Receivers” McGraw-Hill,
1996.
Voltage Controlled Oscillator with Frequency Divider
Voltage Controlled Oscillator with Frequency Divider (VCODIVBYN)

VCODIVBYN
VCO n3
n1
n4
N n5
n2
FLO Center frequency MHz 800 (0,Inf)/Real
FC Flicker frequency of the Hz 1000 (0,Inf)/Real

semiconductor
QLOAD Loaded Q of the tuned None 200 (0,Inf)/Real

circuit
F Noise factor None 10 (0,Inf)/Real
PSAV Average available power dBm 0 [0,Inf)/Real
R Noise resistance of tuning Ohm 5000 (0,Inf)/Real

diode
K Nominal oscillator voltage None 1000 (0,Inf)/Real

gain
T Temperature Cel 27 (0,Inf)/Real
SEED Random seed None 0 [0,Inf)/Integer
N Frequency division factor None 1 (0,Inf)/Integer
DivNoiseOn Divider noise: 1 for On, 0 None 1 [0,1]/Integer

for Off
VcoNoiseOn Vco noise: 1 for On, 0 for None 1 [0, 1]/Integer

Off
WAVETYPE Output waveform type None 0 [0, 1]/Integer

0: sinusoid
1: sawtooth
DIV_FLOOR Divider noise floor in dB None -500 (-Inf, Inf)/Real
DIV_FC Divider flicker corner Hz 10000 (0, Inf)/Real

frequency
FM1...n Frequency offset Hz 100 (0,Inf)/Real
SBN1...n Sideband noise in dB at dB -80 (-Inf,0)/Real

frequency offset
FILE Filename for FM, SBN None <Project> String

data
TSTART Time instance to start Sec 0 [0,Inf)/Real

measuring phase noise
FRACTION Division fraction of None 0 [0,1)/Real

fractional-N synthesizer
(for phase noise
measurement use)
FREF Reference frequency (for Hz 1000 (0, Inf)/Real

phase noise measurement
use)
V_1...n Voltage data point Volt 0 (0, Inf)/Real
K_1...n Oscillator voltage gain at None 0 (0, Inf)/Real

voltage data point
Rin1 Input1 impedance Ohm Inf (0,Inf]/Real
Rin2 Input2 impedance Ohm Inf (0,Inf]/Real
Ports
Input2 Input2 signal (real, optional)
Output1 Output1 signal (complex)
Output2 Output2 signal (complex, optional)
Output3 Output3 signal (real, optional)
Notes
1. This model combines the voltage controlled oscillator with the frequency divider.
2. The pin assignment is as follows: the first input is the tuning voltage signal; the second input
(optional, can be left open) is the instant division factor variation dN; the first output is the
divided VCO output; the second output (optional, can be left open) is the undivided VCO out-
put; the third output is the phase noise output, it is optional also.
3. The sawtooth waveform type option is valid for baseband output signal only. If the option is
set to be sawtooth when the actual signal is a bandpass signal, no action is taken.
4. The parameter “DIV_FLOOR” allows the user to specify noise floor due to the frequency
divider.
5. The indexed parameters “FM” and “SBN” allow the user to specify measured noise data.
When measured noise data is provided, the model will ignore the parameters QLOAD, F, R,
FC.
6. The “FILE” parameter identifies a data file for the phase noise parameters FM and SBN. The
filename must have a .dsp extension, and must be in DSP format:
xy
fm1 sbn1
...
fmN sbnN
Where the first column is the frequency offset in Hz and the second column is the sideband
noise in dB. For example:
xy
100 -80
1000 -90
...
If a valid “FILE” parameter is present, the data from the file will be used and the correspond-
ing “FM” and “SBN” parameters in the netlist will be ignored. Any “FM” and “SBN” parame-
ters in the netlist that are not also defined in the data file will be used.
7. When the parameter “VcoNoiseOn” is set to 1, VCO noise will be simulated. Otherwise, VCO
noise will not be incorporated in the simulation. The same happens to the divider noise. Note
that noise simulation is expensive, so when it is not needed, the two parameters should be
turned on.
8. Parameters "TSTART", "FRACTION", and "FREF" are used to directly output phase noise
data from the third output port. The TSTART time is set to value which is after the PLL is
locked. This insures that only steady-state phase noise samples are sent to the phase noise
probe. FRACTION is the fractional portion of the steady-state divide- ratio, and should be set
to 0 for integer-N PLL designs. Finally, FREF should be set to the reference or comparison fre-
quency that feeds the phase detector. If you choose to use this model without the divider, you
must set N equal to 1 and set FREF equal to FLO (Free-running VCO frequency).
9. Assume the output waveform type is set to be sinusoid. Let the signal from the first input be
Vin(t), and the signal from the second input be dN(t). The relationship between the inputs and
the outputs is given by
fc θ ( t ) -
V out1 ( t ) = A ( t ) cos  2 π -----------------------
-t + -----------------------
 N + dN ( t ) N + dN ( t )
V out2 ( t ) = A ( t ) cos ( 2 π f lo t + θ ( t ) )
Here, A = 4R out1 P sav for envelope analysis
or A = 8R out1 P sav for instantaneous analysis, and
θ ( t ) = θ n ( t ) + 2 π K ∫t V in ( τ ) dτ , θ n ( t ) is the random phase noise process, with the

0
power spectral density [1}:
 f b2 f FkT 2kTRK 2 
L ( F m ) = 10 log  1 + ----------------------------  1 + ----c- ------------
- + -------------------- 
 ( 2f m q load ) 2  f m 2p sav f m2 
A random phase noise process θ n ( t ) is generated by filtering a white Gaussian random sequence
through a filter with a frequency response H ( f m ) , where H ( f m ) = L ( f m )
In general, the random phase noise process θ n ( t ) is a slowly time-varying process.
9. If the user sets the output waveform option to be sawtooth, then sawtooth signal will be sent to
the output with the peak value “A” and the same phase information as the sinusoidal option.
10. If the user supplies the measured V-K data pair, that is the voltage and oscillator voltage gain
pair, the tuning sensitivity will be based on the data set instead of the nominal oscillator voltage
gain. At the same time, the K value in the noise spectrum calculation will be the average of the sup-
plied measured K values instead of the nominal value. Note that when supplying the V-K pairs, V
should be in ascending order. Also, if the actual tuning voltage is smaller than V_1, then K_1 will
be used; if the actual tuning voltage is larger than V_n, then K_n will be used.
11. An example using the VCODIVBYN in a fractional-N synthesizer design is provided with
Designer. Use the File menu to open InstallDirectory/Designer3/Examples/System/
Motorola_Fractional_Synthesizer.adsn. InstallDirectory is the directory where Designer is
installed. See the References under this topic for a paper describing this design and how it was sim-
ulated in Designer.
12. To avoid aliasing the VCO output signal, the simulation sample rate should be set to twice the
maximum swing of the VCO. This swing is based on the Oscillator Voltage Gain parameter [K] and
the maximum allowed tuning voltage of the design.
SampleRate = 2 × Vmax × K
The VCO output must be a complex envelope signal so you have to also have to make sure your
sample rate is less than twice your VCO center frequency [FLO]. In general, your sample rate
should be in the range of:
10 × FREF < SampleRate < min{2 × FLO,2 × Vmax × K }
If you are limited by the FLO parameter, you will not be able to simulate the high-end of your tun-
ing voltage range.
Netlist Form
VCODIVBYN:Name n1 n2 n3 n4 n5 FLO=val [FC=val] [QLOAD=val]
+[F=val][PSAV=val] [R=val] K=val T=val [SEED=val] [N=val]
+[DivNoiseOn=val] [VcoNoiseOn=val] [WAVETYPE=val]
+[DIV_FLOOR=val] [FM1..n=val] [SBN1..n=val] [FILE='filename']
+[TSTART=val] [FRACTION=val] [FREF=val]
+ [RIN1=val] [RIN2=val] [ROUT1=val] [ROUT2=val] [ROUT3=val]
Netlist Example
VCODIVBYN:1 1 2 3 4 5 FLO=800MHZ FC=1KHZ QLOAD=200 F=10
+ PSAV=0dbm R=5000OH K=1e6 T=290Kel

References
[1] Wael Al-Qaq, JianHua Gu, William J. Martin, and Jeffrey L. Cutcher, “Fast and Accurate Fraction-
al-N Synthesizer Simulation Using Ansoft Designer™”, Motorola, Inc., Copyright 2004. A PDF
version of this paper is provided in:
InstallDirectory/Designer3/Help/Frac_Synthesizer_IEEE_WAMI_2004.pdf
where InstallDirectory is the directory where Designer is installed.
[2] Ulrich L. Rohde, J. Whitaker, and T.T.N. Bucher, “Communications Receivers” McGraw-Hill,
1996.
10
IEEE802dot11a
IEEE802dot11a10-246
Baseband Transmitter (BTX11A)

BTX11A
MODULATION Modulation type None 2 [0, 3]/Integer
CODING Coding Rate None 2 [0, 2]/Integer
LENGTH Length of PSDU None 100 [1, 4095]/Integer

(number of octets)
S0 Initial state for None 93 [0, 127]/Integer

scrambling in
decimal value
Ports
Input PSDU bit stream (integer)
Output PSDU frame (complex)
IEEE802dot11a10-247
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM
0 Coding Rate = 1 / 2

Coding = 1 Coding Rate = 2 / 3
2 Coding Rate = 3 / 4

Notes
1. This model is a high level component of the IEEE 802.11a baseband transmitter. The block
diagram of this model is shown in Fig. 1, which does not include PSDU Generator. For some
details, please refer to the related models.
PSDU Convolutional
r1
Generator Padder Scrambler Encoder Puncturer Interleaver
SIGNAL
Field Bits Convolutional Interleaver
Encoder
Generator Preamble Preamble
Field
field
PPDU Frame Former

Generator
Modulator Pilot IFFT CP SIGNAL

Addition Addition PPDU Frame
field
r1 Pilot CP DATA field

Modulator Addition IFFT Addition
Fig.1 Block diagram of the IEEE 802.11a baseband transmitter

Netlist Form
BTX11A:NAME n1 n2 [MODULATION =val] [CODING =val]
+ [LENGTH =val] [S0=val] [RIN=val] [ROUT=val]
Netlist Example
BTX11A:1 1 2 MODULATION = 2 CODING= 2 LENGTH = 100 S0 = 93
References
1. IEEE Std 802.11a, Part 11: “Wireless LAN Medium Access Control (MAC) and Physical
IEEE802dot11a10-248
Layer (PHY) specifications: High-speed Physical Layer in the 5 GHz Band,” ISO/IEC 8802-
11:1999/Amd 1:2000(E).
IEEE802dot11a10-249
Convolutional Encoder, 802.11a (COD11A)

COD11A
PURPOSE Signal field {0}, None 1 [0,1]/Integer

DATA field {1}
MODULATION Modulation Type None 0 [0, 3]/Integer
CODING Coding Rate type None 0 [0, 2]/Integer

(number of
octets)

impedance
Ports
Input Bits before encoding (integer)
Output Bits after encoding (integer)
IEEE802dot11a10-250
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


Notes
1. This model can be used to encode the DATA field and SIGNAL field according to IEEE
802.11a standard.
2. The convolutional encoder shall use the industry-standard generator polynomials,gd = 133 and
gl = 171 , of rate R = 1/2, as shown in Fig.1. The bit denoted as “A” shall be output from the
encoder before the bit denoted as “B.”
3. The initial state of convolutional encoder is set to “all zero.” When the next DATA field
arrives, the initial state of convolutional encoder is reset to “all zero”. The number of bits of
DATA field, NData, can be determined by the three parameters, Modulation, Coding, and
Length. For the calculation of NData, please refer to the PAD11A model.
Output Data A
Input Data Tb Tb Tb Tb Tb Tb
Output Data B
Fig.1 Convolutional encoder

Netlist Form
COD11A:NAME n1 n2 [PURPOSE =val] [MODULATION =val]
+ [CODING =val] [LENGTH =val] [RIN=val] [ROUT=val]
IEEE802dot11a10-251
Netlist Example
COD11A:1 1 2 MODULATION = 2 CODING= 2 LENGTH = 100
References
11:1999/Amd 1:2000(E).
2. J. Terry and J. Heiskala, Proakis, OFDM Wireless LANs: A Theoretical and Practical Guide,
Sams Publishing, 2002.
IEEE802dot11a10-252
CP Addition, 802.11a (CPADD11A)

CPADD11A
PURPOSE SIGNAL field {0} None 1 [0, 1]/Integer

DATA field {1}
CODING Coding Rate Type None 0 [0, 2]/Integer
LENGTH Length of PSDU (number of None 100 [1, 4095]/Integer

octets)
Ports
Input Signal before cyclic prefix addition (complex)
Output Signal after cyclic prefix addition (complex)
IEEE802dot11a10-253
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


Notes
1. This model can be used to add cyclic prefix (CP) into the outputs of 64-point IFFT, according
to IEEE 802.11a standard.
2. The input time domain signal χ0,...,63 are extended using cyclic prefix (CP) as follows:
 xk +48 0 ≤ k ≤ 15

y k =  xk −16 16 ≤ k ≤ 79
 x0 k = 80
(1)
and then multiplied with the window function
0.5 k =0

W (k ) =  1 1 ≤ k ≤ 79
0.5 k = 80
(2)
3. The time domain samples of SIGNAL field are appended with one sample overlap to the pre-
amble. The time domain samples of the first DATA symbol are appended with one sample
overlap to the SIGNAL field symbol. The symbols of DATA field are appended after the other
with one sample overlap.
Netlist Form
CPADD11A:NAME n1 n2 [PURPOSE =val] [MODULATION =val]
Netlist Example
CPADD11A:1 1 2 MODULATION = 2 CODING= 2 LENGTH = 100
IEEE802dot11a10-254
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-255
CP Removal, 802.11a (CPRM11A)

CPRM11A
PURPOSE SIGNAL field {0} None 1 [0, 1]/Integer

DATA field {1}
SOURCE Signal field/Data field {0} None 0 [0, 1]/Integer

PPDU Frame {1}

octets)
Ports
Input Signal before cyclic prefix removed (complex)
Output Signal after cyclic prefix removed (complex)
IEEE802dot11a10-256
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


Notes
1. This model can be used to remove the symbol cyclic prefix (CP) that the cpadd11a model
added to the outputs of 64-point IFFT, according to IEEE 802.11a standard. For details, please
refer to the cpadd11a model.
2. It should be noted that if the parameter Source is set to SIGNAL field/DATA field {0}, the
input of the model is connected to the output of the cpadd11a model. If Source is set to PPDU
Frame {1}, the input of the model should be connected to the output of the pform11a model.
the cprm11a model extracts SIGNAL field or DATA field from the PPDU frame, which
depends on the parameter Purpose.
3. Fig.1 shows a block diagram of the IEEE 802.11a baseband receiver (basic components).
PPDU Frame CP Pilot r1

Removal FFT Removal Demodulator Deinterleaver
DATA field
r1 Viterbi
Depuncturer Descrambler Depadder PSDU bits
Decoder
Fig. 1 Block diagram of the IEEE 802.11a baseband receiver (basic components)
Netlist Form
CPRM11A:NAME n1 n2 [PURPOSE =val] [SOURCE =val]
+ [MODULATION =val] [CODING =val]+ [LENGTH =val] [RIN=val]
+ [ROUT=val]
Netlist Example
CPRM11A:1 1 2 MODULATION = 2 CODING= 2 LENGTH = 100
IEEE802dot11a10-257
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-258
Deinterleaver, 802.11a (DEILV11A)

DEILV11A
MODULATION Modulation type None 0 [0,3]/Integer
Ports
Input Bits before deinterleaving (integer)
Output Bits after deinterleaving (integer)
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM
Notes
1. This model can be used for data deinterleaving, according to IEEE 802.11a standard.
2. All demodulated data bits shall be deinterleaved by a block deinterleaver with a block size cor-
responding to the number of bits in a single OFDM symbol, NCBPS. The deinterleaver, which
performs the inverse relation of the interleaver, is also defined by a two-step permutation.
3. Here we shall denote by J the index of the original received bit before the first permutation; i
IEEE802dot11a10-259
shall be the index after the first and before the second permutation, and k shall be the index
after the second permutation, just prior to delivering the coded bits to the convolutional (Vit-
erbi) decoder. The first permutation is defined by the rule
i = s × floor( j s ) + ( j + floor(16 × j N CBPS )) mod s j = 0, 1,… N CBPS − 1 (1)
where the function floor (.) denotes the largest integer not exceeding the parameter, and
s = max ( N BPSC 2 , 1) (2)
This permutation is the inverse of permutation described in Eqn.(2) of the model intlv11a. The
second permutation is defined by the rule
k = 16 × i − (N CBPS − 1) floor(16 × i N CBPS ) i = 0,1,… N CBPS − 1 (3)
This permutation is the inverse of permutation described in Eqn.(1) of the model intlv11a. In
the above equations,NCBPS and NBPSC depend on the base modulation mode, as shown in
Table I.
Table I IEEE 802.11a Rate-dependent parameter
Coding bits Coding bits Data bits
per per OFDM per OFDM
Data rate Coding rate
Modulation subcarrier symbol symbol
(Mbits/s) (R)
(NBPSC) (NCBPS) (NDBPS)
6 BPSK 1/2 1 48 24
9 BPSK 3/4 1 48 36
12 QPSK 1/2 2 96 48
18 QPSK 3/4 2 96 72
24 16-QAM 1/2 4 192 96
36 16-QAM 3/4 4 192 144
48 64-QAM 2/3 6 288 192
54 64-QAM 3/4 6 288 216
Netlist Form
DEILV11A:NAME n1 n2 [MODULATION =val] [RIN=val] [ROUT=val]
Netlist Example
DEILV11A:1 1 2 MODULATION = 2
References
IEEE802dot11a10-260
11:1999/Amd 1:2000(E).
IEEE802dot11a10-261
Demodulator, 802.11a (DEMOD11A)

DEMOD11A
DECISION Hard decision {0}/ None 0 [0, 1]/Integer

Soft decision {1}
Ports
Input Signal before demodulation (complex)
Output Signal after demodulation (real)
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM
Notes
1. This model can be used for demodulation according to Gray-coded constellation mappings[1].
IEEE802dot11a10-262
For details, please refer to the MOD11a model.

2. Hard decision demodulator makes a definite determination of whether a zero or one bit was
transmitted, thus the outputs of the demodulator are zeros and ones. Soft decision demodulator
outputs information of the reliability of the decision along with a zero or one bit. The sign of
the soft decision indicators a zero or one bit, and the absolute value of each soft decision is the
distance to the decision boundary[2].
Netlist Form
DEMOD11A:NAME n1 n2 [MODULATION =val] [DECISION = val]
+ [RIN=val] [ROUT=val]
Netlist Example
DEMOD11A:1 1 2 MODULATION = 2
References
1. [1] IEEE Std 802.11a, Part 11: “Wireless LAN Medium Access Control (MAC) and Physical
11:1999/Amd 1:2000(E).
2. [2]J. Terry and J. Heiskala, Proakis, OFDM Wireless LANs: A Theoretical and Practical
Guide, Sams Publishing, 2002.
IEEE802dot11a10-263
Depadder, 802.11a (DPAD11A)

DPAD11A
LENGTH Length PSDU (number of None 100 [1, 4095]/Integer

octets)
Ports
Input Bits before depadding (integer)
Output Bits after depadding (integer)
IEEE802dot11a10-264
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


Notes
1. This model can be used to extract the PSDU bits from the DATA field bits by removing the
SERVICE field, tail bits and pad bits, according to IEEE 802.11a standard. For details, please
refer to the PAD11A model.
Netlist Form
DPAD11A:NAME n1 n2 [MODULATION =val] [CODING =val]
+ [LENGTH =val] [RIN=val] [ROUT=val]
Netlist Example
DPAD11A:1 1 2 MODULATION = 2 CODING= 2 LENGTH = 100
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-265
Depuncturer, 802.11a (DPUNC11A)

DPUNC11A
Ports
Input Signal before depuncturing (real)
Output Signal after depuncturing (real)
Limits


Notes
1. This model can be used to perform “depuncturing”, according to IEEE 802.11a standard.
2. The DATA field, composed of SERVICE, PSDU, tail, and pad parts, shall be coded with a
convolutional encoder of coding rate R = 1/2, 2/3, or 3/4, corresponding to the desired data
rate. The convolutional encoder shall use the industry-standard generator polynomials, g0 =
133z and gl = 133z, of rate R =1/2, please refer to the COD11A model. Higher rates are derived
IEEE802dot11a10-266
from it by employing “puncturing.” Puncturing is a procedure for omitting some of the

encoded bits in the transmitter (thus reducing the number of transmitted bits and increasing the
coding rate) and inserting a dummy “zero” metric into the convolutional decoder in the
receiver in place of the omitted bits. The “puncturing” and “depuncturing” procedure are illus-
trated in Fig.1a and Fig 1b.
Source Data X 0 X1 X 2 X 3 X 4 X 5 X 6 X 7 X 8
A0 A1 A2 A3 A4 A5 A6 A7 A8
Encoded Data Stolen Data
B0 B1 B2 B3 B4 B5 B6 B7 B8
Bit Stolen Data

(Sent/received data)
A0 B0 A1 B2 A3 B3 A4 B5 A6 B6 A7 B8
A0 A1 A2 A3 A4 A5 A6 A7 A8
Bit Inserted Data Inserted Dummy Data
B0 B1 B2 B3 B4 B5 B6 B7 B8
Decoded Data y0 y1 y2 y3 y4 y5 y6 y7 y8
Fig.1A The “puncturing” and “depuncturing” procedure for coding rate R = 3/4.
IEEE802dot11a10-267
Source Data X 0 X1 X 2 X 3 X 4 X 5
A0 A1 A2 A3 A4 A5
B0 B1 B2 B3 B4 B5
Bit Stolen Data

A0 B0 A1 A2B2 A3 A4B4 A5
A0 A1 A2 A3 A4 A5
B0 B1 B2 B3 B4 B5
Decoded Data y0 y1 y2 y3 y4 y5
Fig.1B The “puncturing” and “depuncturing” procedure for coding rate R = 2/3
Netlist Form
DPUNC11A:NAME n1 n2 [CODING=val] [RIN=val] [ROUT=val]
Netlist Example
DPUNC11A:1 1 2 CODING = 2
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-268
Descrambler, 802.11a (DSCRM11A)

DSCRM11A

(number of octets)
S0 Initial state of the None 93 [0, 127]/Integer

scrambler in
decimal
Ports
Input Bits before descrambling (integer)
Output Bits after descrambling (integer)
IEEE802dot11a10-269
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


Notes
1. This model can be used to descramble the DATA field, according to IEEE 802.11a standard.
The structure is the same as scrambler, as shown in Fig.1. For details, please refer to the model
SCRM11a.
Data In
x7 x6 x5 x 4 x 3 x 2 x1
Descrambed
Data Out
Fig.1 Data descrambler

Netlist Form
DSCRM11A:NAME n1 n2 [MODULATION =val] [CODING =val]
Netlist Example
DSCRM11A:1 1 2 MODULATION = 2 CODING= 2 LENGTH = 100 S0 = 93
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-270
FFT, 802.11a (FFT11A)
FFT, 802.11a (FFT11A)

FFT11A
Ports
Input Signal before FFT, time domain

representation (complex)
Output Signal after FFT, time domain
representation (complex)
Notes
1. This model can be used to implement 64-point Fast Fourier Transform (IFFT) according to
IEEE 802.11a standard.
2. In this model, a 64-point FFT is used. It should be noted that the coefficients of subcarriers at
the output are arranged from -32 to 31 rather than from 0 to 63. Therefore, the FFT mapping is
IEEE802dot11a10-271
FFT, 802.11a (FFT11A)
illustrated in Fig.1.
0 0 #0
1 1 #1
31 FFT 31 # 31
32 32 # -32
Frequency Domain Outputs
62 62 # -2
63 63 # -1
Fig.1 Inputs and outputs of FFT

Netlist Form
FFT11A:NAME n1 n2 [RIN=val] [ROUT=val]
Netlist Example
FFT11A:1 1 2
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-272
IFFT, 802.11a (IFFT11A)

IFFT11A
Ports
Notes
1. This model can be used to implement 64-point inverse Fast Fourier Transform (IFFT) accord-
ing to IEEE 802.11a standard.
2. In this model, a 64-point IFFT is used. It should be noted that the coefficients of subcarriers at
the input are arranged from -32 to 31 rather than from 0 to 63. Therefore, the IFFT mapping is
IEEE802dot11a10-273
illustrated in Fig.1.
#0 0 0
#1 1 1
# 31 31 IFFT 31
# -32 32 32
Time Domain Outputs
# -2 62 62
# -1 63 63
Fig.1 Inputs and outputs of IFFT

Netlist Form
IFFT11A:NAME n1 n2 [RIN=val] [ROUT=val]
Netlist Example
IFFT11A:1 1 2
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-274
Interleaver, 802.11a (INTLV11A)

INTLV11A
MODULATION Modulation type None 0 [0, 3]/Integer
Ports
Input Bits before interleaving (integer)
Output Bits after interleaving (integer)
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM
Notes
1. This model can be used for encoded data interleaving, according to IEEE 802.11a standard.
2. All encoded data bits shall be interleaved by a block interleaver with a block size correspond-
ing to the number of bits in a single OFDM symbol, NCBPS. The interleaver is defined by a
two-step permutation. The first permutation ensures that adjacent coded bits are mapped onto
nonadjacent subcarriers. The second ensures that adjacent coded bits are mapped alternately
IEEE802dot11a10-275
onto less and more significant bits of the constellation and, thereby, long runs of low reliability
(LSB) bits are avoided.
3. We shall denote by k the index of the coded bit before the first permutation; i, shall be the
index after the first and before the second permutation, and J shall be the index after the second
permutation, just prior to modulation mapping. The first permutation is defined by the rule
i = ( N CBPS 16)(k mod 16) + floor(k 16) k = 0,1,… N CBPS − 1 (1)
where the function floor (.) denotes the largest integer not exceeding the parameter. The sec-
ond permutation is defined by the rule
j = s × floor(i s ) + (i + N CBPS − floor(16 × i N CBPS )) mod s i = 0,1,… N CBPS − 1 (2)
where the value of s is determined by the number of coded bits per subcarrier, NBPSC , accord-
ing to
s = max ( N BPSC 2 , 1) (3)
In the above equations, NCBPS and NBPSC depend on the base modulation mode, as shown in
the following Table (IEEE 802.11a Rate-dependent parameter).
(Mbits/s) (R)
6 BPSK 1/2 1 48 24
9 BPSK 3/4 1 48 36
12 QPSK 1/2 2 96 48
18 QPSK 3/4 2 96 72
24 16-QAM 1/2 4 192 96
36 16-QAM 3/4 4 192 144
48 64-QAM 2/3 6 288 192
54 64-QAM 3/4 6 288 216
Netlist Form
INTLV11A:NAME n1 n2 [MODULATION =val] [RIN=val] [ROUT=val]
Netlist Example
INTLV11A:1 1 2 MODULATION = 2
References
IEEE802dot11a10-276
11:1999/Amd 1:2000(E).
IEEE802dot11a10-277
Modulator, 802.11a (MOD11A)

MOD11A
Ports
Input Bits before modulation (integer)
Output Modulated signal (complex)
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM
Notes
1. This model can be used for modulation according to Gray-coded constellation mappings[1].
2. The OFDM subcarriers can be modulated by using BPSK, QPSK, 16-QAM, or 64-QAM mod-
ulation, depending on the RATE requested. The encoded and interleaved binary serial input
data shall be divided into groups of NBPSC (1, 2, 4, or 6) bits and converted into complex num-
bers representing BPSK, QPSK, 16-QAM, or 64-QAM constellation points. The conversion
IEEE802dot11a10-278
shall be performed according to Gray-coded constellation mappings[1]. The output values, d,

are formed by multiplying the resulting I + jQ value by a normalization factor KMOD, as
described in Eqn.(1).
d = ( I + jQ ) × K MOD (1)
The normalization factor,KMOD, depends on the base modulation mode, as prescribed in Table
I. Note that the modulation type can be different from the start to the end of the transmission,
as the signal changes from SIGNAL to DATA, as shown in Fig.1. The purpose of the normal-
ization factor is to achieve the same average power for all mappings. In practical implementa-
tions, an approximate value of the normalization factor can be used, as long as the device
conforms with the modulation accuracy requirements described in [1].
For BPSK, b0 determines the I value, as illustrated in Table II. For QPSK, b0 determines the I
value and b1 determines the Q value, as illustrated in Table III. For 16-QAM, b0b1 determines
the I value and b2b3 determines the Q value, as illustrated in Table IV. For 64-QAM, b0b1b2
determines the I value and b2b3b4 determines the Q value, as illustrated in Table V. The input
bit, b0, is the earliest in the stream.
RATE Reserved LENGTH Parity Tail SERVICE PSDU Tail Pad Bits
4 bits 1 bit 12 bit 1 bit 6 bits 16 bits 6 bits
Coded/OFDM Coded/OFDM
(BPSK, R=1/2) (RATE is indicated in SIGNAL)
PLCP Preamble SIGNAL DATA

12 Symbols One OFDM Symbol Variable Number of OFDM Symbols
Fig.1 PPDU frame format

Table I IEEE 802.11a Modulation-dependent normalization factor KMOD
Modulation (KMOD)
BPSK 1
QPSK 1 2
16-QAM 1 10
64-QAM 1 42
IEEE802dot11a10-279
Table II IEEE 802.11a BPSK encoding table

Input bit (b0) I-out Q-out
0 -1 0
1 1 0
Table III IEEE 802.11a QPSK encoding table
Input bit (b0) I-out Input bit (b1) Q-out
0 -1 0 -1
1 1 1 1
Table IV IEEE 802.11a 16-QAM encoding table
Input bits I-out Input bits Q-out
(b0b1) (b2b3)
00 -3 00 -3
01 -1 01 -1
11 1 11 1
10 3 10 3
Table V IEEE 802.11a 64-QAM encoding table
Input bits I-out Input bits Q-out
(b0b1b2) (b3b4b5)
000 -7 000 -7
001 -5 001 -5
011 -3 011 -3
010 -1 010 -1
110 1 110 1
111 3 111 3
101 5 101 5
100 7 100 7
Netlist Form
MOD11A:NAME n1 n2 [MODULATION =val] [RIN=val] [ROUT=val]
Netlist Example
MOD11A:1 1 2 MODULATION = 2
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-280
IEEE802dot11a10-281
Padder, 802.11a (PAD11A)

PAD11A

octets)
Ports
Input Bits before padding (integer)
Output Bits after padding (integer)
IEEE802dot11a10-282
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


Notes
1. This model can be used to form DATA field bits by prepending the SERVICE field, add tail
bits and pad bits, according to IEEE 802.11a standard.
2. Fig.1 shows the format for the PPDU including the OFDM PLCP preamble, OFDM PLCP
header, PSDU, tail bits, and pad bits. The PLCP header contains the following fields:
LENGTH, RATE, a reserved bit, an even parity bit, and the SERVICE field. In terms of mod-
ulation, the LENGTH, RATE, reserved bit, and parity bit (with 6 “zero” tail bits appended)
constitute a separate single OFDM symbol, denoted SIGNAL, which is transmitted with the
most robust combination of BPSK modulation and a coding rate of R=1/2. The SERVICE field
of the PLCP header and the PSDU (with 6 “zero” tail bits and pad bits appended), denoted as
DATA, are transmitted at the data rate described in the RATE field and may constitute multi-
ple OFDM symbols. The tail bits in the SIGNAL symbol enable decoding of the RATE and
LENGTH fields immediately after the reception of the tail bits. The RATE and LENGTH are
required for decoding the DATA part of the packet. We will describe the DATA field in the
following sections
RATE Reserved LENGTH Parity Tail SERVICE PSDU Tail Pad Bits
4 bits 1 bit 12 bits 1 bit 6 bits 16 bits 6 bits
Coded/OFDM Coded/OFDM
(BPSK, R =1/2) (RATE is indicated in SIGNAL)
PLCP Preamble SIGNAL DATA

12 Symbols One OFDM Symbol Variable Number of OFDM Symbols
Fig.1 PPDU frame format

3. Service field (SERVICE)
The IEEE 802.11 SERVICE field has 16 bits, which shall be denoted as bits 0~15, as shown in
Fig.2. The bit 0 shall be transmitted first in time. The bits from 0~6 of the SERVICE field,
IEEE802dot11a10-283
which are transmitted first, are set to zeros and are used to synchronize the descrambler in the
receiver. The remaining 9 bits (7~15) of the SERVICE field shall be reserved for future use.
All reserved bits shall be set to zero.
Scrambler Initialization Reserved SERVICE Bits R: Reserved

"0" "0" "0" "0" "0" "0" "0" R R R R R R R R R
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Transmit Order
Fig.2 SERVICE field bit assignment

4. Tail bits field (TAIL)
The PPDU tail bits field shall be six bits of “0”, which are required to return the convolutional
encoder to the “zero state”. This procedure improves the error probability of the convolutional
decoder, which relies on future bits when decoding and which may be not be available past the
end of the message. The PLCP tail bit field shall be produced by replacing six scrambled
“zero” bits following the message end with six nonscrambled “zero” bits.
5. Pad bits (PAD)
The number of bits in the DATA field shall be a multiple of NCBPS, the number of coded bits
in an OFDM symbol (48, 96, 192, or 288 bits), as shown in Table I. To achieve that, the length
of the message is extended so that it becomes a multiple of NDBPS, the number of data bits per
OFDM symbol. NCBPS and NDBPS can be determined by the two parameters, Modulation and
Coding as shown in Table I. At least 6 bits are appended to the message, in order to accommo-
date the TAIL bits. The number of OFDM symbols NSYM the number of bits in the DATA field
NDATA and the number of pad bits NPAD are computed from the length of the PSDU (Length)
as follows:
N SYM = Ceiling((16 + 8 × Length + 6) N DBPS ) (1)
N DATA = N SYM × N DBPS (2)
N PAD = N DATA − (16 + 8 × Length + 6 ) (3)

The function ceiling (.) is a function that returns the smallest integer value greater than or equal
to its argument value. The appended bits (“pad bits”) are set to “zeros” and are subsequently
scrambled with the rest of the bits in the DATA field.
IEEE802dot11a10-284

(Mbits/s) (R) (NBPSC) (NCBPS) (NDBPS)
6 BPSK 1/2 1 48 24
9 BPSK 3/4 1 48 36
12 QPSK 1/2 2 96 48
18 QPSK 3/4 2 96 72
24 16-QAM 1/2 4 192 96
36 16-QAM 3/4 4 192 144
48 64-QAM 2/3 6 288 192
54 64-QAM 3/4 6 288 216
Netlist Form
PAD11A:NAME n1 n2 [MODULATION =val] [CODING =val]
Netlist Example
PAD11A:1 1 2 MODULATION = 2 CODING= 2 LENGTH = 100
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-285
PPDU Frame Former, 802.11a (PFORM11A)

PFORM11A
Ports
Input1 Preamble field (complex)
Input2 Signal field (complex)
Input3 Data field (complex)
Output PPDU Frame (complex)
IEEE802dot11a10-286
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


Notes
1. This model can be used to form PPDU frame, according to IEEE 802.11a standard.
2. Fig.1 shows a block diagram of the IEEE 802.11a baseband transmitter. One sample overlap
occurs between preamble and SIGNAL field as well as between SIGNAL field and DATA
field. The number of OFDM symbols during DATA field is determined by the three parame-
ters, Modulation, Coding, and Length.. For some details, please refer to the PAD11A model.
PSDU Convolutional
r1
Generator Padder Scrambler Encoder Puncturer Interleaver
SIGNAL
Field Bits Convolutional Interleaver
Encoder
Generator Preamble Preamble
Field
field
PPDU Frame Former

Generator
Modulator Pilot IFFT CP SIGNAL

Addition Addition PPDU
field
r1 Pilot CP DATA field

Modulator Addition IFFT Addition
Fig.1 Block diagram of the IEEE 802.11a baseband transmitter

Netlist Form
PFORM11A:NAME n1 n2 n3 n4 [MODULATION =val] [CODING =val]
+ [LENGTH =val] [RIN=val] [RIN1=val] [RIN2=val] [RIN3=val]
+ [ROUT=val]
IEEE802dot11a10-287
Netlist Example
PFORM11A:1 1 2 3 4 MODULATION = 2 CODING= 2 LENGTH = 100
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-288
Pilot Addition, 802.11a (PLTADD11A)

PLTADD11A
PURPOSE Signal field {0} None 1 [0, 1]/Integer

Data field {1}
CODING Coding rate type None 0 [0, 2]/Integer

octets)
Ports
Input Signal before pilot addition (complex)
Output Signal after pilot addition) (complex)
IEEE802dot11a10-289
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


Notes
1. This model can be used for pilot addition according to IEEE 802.11a standard.
2. In each OFDM symbol, four of the subcarriers are dedicated to pilot signals in order to make
the coherent detection robust against frequency offsets and phase noise. These pilot signals
shall be put in subcarriers –21, –7, 7 and 21. The pilots shall be BPSK modulated by a pseudo
binary sequence to prevent the generation of spectral lines. The contribution of the pilot sub-
carriers to each OFDM symbol is described in the following sections.
3. The stream of complex numbers at the output of modulation is divided into groups of NSD = 48
complex numbers. We shall denote this by writing the complex number dk,n which corre-
sponds to subcarrier k of OFDM symbol n, as follows:
d k ,n = d k + N SD ×n k = 0, 1,… N SD − 1 n = 0,1,… N SYM − 1
(1)
The number of OFDM symbols, NSYM, depends on the three parameters, Modulation, Coding,
and Length. For details, please refer to the pad11a model.
4. The contribution of the pilot subcarriers for the nth OFDM symbol is produced by Fourier
transform of sequence P, given by
P−26, 26 = { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 0, 0, 0, 0 }
(2)
The polarity of the pilot subcarriers is controlled by the sequence, Pn, which is a cyclic exten-
sion of the 127 elements sequence and is given by the following equation
P0..126 v = {1,1,1,1, - 1,-1,-1,1, - 1,-1,-1,-1, 1,1,-1,1, - 1,-1,1,1, - 1,1,1,-1, 1,1,1,1, 1,1,-1,1,
1,1,-1,1, 1,-1,-1,1, 1,1,-1,1, - 1,-1,-1,1, - 1,1,-1,-1, 1,-1,-1,1, 1,1,1,1, - 1,-1,1,1,
- 1,-1,1,-1, 1,-1,1,1, - 1,-1,-1,1, 1,-1,-1,-1, - 1,1,-1,-1, 1,-1,1,1, 1,1,-1,1, - 1,1,-1,1,
- 1,-1,-1,-1, - 1,1,-1,1, 1,-1,1,-1, 1,1,1,-1, - 1,1,-1,-1, - 1,1,1,1, - 1,-1,-1,-1, - 1,-1,-1}
(3)
Each sequence element is used for one OFDM symbol. The first element, P0, multiplies the
IEEE802dot11a10-290
pilot subcarriers of the SIGNAL symbol, while the elements from P1 on are used for the DATA
symbols.
The subcarrier frequency allocation is shown in Fig.1. To avoid difficulties in D/A and A/D
converter offsets and carrier feedthrough in the RF system, the subcarrier falling at DC (0th
subcarrier) is not used.Fig.1 Subcarrier frequency allocation
5. To meet 64-point requirement, 11 “zero” shall be put in subcarriers –32~-27 and 27~31.
d0 d 4 P−21 d 5 d17 P−7 d18 d 23DC d 24 d 29 P7 d 30 d 42 P21 d 43 d 47
-26 -21 -7 0 7 21 26
Subcarrier Numbers
Fig.1 Subcarrier frequency allocation

Netlist Form
PLTADD11A:NAME n1 n2 [PURPOSE =val] [MODULATION =val]
Netlist Example
PLTADD11A:1 1 2 MODULATION = 2 CODING= 2 LENGTH = 100
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-291
Pilot Removal, 802.11a (PLTRM11A)
Pilot Removal, 802.11a (PLTRM11A)

PLTRM11A
Ports
Input Signal before pilot removal (complex)
Output Signal after pilot removal (complex)
Notes
1. This model can be used for remove the pilot signal that the pltadd11a model added to the out-
puts of modulator, according to IEEE 802.11a standard. For details, please refer to the
pltadd11a model.
Netlist Form
PLTRM11A:NAME n1 n2 [RIN=val] [ROUT=val]
Netlist Example
PLTRM11A:1 1 2
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-292
Preamble Generator, 802.11a (PREAM11A)

PREAM11A
Ports
Output Preamble field (integer)
Notes
1. This model can be used to generate PLCP Preamble according to IEEE 802.11a standard.
2. The PLCP preamble field is used for synchronization. It consists of 10 short symbols and two
long symbols shown in Fig.1.
8 + 8 = 16µs
10 × 0.8 = 8µs 2 × 0.8 + 2 × 3.2 = 8µs 0.8 + 3.2 = 4 µs 0.8 + 3.2 = 4 µs 0.8 + 3.2 = 4 µs
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 GI2 T1 T2 GI SIGNAL GI Data 1 GI Data 2
Signal Detect, Coarse Freq. Channel and Fine RATE SERVICE+DATA DATA
AGC, Diversity Offset Estimation Frequency LENGTH
Selection Timing Synchronize Offset Estimation
Fig.1 OFDM training structure

3. Fig.1 shows the OFDM training structure (PLCP preamble), where fl and fID to denote short
IEEE802dot11a10-293
training symbols and Tl and T1 denote long training symbols. The PLCP preamble is followed
by the SIGNAL field and DATA field. The total training length is 16µs. The dashed bound-
aries in the figure denote repetitions due to the periodicity of the inverse Fourier transform.
4. A short OFDM training symbol consists of 12 subcarriers, which are modulated by the ele-
ments of the sequence S, given by
S −26, 26 = 13 6 × { 0, 0, 1 + j, 0, 0, 0, - 1 - j, 0, 0, 0, 1 + j, 0, 0, 0, - 1 - j, 0, 0, 0, - 1 - j, 0, 0, 0, 1 + j, 0, 0, 0,0,
0, 0, 0,-1 - j, 0, 0, 0, - 1 - j, 0, 0, 0, 1 + j, 0, 0, 0, 1 + j, 0, 0, 0, 1 + j, 0, 0, 0, 1 + j, 0, 0 }
The multiplication by a factor of (13/6)1/2 is in order to normalize the average power of the
resulting OFDM symbol, which utilizes 12 out of 52 subcarriers. To meet 64-point IFFT
requirement, 11 “zero” shall be put in subcarriers –32~-27 and 27~31, respectively. These
samples are transformed using IFFT, extended periodically for 161 samples (about 8 ms), and
then multiplied by the window function:
0.5 k =0

W (k ) =  1 1 ≤ k ≤ 159
0.5 k = 160
(2)
5. A long OFDM training symbol consists of 53 subcarriers (including a zero value at dc), which
are modulated by the elements of the sequence, L, , given by
L−26, 26 = {1, 1, - 1, - 1, 1, 1,-1, 1, - 1, 1, 1, 1, 1, 1, 1, - 1, - 1, 1, 1, - 1, 1, - 1, 1, 1, 1, 1, 0,
1, - 1, - 1, 1, 1, - 1, 1, - 1, 1, - 1, - 1, - 1, - 1, - 1, 1, 1, - 1, - 1, 1, - 1, 1, - 1, 1, 1, 1, 1} (3)
To meet 64-point IFFT requirement, 11 “zero” shall be put in subcarriers –32~-27 and 27~31.
The time domain samples are produced by performing IFFT, cyclically extending the results to
get cyclic prefix, and then multiplied by the window function:
0.5 k =0

W (k ) =  1 1 ≤ k ≤ 159
0.5 k = 160
(4)
The resulting 161 samples are appended with one sample overlap to the SIGNAL field symbol.
Netlist Form
PREAM11A:NAME n1 [RIN=val] [ROUT=val]
Netlist Example
PREAM11A:1 1
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-294
PSDU Generator, 802.11a (PSDU11A)

PSDU11A
NUM_OCTETS Number of octets None 100 [1, Inf]/Integer
Ports
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


IEEE802dot11a10-295
Notes
1. This model can be used to generate IEEE 802.11a PSDU bit stream.
2. The PSDU Generator generates random binary sequence, taking the value 1 or 0 with equal
probability. The number of bits equals Num_Octets x 8.
3. The output bit rate is determined by the first two parameters, Modulation and Coding, as
shown in Table I.
(Mbits/s) (R)
6 BPSK 1/2 1 48 24
9 BPSK 3/4 1 48 36
12 QPSK 1/2 2 96 48
18 QPSK 3/4 2 96 72
24 16-QAM 1/2 4 192 96
36 16-QAM 3/4 4 192 144
48 64-QAM 2/3 6 288 192
54 64-QAM 3/4 6 288 216
Netlist Form
PSDU11A:NAME n1 n2 [MODULATION =val] [CODING =val]
+ [NUM_OCTETS =val] [SEED =val] [ROUT=val]
Netlist Example
PSDU11A:1 1 2 MODULATION = 2 CODING= 2 NUM_OCTETS = 200
SEED=17427
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-296
PSDU Generator with External File, 802.11a
PSDU Generator with External File, 802.11a (PSDUF11A)

PSDUF11A
NUM_OCTETS Number of octets to read None 100 [1, Inf)/Integer

from external file
FILE Name of the external data None Required N/A

file
Ports
IEEE802dot11a10-297
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


File name must have a “.mat” extension.
Notes
1. This model generates IEEE 802.11a PSDU bit stream using an external file.
2. The PSDU Generator reads hexadecimal integer type data from a MATLAB file (extension
.mat) and converts it into a binary signal with the least significant bit (LSB) being outputted
first. The file should simply contain the ASCII data to be read out. If the file contains less data
than Num_Octets, then the data in the file is read periodically until Num_Octets data are read
out.
3. The output bit rate is determined by the first two parameters, Modulation and Coding, as
shown in Table I.
Data rate Coding rate subcarrier symbol symbol
Modulation
(Mbits/s) (R)
( N BPSC ) ( N CBPS ) ( N DBPS )
6 BPSK 1/2 1 48 24
9 BPSK 3/4 1 48 36
12 QPSK 1/2 2 96 48
18 QPSK 3/4 2 96 72
24 16-QAM 1/2 4 192 96
36 16-QAM 3/4 4 192 144
48 64-QAM 2/3 6 288 192
54 64-QAM 3/4 6 288 216
IEEE802dot11a10-298
Netlist Form
PSDUF11A:NAME n1 n2 [MODULATION =val] [CODING =val]
+ [NUM_OCTETS =val] [RIN=val] [ROUT=val] FILE = "filename"
Netlist Example
PSDUF11A:1 1 2 MODULATION = 2 CODING= 2 NUM_OCTETS = 200
+ FILE = "octets11a.mat"
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-299
Puncturer, 802.11a (PUNC11A)

PUNC11A
Ports
Input Bits before puncturing (integer)
Limits


Notes
1. This model can be used to increase coding rate by employing “puncturing”, according to IEEE
IEEE802dot11a10-300
802.11a standard.
2. The DATA field, composed of SERVICE, PSDU, tail, and pad parts, shall be coded with a
convolutional encoder of coding rate R = 1/2, 2/3, or 3/4, corresponding to the desired data
rate. The convolutional encoder shall use the industry-standard generator polynomials, g0 =
133 and gl = 171 and , of rate R = 1/2, please refer to the COD11A model. Higher rates are
derived from it by employing “puncturing”. Puncturing is a procedure for omitting some of the
encoded bits in the transmitter (thus reducing the number of transmitted bits and increasing the
coding rate) and inserting a dummy “zero” metric into the convolutional decoder in the
receiver in place of the omitted bits. The puncturing patterns are illustrated in Fig.1.
Source Data X 0 X1 X 2 X 3 X 4 X 5 X 6 X 7 X 8
A0 A1 A2 A3 A4 A5 A6 A7 A8
B0 B1 B2 B3 B4 B5 B6 B7 B8
Bit Stolen Data

A0 B0 A1 B2 A3 B3 A4 B5 A6 B6 A7 B8
A0 A1 A2 A3 A4 A5 A6 A7 A8
B0 B1 B2 B3 B4 B5 B6 B7 B8
Decoded Data y0 y1 y2 y3 y4 y5 y6 y7 y8
Fig.1A The “puncturing” and “depuncturing” procedure for coding rate R = 3/4
IEEE802dot11a10-301
Source Data X 0 X1 X 2 X 3 X 4 X 5
A0 A1 A2 A3 A4 A5
B0 B1 B2 B3 B4 B5
Bit Stolen Data

A0 B0 A1 A2B2 A3 A4B4 A5
A0 A1 A2 A3 A4 A5
B0 B1 B2 B3 B4 B5
Decoded Data y0 y1 y2 y3 y4 y5
Fig. 1b, The “puncturing” and “depuncturing” procedure for coding rate R = 2/3.
Netlist Form
PUNC11A:NAME n1 n2 [CODING =val] [RIN=val] [ROUT=val]
Netlist Example
PUNC11A:1 1 2 CODING= 2
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-302
Scrambler, 802.11a (SCRM11A)

SCRM11A
MODULATION Modulation Type None 0 [0,3]/Integer
CODING Coding Rate Type None 0 [0,2]/Integer

octets)
S0 Initial state of the scrambler None 93 [0, 12]/Integer

in decimal
Ports
Input Bits before scrambling (integer)
Output Bits after scrambling (integer)
IEEE802dot11a10-303
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


1 ≤ Length ≤ 4095
0 ≤ S0 ≤ 27 − 1
Notes
1. This model can be used to scramble the DATA field and then let the tail bits be zero, according
to IEEE 802.11a standard.
2. The DATA field, composed of SERVICE, PSDU, tail, and pad parts, shall be scrambled with a
length-127 frame-synchronous scrambler. The frame synchronous scrambler uses the genera-
tor polynomia S(x)l as follows, and is illustrated in Fig.1.
S ( x ) = x 7 + x 4 + 1 (1)
The 127-bit sequence generated repeatedly by the scrambler shall be (leftmost used first),
00001110 11110010 11001001 00000010 00100110 00101110 10110110 00001100 11010100
11100111 10110100 00101010 11111010 01010001 10111000 1111111, when the “all ones”
initial state is used. The same scrambler is used to scramble transmit data and to descramble
receive data. When transmitting, the initial state of the scrambler will be set to a pseudo ran-
dom non-zero state Sd. The seven LSBs of the SERVICE field will be set to all zeros prior to
scrambling to enable estimation of the initial state of the scrambler in the receiver.
3. The 6 tail bits should be reset to “zero”. The position of the tail bits can be determined by the
three parameters, Modulation, Coding, and Length. The position of the first tail bit is deter-
mined by:
p0 = (16 + 8 × Length) mod N DATA (2)
For the calculation of NData, please refer to the pad11a model.
IEEE802dot11a10-304
Data In
x7 x6 x5 x 4 x 3 x 2 x1
Scrambled
Scrambed
Data Out
Fig.1 Data scrambler

Netlist Form
SCRM11A:NAME n1 n2 [MODULATION =val] [CODING =val]
Netlist Example
SCRM11A:1 1 2 MODULATION = 2 CODING= 2 LENGTH = 100 S0 = 93
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-305
Signal Field Bits Generator, 802.11a (SIG11A)

SIG11A
CODING Coding Rate Length None 0 [0, 2]/Integer

(number of octets)
Ports
Output Output signal (integer)
IEEE802dot11a10-306
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


Notes
1. This model can be used to generate the contents of the SIGNAL field, according to IEEE
802.11a standard.
2. The SIGNAL field contains the RATE and the LENGTH fields. The RATE field conveys
information about the type of modulation and the coding rate as used in the rest of the packet.
The encoding of the SIGNAL single OFDM symbol shall be performed with BPSK modula-
tion of the subcarriers and using convolutional coding at R = 1/2.
The contents of the SIGNAL field are not scrambled. The SIGNAL field shall be composed of
24 bits, as illustrated in Fig.1. The four bits 0 to 3 shall encode the RATE. Bit 4 shall be
reserved for future use. Bits 5~16 shall encode the LENGTH field, with the least significant bit
(LSB) being transmitted first.
3. Data rate (RATE): The bits R1~R4 shall be set, dependent on RATE, according to the values
in Table I. The data rate is determined by the two parameters, Modulation and Coding, as
shown in Table II.
4. PLCP length field (LENGTH): The PLCP length field shall be an unsigned 12-bit integer that
indicates the number of octets in the PSDU that the MAC is currently requesting the PHY to
transmit. This value is used to determine the number of octet transfers that will occur between
the MAC and the PHY after receiving a request to start transmission. The LSB shall be trans-
mitted first in time.
5. Parity (P), Reserved (R), and SIGNAL tail (SIGNAL TAIL): The Bit 4 shall be reserved for
future use. Bit 17 shall be a positive parity (even parity) bit for bits 0~16. The bits 18–23 con-
stitute the SIGNAL TAIL field, and all 6 bits shall be set to zero.
RATE LENGTH SIGNAL TAIL

(4 Bits) (12 Bits) (6 Bits)
R1 R2 R3 R4 R LSB MSB P "0" "0" "0" "0" "0" "0"
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Transmit Order
IEEE802dot11a10-307
Fig.1 SIGNAL field bit assignment

Table I Contents of IEEE 802.11a SIGNAL field
Rate (Mbits/s) R1~R4
6 1101
9 1111
12 0101
18 0111
24 1001
36 1011
48 0001
54 0011
Table II IEEE 802.11a Rate-dependent parameter

Data rate Coding rate subcarrier symbol symbol
Modulation
(Mbits/s) (R)
( N BPSC ) ( N CBPS ) ( N DBPS )
6 BPSK 1/2 1 48 24
9 BPSK 3/4 1 48 36
12 QPSK 1/2 2 96 48
18 QPSK 3/4 2 96 72
24 16-QAM 1/2 4 192 96
36 16-QAM 3/4 4 192 144
48 64-QAM 2/3 6 288 192
54 64-QAM 3/4 6 288 216
Netlist Form
SIG11A:NAME n1 n2 [MODULATION =val] [CODING =val]
Netlist Example
SIG11A:1 1 2 MODULATION = 2 CODING= 2 LENGTH = 100
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-308
Vitrebi Decoder, 802.11a (VDEC11A)

VDEC11A
PURPOSE Signal field {0} None 0 [0, 1]/Integer

DATA field {1}
CODING Coding Rate type None 0 [0, 2]/Integer

octets)
DECISION Hard decision {0}/ None 0 [0, 1]/Integer

Soft decision {1}
DEPTH Trellis depth of Viterbi None 100 [0, 1]/Integer

decoder
Ports
Input Signal before encoding (real)
Output Bits after decoding (integer)
IEEE802dot11a10-309
Limits
0 BPSK
1 QPSK

Modulation = 
2 16 - QAM
3 64 - QAM


Notes
1. This model can be used to decode the DATA field and SIGNAL field by using Viterbi algo-
rithm, according to IEEE 802.11a standard. For details, please refer to the COD11A model.
Netlist Form
VDEC11A:NAME n1 n2 [PURPOSE =val] [MODULATION =val]
+ [CODING =val] [LENGTH =val] [DEPTH =val] [RIN=val] [ROUT=val]
Netlist Example
VDEC11A:1 1 2 MODULATION = 2 CODING= 2 LENGTH = 100 DEPTH = 200
References
11:1999/Amd 1:2000(E).
IEEE802dot11a10-310
11
Math, Complex
Math, Complex11-313
Add Two Complex Signals (CADD)

CADD
Ports
Notes
1. This model Adds the two complex input signals (sample by sample) and writes the result to the
output port.
Netlist Form
CADD:NAME n1 n2 n3 [Rin1=val] [Rin2=val] [Rout=val]
Math, Complex11-314
Netlist Example
CADD:1 1 2 3
Math, Complex11-315
Scale a Complex Signal (CSCALE)
Scale a Complex Signal (CSCALE)

CSCALE
GAIN Magnitude of None 1 [0, Inf)/Real

complex gain
PHASE Phase of voltage Deg 0 [-180, 180)/Real

gain
Ports
Notes
This model takes a complex input signal and scales each input sample by the complex gain GAIN .
exp (j . PHASE). If the input signal is x(n), then the output signal y(n) is given by
y(n) = GAIN . exp (j . PHASE) . x(n)
Netlist Form
CSCALE:Name n1 n2 GAIN=val PHASE=val [Rin=val][Rout=val]
Netlist Example
CSCALE:1 1 2 GAIN=1.2 PHASE=10DEG
Math, Complex11-316
Subtract Two Complex Signals (CSUB)

CSUB
Ports
Notes
1. This model subtracts the two complex input signal (sample by sample) and writes the result to
the output port
Netlist Form
CSUB:NAME n1 n2 n3 [Rin1=val] [Rin2=val] [Rout=val]
Math, Complex11-317
Netlist Example
CSUB:1 1 2 3
Math, Complex11-318
Divide Two Signals (DIV)

DIV
Ports
Input1 Input1 signal, numerator (complex)
Input2 Input2 signal, denominator (complex)
Math, Complex11-319
Notes
1. This model performs a sample by sample division of two complex (or real) baseband signal.
Netlist Form
1. DIV:NAME n1 n2 n3 [RIN1=val] [RIN2=val] [ROUT=val]
Netlist Example
1. DIV:1 1 2 3
Math, Complex11-320
Angle (FANGLE)
Angle (FANGLE)
FANGLE
Ports
Notes
1. This is a math function. The output is the phase angle of the input complex signal.
Netlist Form
FANGLE:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FANGLE:1 1 2
Math, Complex11-321
Complex Conjugate (FCONJ)
Complex Conjugate (FCONJ)

FCONJ
Ports
Notes
1. This is a math function. The output is the complex conjugate value of the input complex signal.
Netlist Form
FCONJ:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FCONJ:1 1 2
Math, Complex11-322
Complex Magnitude (FMAG)
Complex Magnitude (FMAG)

FMAG
Ports
Notes
1. This is a math function. The output is the magnitude of the complex input signal.
Netlist Form
FMAG:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FMAG:1 1 2
Math, Complex11-323
Multiply Two Signals (MULT)

MULT
Ports
Notes
1. This model performs a sample by sample multiplication of two complex (or real) baseband sig-
Math, Complex11-324
nal.
Netlist Form
MULT:NAME n1 n2 n3 [RIN1=val] [RIN2=val] [ROUT=val]
Netlist Example
MULT:1 1 2 3
Math, Complex11-325
12
Math, Exponential
Math, Exponential12-326
Exponential Base e (FEXP)
Exponential Base e (FEXP)

FEXP
Ports
Notes
1. This is a math function. The output is the exponential (base e = 2.7182818) of the input signal.
Netlist Form
FEXP:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FEXP:1 1 2
Square (FSQR)
Square (FSQR)
FSQR
Ports
Notes
1. This is a math function. The output is the square of the input signal.
Netlist Form
FSQR:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FSQR:1 1 2
Square Root (FSQRT)
Square Root (FSQRT)

FSQRT
Ports
Notes
1. This is a math function. The output is the square root of the input signal.
Netlist Form
FSQRT:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FSQRT:1 1 2
Power (POW)
Power (POW)
POW
K Exponent None 2 (-Inf, Inf)/

Integer
Ports
Notes
1. This is a math function. The output is the power of the input signal. The relation of the output
Z and the input Xi s given by
z = xk
Netlist Form
POW:NAME n1 n2 [K=val] [RIN=val] [ROUT=val]
Netlist Example
POW:1 1 2 K=2
Power with Exponential Format (POW2)

POW2
M Numerator of None 1 (-Inf, Inf)/

exponent Integer
N Denominator of None 2 [2, Inf)/

exponent Integer
Ports
Notes
1. This is a math function. The output is the power of the input signal. The relation of the output
Z and the input X is given by
m
z= xn
Netlist Form
POW2:NAME n1 n2 [M=val] [N=val] [RIN=val] [ROUT=val]
Netlist Example
POW2:1 1 2 M=1 N=2
Root (ROOT)
Root (ROOT)
ROOT
K Root None 2 [2, Inf)/

Integer
Ports
Notes
1. This is a math function. The output is the root of the input signal. The relation of the output z
and the input x is given by
z=k x
Netlist Form:
ROOT:NAME n1 n2 [K=val] [RIN=val] [ROUT=val]
Netlist Example:
ROOT:1 1 2 K=2
13
Math, Logarithm
Math, Logarithm13-334
Natural Logrithm (FLN)
Natural Logrithm (FLN)

FLN
Ports
Notes
1. This is a math function. The output is the natural logarithm of the input signal.
Netlist Form
FLN:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FLN:1 1 2
Logarithm Base 10 (FLOG)
Logarithm Base 10 (FLOG)

FLOG
Ports
Notes
1. This is a math function. The output is the logarithm (base 10) of the input signal.
Netlist Form
FLOG:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FLOG:1 1 2
14
Math, Precision
Math, Precision14-337
Ceiling (CEIL)
Ceiling (CEIL)
CEIL
RIN Inpu1 impedance Ohm Inf (0, Inf]/Real
Ports
Notes:
1. This model rounds the input values to the nearest integers towards infinity.
Netlist Form:
CEIL:NAME n1 n2 [RIN=val] [ROUT=val]
Netlist Example:
CEIL:1 1 2
Floor (FLOOR)
Floor (FLOOR)
FLOOR
Ports
Note
1. This model rounds the input values to the nearest integers towards minus infinity.
Netlist Form
FLOOR:NAME n1 n2 [RIN=val] [ROUT=val]
Netlist Example
FLOOR:1 1 2
Fraction (FRACTION)
Fraction (FRACTION)
FRACTION
Ports
Notes
1. This model is used to output the fractional part of the input values.
Netlist Form
FRACTION:NAME n1 n2 [RIN=val] [ROUT=val]
Netlist Example
FRACTION:1 1 2
Round (ROUND)
Round (ROUND)
ROUND
Ports
Notes
1. This model rounds the input values to the nearest integers.
Netlist Form
ROUND:NAME n1 n2 [RIN=val] [ROUT=val]
Netlist Example
ROUND:1 1 2
Truncation (TRUNC)
Truncation (TRUNC)
TRUNC
Ports
Notes
1. This model rounds the input values to the nearest integers towards zero.
Netlist Form:
TRUNC:NAME n1 n2 [RIN=val] [ROUT=val]
Netlist Example:
TRUNC:1 1 2
15
Math, Real
Math, Real15-343
Compare Two Real Input Signals (CINT)

CINT
Ports
Notes
1. This model compares two input signals. If the nth sample of both signals is different, the model
outputs a 1, otherwise, it outputs a 0. This model could be used as an error counter.
Netlist Form
CINT:NAME n1 n2 n3 [Rin1=val] [Rin2=val] [Rout=val]
Math, Real15-344
Netlist Example
CINT:1 1 2 3
Math, Real15-345
Absolute Value (FABS)
Absolute Value (FABS)

FABS
Ports
Model Notes
1. This is a math function. The output is the absolute value of the input signal.
Netlist Form
FABS:NAME n1 n2 [Rin1=val] [Rout=val]
Netlist Example
FABS:1 1 2
Math, Real15-346
Add Two Real Input Signals (RADD)
Add Two Real Input Signals (RADD)

RADD
Ports
Notes
1. This model performs a sample by sample addition of two real input signals.
Netlist Form
RADD:NAME n1 n2 n3 [Rin1=val] [Rin2=val] [Rout=val]
Netlist Example
RAD:1 1 2 3
Math, Real15-347
Reciprocator (RECIP)
Reciprocator (RECIP)
RECIP
Ports
Notes
1. This is a math function. The output is the reciprocal of the input signal. The relation of the out-
put Z and the input X is given by
1
z=
x
Netlist Form:
RECIP:NAME n1 n2 [RIN=val] [ROUT=val]
Netlist Example:
RECIP:1 1 2
Math, Real15-348
Scale a Real Signal (RSCALE)
Scale a Real Signal (RSCALE)

RSCALE
GAIN Gain factor None 1 (-Inf, Inf)/Real
Ports
Notes
This model takes a real input signal and scales each input sample by GAIN. If the input signal is
x(n), then the output signal y(n) is given by: y(n) = GAIN .x(n), where n ≥ 0.
Netlist Form
RSCALE:Name n1 n2 GAIN=val [Rin=val][Rout=val]
Netlist Example
RSCALE:1 1 2 GAIN=0.01
Math, Real15-349
Subtract Two Real Input Signals (RSUB)
Subtract Two Real Input Signals (RSUB)

RSUB
Ports
Input1 Input1 signal (real)1
Notes
1. This model performs a sample by sample subtraction of two real input signals. Input2 which
corresponds to node n2 is subtracted from Input1 which corresponds to node n1.
Netlist Form
RSUB:NAME n1 n2 n3 [Rin1=val] [Rin2=val] [Rout=val]
Netlist Example
RSUB:1 1 2 3
Math, Real15-350
16
Math, Transforms
Math, Transforms16-351
Fast Fourier Transform (FFT)
Fast Fourier Transform (FFT)

FFT
FFTL FFT length None 1024 [1, Inf)/Integer
Ports
Notes
1. This model performs FFT on the incoming signal. If “FFTL” is not a power of 2, it will be set
to the integer next power of 2 value greater than FFTL.
Netlist Form
FFT:NAME n1 n2 fftl=val [Rin=val] [Rout=val]
Netlist Example
FFT:1 1 2 fftl = 2048
Inverse Fast Fourier Transform (IFFT)
Inverse Fast Fourier Transform (IFFT)

IFFT
FFTL FFT length None 1024 [1, Inf)/Integer
Ports
Notes
1. This model performs inverse FFT on the incoming signal. If “FFTL” is not a power of 2, it will
be set to the integer next power of 2 value greater than FFTL.
Netlist Form
IFFT:NAME n1 n2 fftl=val [Rin=val] [Rout=val]
Netlist Example
IFFT:1 1 2 fftl = 2048
17
Math, Trigonometry
Math, Trigonometry17-354
Arc Cosine (FACOS)
Arc Cosine (FACOS)

FACOS
Ports
Notes
1. This is a math function. The output is the arc cosine of the input signal.
Netlist Form
FACOS:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FACOS:1 2
Arc Sine (FASIN)
Arc Sine (FASIN)

FASIN
Ports
Notes
1. This is a math function. The output is the arc sine of the input signal.
Netlist Form
FASIN:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FASIN:1 1 2
Arc Tangent (FATAN)
Arc Tangent (FATAN)

FATAN
Ports
Notes
1. This is a math function. The output is the arc tangent of the input signal.
Netlist Form
FATAN:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FATAN:1 1 2
Cosine (FCOS)
Cosine (FCOS)
FCOS
Ports
Notes
1. This is a math function. The output is the cosine of the input signal.
Netlist Form
FCOS:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FCOS:1 1 2
Hyperbolic Cosine (FCOSH)
Hyperbolic Cosine (FCOSH)

FCOSH
Ports
Notes
1. This is a math function. The output is the hyperbolic cosine of the input signal.
Netlist Form
FCOSH:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FCOSH:1 1 2
Sine (FSIN)
Sine (FSIN)
FSIN
Ports
Notes
1. This is a math function. The output is the sine of the input signal.
Netlist Form
FSIN:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FSIN:1 1 2
Hyperbolic Sine (FSINH)
Hyperbolic Sine (FSINH)

FSINH
Ports
Notes
1. This is a math function. The output is the hyperbolic sine of the input signal.
Netlist Form
FSINH:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FSINH:1 1 2
Tangent (FTAN)
Tangent (FTAN)
FTAN
Ports
Notes
1. This is a math function. The output is the tangent of the input signal.
Netlist Form
FTAN:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FTAN:1 1 2
Hyperbolic Tangent (FTANH)
Hyperbolic Tangent (FTANH)

FTANH
Ports
Notes
1. This is a math function. The output is the hyperbolic tangent of the input signal.
Netlist Form
FTANH:NAME n1 n2 [Rin=val] [Rout=val]
Netlist Example
FTANH:1 1 2
18
Miscellaneous
Miscellaneous18-364
Delay, Complex Signal (CDELAY)

CDELAY
D The number of None 1 [0, Inf)/Integer

samples by which
the input signal is
delayed.
REAL_V Real part of the Volt 0 (-Inf, Inf)/Real

value of the first D
output samples
IMAG_V Imaginary part of Volt 0 (-Inf, Inf)/Real

the value of the
first D output
samples
Ports
Miscellaneous18-365
Notes
This model delays a complex signal by a specified number of samples given by the parameter D.
This delay will effectively place D number of samples at the beginning of the output signal with the
value RealV + jImagV .
Netlist Form
CDELAY:Name n1 n2 D=val [REAL_V=val] [IMAG_V=val] [Rin=val]
[Rout=val]
Netlist Example
CDELAY:1 1 2 D=8 REAL_V=1
Miscellaneous18-366
Demultiplexer, Complex (CDMUX)

CDMUX
Type Output sample rate None 0 [0, 1]/Integer

changed: 0 for No,
1 for Yes
NS1 Number of samples None 1 [1, Inf)/Integer

to write to output1

to write to output2
Ports
Miscellaneous18-367
Notes
This model demultiplexes one complex input signal into two complex output signals. It works as
follows: the first output reads NS1 samples from the input signal, then the second output reads NS2
samples from the incoming signal, then the first output reads again, repeating the pattern until there
are no more data to be read. Based on whether the parameter “type” is set or not, the sampling rate
of the two output signals can change or remain the same. Suppose the sampling rate of the input
signal is f s ( in ) , if TYPE is set to be 1, then the sampling rate for the two outputs would be
NS1 - and f ( out2 ) = f ( in ) × ---------------------------
f ( out1 ) = f ( in ) × --------------------------- NS2 - respectively.
s sNS1 + NS2 s
NS1 + NS2 s
Netlist Form
CDMUX:Name n1 n2 n3 [TYPE=val] NS1=val NS2=val [Rin=val]
[Rout1=val] [Rout2=val]
Netlist Example
CDMUX:Name 1 2 3 NS1=20 NS2=30
Miscellaneous18-368
Demultiplexer with Four Outputs, Complex
Demultiplexer with Four Outputs, Complex (CDMUX4)

CDMUX4
TYPE Output sample rate None 0 [0, 1]/Integer

changed: 0 for No,
1 for Yes
N Number of output None 4 [1, 4]/Integer

ports used for
demultiplexing

to write to output1

to write to output2

to write to output3
Miscellaneous18-369

to write to output4
ROUT1 Output1 impedance Ohm Inf [0, Inf)/Real
Ports
Notes
This model is used to demultiplex one complex input signal into N (1≤ N ≤ 4) complex output signals.
Note that only N ports are used to do the demultiplexing, the remaining output ports will receive no
data.If TYPE is set to 0, then the sampling rate of the output signals will not change. Otherwise, the
NSi
sampling rate of the ith output port can be calculated as fs ( outi ) = fs ( in ) × --------------------------------------------------------
NS1 + NS2 + … + N S · -
4
Netlist Form
CDMUX4:Name n1 n2 n3 n4 n5 [TYPE= val] N= val [NS1= val] [NS2= val] [NS3=
val] [NS4= val] [Rin=val][Rout1=val] [Rout2=val] [Rout3=val] Rout4=val]
Netlist Example
CDMUX4:1 1 2 3 4 5 N=3 TYPE=0 NS1=1 NS2=1 NS3=1 NS4=0
In this example, 1 sample is read from the input signal to Output1 followed by 1 sample to
Output2, followed by 1 sample toOutput3 and followed by 1 sample to Output1 and so on
Miscellaneous18-370
until no sample exists at the input port. Each output sample rate equals one third the input sam-
ple rate.
Miscellaneous18-371
Demultiplexer with Eight Outputs, Complex
Demultiplexer with Eight Outputs, Complex (CDMUX8)

CDMUX8

changed: 0 for No,
1 for Yes
N Number of output None 8 [1, 8]/Integer

ports used for
demultiplexing
Miscellaneous18-372

to write to output1

to write to output2

to write to output3

to write to output4

to write to output5

to write to output6

to write to output7

to write to output8
Ports
Miscellaneous18-373
Notes
This model is used to demultiplex one complex input signal into N (1≤ N ≤ 8) complex output sig-
nals. Note that only N ports are used to do the demultiplexing, the remaining output ports will
receive no data.If TYPE is set to 0, then the sampling rate of the output signals will not change.
Otherwise, the sampling rate of the ith output port can be calculated as
NSi
f ( outi ) = f ( in ) × ---------------------------------------------------------
s s NS1 + NS2 + … + NS8
Netlist Form
CDMUX8:Name n1 n2 n3 n4 n5 n6 n7 n8 n9 [TYPE=val] N=val
[NS1=val] [NS2=val] [NS3=val] [NS4=val] [NS5=val] [NS6=val]
[NS7=val] [NS8=val] [Rin=val][Rout1=val] [Rout2=val]
[Rout3=val] [Rout4=val] [Rout5=val] [Rout6=val] [Rout7=val]
[Rout8=val]
NetlistExample
CDMUX8:1 1 2 3 4 5 6 7 8 9 TYPE=0 N=5 NS1=1 NS2=1 NS3=1 NS4=0
NS5=1 NS6=0 NS7=0 NS8=0
In this example, 1 samples is read from the input signal to Output1 followed by 1 sample to
Output2, … followed by 1 sample to Output5 and followed by 1 sample to Output1 and so
on until no sample exists at the input port. Each output sample rate equals one fifth the input
sample rate.
Miscellaneous18-374
Multiplexer, Complex (CMUX)

CMUX
Type Output sample rate changed: None 0 [0, 1]/Integer

0 for No, 1 for Yes
NS1 Number of samples to read None 1 [1, Inf)/Integer

from input1

from input2
Ports
Output Multiplexed output signal (complex)
Miscellaneous18-375
Notes
This model multiplexes two complex input signals with the same sampling rate into a single com-
plex output signal. The output signal takes NS1 samples from the first input, and then NS2 samples
from the second input, and then NS1 samples from the first input again, continuing until no data
remains for processing. If TYPE is set to 0, then the sampling rate of the output signals will not
change. Otherwise, the sampling rate of the ith output port can be calculated as
f ( out ) = f ( in ) × NS1 + NS2-
---------------------------
s s NS1
Netlist Form
CMUX:Name n1 n2 n3 [TYPE=val] [NS1=val] [NS2=val]
[Rin1=val] [Rin2=val] [Rout=val]
Netlist Example
CMUX:1 1 2 3 INPUT1=45 INPUT2=100
In this example, the multiplexed complex output signal will consist of 45 samples from Input1
followed by 100 samples from Input2 followed by 45 samples from Input1, continuing until
no more input samples remain at one or both input nodes.
Miscellaneous18-376
Multiplexer with Four Inputs, Complex (CMUX4)

CMUX4

changed: 0 for No,
1 for Yes
N Number of input None 4 [1, 4]/Integer

ports used for
multiplexing

to read from input1

to read from input2

to read from input3
Miscellaneous18-377

to read from input4
RIN1 Input1 Impedance Ohm Inf (0, Inf]/Real
Ports
Notes
This model is used to multiplex N (1≤ N ≤ 4) complex input signals with the same sampling rate
into a single complex output signal. Note that if only N input ports are used to do the multiplexing,
the remaining ports are not used. If TYPE is set to 0, then the sampling rate of the output signals
will not change. Otherwise,
NS1 + NS2 + …NS4
the sampling rate of the output port can be calculated as f ( out ) = f × ----------------------------------------------------
s s NS1
Netlist Form
CMUX4:Name n1 n2 n3 n4 n5 [TYPE=val] [N=val] [NS1=val]
[NS2=val] [NS3=val] [NS4=val] [Rin1=val][Rin2=val]
[Rin3=val] [Rin4=val] [Rout=val]
Netlist Example
CMUX4:1 1 2 3 4 5 N=3 TYPE=0 NS1=1 NS2=1 NS3=1
Miscellaneous18-378
In this example, the multiplexed complex output signal will consist of 1 sample from Input1
followed by 1 sample from Input2, …, followed by 1 sample from input3 and followed by 1
sample from Input1 and so on until no input sample exists at the input ports being processed.
The output sample rate equals three times the first input sample rate.
Miscellaneous18-379
Multiplexer with Eight Inputs, Complex (CMUX8)

CMUX8

changed: 0 for No,
1 for Yes
N Number of input None 8 [1, 8]/Integer

ports used for
multiplexing
NS1 Number of None 1 [1, Inf)/Integer

samples to read
from input1

samples to read
from input2
Miscellaneous18-380

samples to read
from input3

samples to read
from input4

samples to read
from input5

samples to read
from input6

samples to read
from input7

samples to read
from input8
RIN5 Input 5 Impedance Ohm Inf (0, Inf]/Real
Ports
Miscellaneous18-381
Notes
This model is used to multiplex N (1≤ N ≤ 8) complex input signals with same sampling rate into a
single complex output signal. Note that if only N input ports are used to do the multiplexing, the
remaining ports are not used. If TYPE is set to 0, then the sampling rate of the output signals will
not change. Otherwise,
the sampling rate of the output port can be calculated as f ( out ) = f × NS1 + NS2 + …NS8-
---------------------------------------------------
s s NS1
Netlist Form
CMUX8:Name n1 n2 n3 n4 n5 n6 n7 n8 n9 [TYPE=val] [N=val]
[NS1=val] [NS2=val] [NS3=val] [NS4=val] [NS5=val] [NS6=val]
[NS7=val] [NS8=val] [Rin1=val][Rin2=val] [Rin3=val] [Rin4=val]
[Rin5=val] [Rin6=val] [Rin7=val] [Rin8=val] [Rout=val]
NetlistExample
CMUX8:1 1 2 3 4 5 6 7 8 9 TYPE=0 N=5 NS1=1 NS2=1 NS3=1 NS4=0
NS5=1 NS6=0 NS7=0 NS8=0
In this example, the multiplexed complex output signal will consist of 1 sample from input1
followed by 1 sample from Input2, followed by 1 sample from Input5 and followed by 1 sam-
ple from Input1 and so on until no input sample exists at the input node which is being pro-
cessed. The output sample rate equals five times the first input sample rate.
Miscellaneous18-382
Convolution of Two Real Input Signals (CONV)

CONV

from the first input per
invocation

from the second input
per invocation
Ports
Notes
This model convolves two real input signals. The convolution is performed in the frequency
domain according to the overlap-save technique [1].
Miscellaneous18-383
If the number of samples is INPUT1_NSAMP at the first input port and INPUT2_NSAMP at the
second input port, then the total number of samples at the output port (per invocation) will be
INPUT1_NSAMP + INPUT2_NSAMP - 1. Keep in mind that the convolution process is commu-
tative, which implies that switching the input ports around should not alter the outcome at the out-
put port.
Netlist Form
CONV:Name n1 n2 n3 [NS1=val] [NS2=val] [Rin1=val][Rin2=val]
[Rout=val]
Netlist Example
CONV:1 1 2 3 NS1=300 NS2=400
References
Miscellaneous18-384
Real Signal Correlator (CRLTR)

CRLTR
COR_LEN Correlation length None 1 [1, Inf)/Integer
Ports
Notes
This model accepts COR_LEN samples each from the two inputs per invocation and generates
2*COR_LEN-1 samples to the output. For a given two input sequences, x1(n) and x2(n) , the output
signal y(n) is calculated as:
Miscellaneous18-385
CorLen – 1
y(n) = ∑ x1 ( m ) x2 ( n – m )
m=0
with n in the range of [0, 2*CorLen-1]. Note x1(n) and x2(n) are zero when n is out of the range of
[0, CorLen-1] in the above equation.
Netlist Form
CRLTR:Name n1 n2 n3 COR_LEN=val [Rin1=val] [Rin2=val]
[Rout=val]
Netlist Example
CRLTR:1 1 2 3 COR_LEN=100
Miscellaneous18-386
Toggle Complex Input Signals (CTOGGLE)

CTOGGLE
NS The number of None 0 [0, Inf)/Integer

samples to output
from Input1 before
switching to
Input2.
Ports
Notes
This model switches from Input1 to Input2 after a specified number of samples given by the
parameter NS. In other words, the output will simply be a replica of Input1 for the duration of the
first NS samples after which it outputs samples from the second input signal.
Miscellaneous18-387
Netlist Form
CTOGGLE:Name n1 n2 n3 NS=val [Rin1=val] [Rin2=val] [Rout=val]
Netlist Example
CTOGGLE:1 1 2 3 NS=8
Miscellaneous18-388
Deinterleaver (DEILV)
DEILV
BLOCK_SIZE Number of input None 64 [1, Inf)/Integer

samples to
window per
invocation
RANDOM_SEED Random seed None 0 [-1, Inf)
FILE Data file used to None Optional String

generate
interleaving
function

impedance
Ports
Output Deinterleaved input signal (real)
Notes
1. This model deinterleaves a real signal using given interleave functions, which may be provided
by an external data file or created from computer by pseudo-random generator. During each
Miscellaneous18-389
invocation, this model deinterleaves BLOCK_SIZE input samples

2. The interleave function is just a sequence of BLOCK_SIZE integers:
f(i) = ai (i= 1, … ,BLOCK_SIZE)
The output signal values related to input signal values for every BLOCK_SIZE samples are:
Output( f(i) ) = input (i) (i= 1, … ,BLOCK_SIZE)
3. The parameters RANDOM_SEED and FILE are optional. If neither is provided, the program
uses the default value of RANDOM_SEED, which is 0.
4. For any non-negative values of RANDOM_SEED, the program sets up a random seed from
its internal random generator = RANDOM_SEED and generates the interleaving function ran-
domly.
5. An external file will be used to generate interleaving function for either of the following cases:
RANDOM_SEED = -1, or FILENAME has been provided.
Data format for the external file is text file. The contents of the file are just BLOCK_SIZE
integers, which are used as interleave function.
6. This element will recover the interleaved signal if the RANDOM_SEED are the same (or use
same external file) for INTLV and DEILV.
Netlist Form
DEILV:Name n1 n2 BLOCK_SIZE=val [RANDOM_SEED=val]
FILE=”filename” [Rin=val] [Rout=val]
Netlist Example
1. Random deinterleaver:
DEILV:1 1 2 BLOCK_SIZE=256 RANDOM_SEED=40435
2. Interleave function provided by external file:
DEILV:1 3 2 BLOCK_SIZE=960 RANDOM_SEED=-1 FILE=”filename”
END
Miscellaneous18-390
Interleaver (INTLV)
Interleaver (INTLV)
INTLV
BLOCK_SIZE Number of input None 64 [1, Inf)/Integer

samples to
window per
invocation
RANDOM_SEED Random seed None 0 [-1, Inf)/Integer
FILE Data file used to None Optional String

generate
interleaving
function

impedance
Ports
Output Interleaved input signal (real)
Notes
1. This model interleaves a real signal using given interleave functions, which may be provided
by an external data file or created from computer by pseudo-random generator. During each
Miscellaneous18-391
Interleaver (INTLV)
invocation, this model deinterleaves BLOCK_SIZE input samples

2. The interleave function is just a sequence of BLOCK_SIZE integers:
f(i) = ai (i= 1, … ,BLOCK_SIZE)
The output signal values related to input signal values for every BLOCK_SIZE samples are:
Output( f(i) ) = input (i) (i= 1, … ,BLOCK_SIZE)
3. The parameters RANDOM_SEED and FILE are optional. If neither is provided, the program
uses the default value of RANDOM_SEED, which is 0.
4. For any non-negative values of RANDOM_SEED, the program sets up a random seed from
its internal random generator = RANDOM_SEED and generates the interleaving function ran-
domly.
5. An external file will be used to generate interleaving function for either of the following cases:
RANDOM_SEED = -1, or FILENAME has been provided.
Data format for the external file is MatLab format with extension .mat. The contents of the file
are just BLOCK_SIZE integers, which are used as interleave function.
6. This element will recover the interleaved signal if the RANDOM_SEED are the same (or use
same external file) for INTLV and DEILV.
Netlist Form
INTLV:Name n1 n2 BLOCK_SIZE=val [RANDOM_SEED=val]
FILE=”filename” [Rin=val] [Rout=val]
Netlist Example
1. Random interleaver:
INTLV:1 1 2 BLOCK_SIZE=256 RANDOM_SEED=40435
2. Interleave function provided by external file:
INTLV:1 3 2 BLOCK_SIZE=960 RANDOM_SEED=-1
Miscellaneous18-392
Limiter (LIMITER)
Limiter (LIMITER)
LIMITER
VN Negative output saturation voltage Volt -1 (-Inf, 0]/Real
VP Positive output saturation voltage Volt 1 [0, Inf)/Real
GAIN Small signal voltage gain None 109 (-Inf, Inf)/

Real
Ports
Notes
1. This model performs amplitude limitation. If the input to this model is a baseband signal vin(t),
the output is a baseband signal. The output quadrature-phase is 0, and in-phase signal is given
as follows
Vout,i(t) = GAIN . Vin(t),for VN ≤ GAIN . Vin,i(t) ≤ VP
Vout,i(t) = VN, for GAIN . Vin,i(t) < VN
Vout,i(t) = VP, for GAIN . Vin,i(t) > VP
Vout,q(t) = 0
If the input to this model is a bandpass signal with the in-phase and quad-phase envelopes
Miscellaneous18-393
Limiter (LIMITER)
Vin,i(t) and Vin,q(t), the output is bandpass signal and has the same carrier frequency as the
input. The output in-phase and quad-phase envelopes are given as follows, respectively
Vout,i(t) = GAIN . Vin,i(t) and Vout,q(t) = GAIN . Vin,q(t) for GAIN . V(t) < VP
Vout,i(t) = [VP/V(t)] . Vin,i(t) and Vout,q(t) = [VP/V(t)] • Vin, q(t) for GAIN . V(t) ≥ VP
where V(t) = SQRT(Vin,i(t)2 +Vin,q(t)2)

Netlist Form
LIMITER:Name n1 n2 VN=val VP=val [GAIN=val] [Rin=val]
[Rout=val]
Netlist Example
LIMITER:1 1 2 VN=-2V VP=2V GAIN=3
Miscellaneous18-394
Rate Changer (RATECHANGER)
Rate Changer (RATECHANGER)

RATECHANGER
SAMPLE_RATE Output sampling rate Hz 1000 (0, Inf)/Real
Ports
Netlist Form
RATECHANGER:Name n1 n2 SAMPLE_RATE=val, [Rin=val] [Rout=val]
Netlist Example
RATECHANGER:1 1 2 SAMPLE_RATE=15KHZ
Notes
This model changes the sampling rate of an input signal to the sampling rate specified by the user.
Miscellaneous18-395
Delay, Real Signal (RDELAY)
Delay, Real Signal (RDELAY)

RDELAY
D The number of samples by which the None 1 [0, Inf)/

input signal is delayed Integer
V The value of the first D samples at the Volt 0.0 (-Inf, Inf)/
output Real
Ports
Output Delayed input signal (real)
Notes
This model delays a real signal by a specified number of samples given by the parameter D. This
delay will effectively place D samples of V at the beginning of the output signal.
Netlist Form
RDELAY:Name n1 n2 D=val [Rin=val] [Rout=val]
Netlist Example
RDELAY:1 1 2 D=8
Miscellaneous18-396
Demultiplexer, Real (RDMUX)

RDMUX

changed: 1 for Yes,
0 for No

to write to output1
per cycle

to write to output2
per cycle
Ports
Miscellaneous18-397
Output1 The first demultiplexed output signal (real)
Output2 The second demultiplexed output signal (real)
Notes
This model demultiplexes one real input signal into two real output signals. It works as follows: the
first output reads NS1 samples from the input signal, then the second output reads NS2 samples
from the incoming signal, then the first output reads again, and so on until there are no more data to
be read. Based on whether the parameter “type” is set or not, the sampling rate of the two output
signals can change or remain the same. Suppose the sampling rate of the input signal is f s ( in ) , if
NS1 -
TYPE is set to be 1, then the sampling rate for the two outputs would be fs ( out1 ) = fs ( in ) × ---------------------------
NS2 NS1 + NS2
and fs ( out2 ) = fs ( in ) × ---------------------------- respectively.
NS1 + NS2
Netlist Form
RDMUX:Name n1 n2 n3 NS1=val NS2=val [TYPE=val] [Rin=val]
[Rout1=val][Rout2=val]
Netlist Example
RDMUX:1 1 2 3 NS1=20 NS2=30
In this example, 20 samples are read from the input signal to Output1 at n = 2 followed by 30 sam-
ples to Output2 at n = 3 followed by 20 samples to Output1 and so on until no more samples exist
at the input port.
Miscellaneous18-398
Rectifier (RECTFR)
Rectifier (RECTFR)
RECTFR
Range/
Type
Ports
Notes
The output of this rectifier is: V2 (t) = V1 (t)
Netlist Form
RECTFR:Name n1 n2 [Rin=val] [Rout=val]
Netlist Example
RECTFR:1 1 2
Miscellaneous18-399
Multiplexer, Real (RMUX)

RMUX
TYPE Output sampling rate None 0 [0, 1]/Integer

changed: 1 for Yes, 0 for No

from input1 per cycle

from input2 per cycle
Ports
Output Multiplexed output signal (real)
Miscellaneous18-400
Notes
This model multiplexes two real input signals with the same sampling rate into a single real output
signal. The output signal takes NS1 samples from the first input, and then NS2 samples from the
second input, and then NS1 samples from the first input again, and so on until no data is available
for processing. If TYPE is set to 0, then the sampling rate of the output signals will not change.
Otherwise, the sampling rate of the ith output port can be calculated as fs ( out ) = fs ( in ) × NS1 + NS2
----------------------------
NS1
Netlist Form
RMUX:Name n1 n2 n3 NS1=val NS2=val [TYPE=val] [Rin1=val]
Netlist Example
RMUX:1 1 2 3 NS1=45 NS2=100
In this example, the multiplexed real output signal will consist of 45 samples from Input1 followed
by 100 samples from Input2 followed by 45 samples from Input1 and so on until no more input
samples exist at one or both input nodes
Miscellaneous18-401
Toggle Real Input Signals (RTOGGLE)

RTOGGLE
NS The number of None 0 [0, Inf)/Integer

samples to output
from Input1 before
switching to
Input2.
Ports
Notes
This model switches from Input1 to Input2 after a specified number of samples given by the
parameter NS. In other words, the output will simply be a replica of Input1 for the duration of the
first NS samples after which it outputs samples from the second input signal.
Miscellaneous18-402
Netlist Form
RTOGGLE:Name n1 n2 n3 NS=val [Rin=val][Rout=val]
Netlist Example
RTOGGLE:1 1 2 3 NS=8
Miscellaneous18-403
Symbol Repeater (SAMPREP)
Symbol Repeater (SAMPREP)

SAMPREP
NOR Number of repetitions None 1 [1, Inf)/Integer

per input symbol
Ports
Input Input signal (Real)
Output Output signal (Real)
Notes
This model repeats every input symbol NOR times. The sampling rate of the output is NOR times
the sampling rate of the input.
Netlist Form
SAMPREP:Name n1 n2 NOR=val [Rin=val][Rout=val]
Netlist Example
SAMPREP:1 1 2 NOR=6
Miscellaneous18-404
Schmitt Trigger Nonlinear (SCHMIT)

SCHMIT
VIL Lower input trigger Volt 0 (-Inf, Inf)/Real

voltage
VIH Higher input Volt 0 (-Inf, Inf)/Real

trigger voltage
VOL Lower output Volt 0 (-Inf, Inf)/Real

voltage
VOH Higher output Volt 0 (-Inf, Inf)/Real

voltage
Ports
Limits
VIL <= VIH
VOL <= VOH
Miscellaneous18-405
Notes
1. This element is a Schmitt trigger with programmable levels. The output of this element is
always a baseband signal.
2. The input voltage must actually cross the threshold before the output voltage changes. For
example, a trigger VIL=0 and VIH=2, whose output is currently the ‘low’ value, will not
change its output on the input sequence, 1.7V, 1.8V, 1.9V, 2.0V, 1.9V, etc.
3. The initial value of the output is VOH if the initial input is greater than VIH. The initial value
of the output is VOL otherwise.
4. Example: Input and output waveforms are shown for a Schmitt trigger with the following
parameters: VIL = 2, VIH = 5.6, VOL = 0, and VOH = 2.5.
Netlist Form
SCHMIT:Name n1 n2 VIL=val VIH=val VOL=val VOH=val
[Rin=val][Rout=val]
Netlist Example
SCHMIT:1 1 2 VIL=13.5mv VIH=15mv VOL=0 VOH=1
Miscellaneous18-406
Signal Sink (SINK)
Signal Sink (SINK)

SINK
Range/
Type
Ports
Input Input signal (Real, Complex)
Notes
1. This model is used to terminate any output signal (i.e., no further processing takes place after
this component). This model is normally used to terminate all open nodes in a DSP system.
Netlist Form
SINK:Name n1 [Rin=val]
Netlist Example
SINK:1 1
Miscellaneous18-407
Sample and Hold (SMPLHLD)

SMPLHLD
DECAY_RATE Output voltage decay V/Sec 0 [0, Inf)/Real

rate, in 1/second unit
Ports
Notes
1. The input signal is sampled at each rising edge of the clock signal (the input is sampled at the
instant when the clock signal crosses a threshold of 0.5V). In the hold state of the sample and
hold the output voltage decays at a constant rate determined by the parameter
DECAY_RATE.
2. The output signal is always a baseband signal.
3. The input signal and output signal voltages of the SMPLHLD element, with its CLK pin tied to
Miscellaneous18-408
a clock source with period 10 msec and DECAY_RATE = 0, are shown in the figure below.
Netlist Form
SMPLHLD:Name n1 n2 n3 DECAY_RATE=val [Rin1=val] [Rin2=val]
[Rout=val]
Netlist Example
SMPLHLD:1 1 2 3 DECAY_RATE=0
Miscellaneous18-409
Sampling Rate Downsampler for Complex Signal
Sampling Rate Downsampler for Complex Signal (SRDC)

SRDC
DF Factor by which the None 8 [1, Inf)/Integer

input signal is
downsampled
Ports
Notes
This model downsamples a complex input signal. It outputs the first sample for each block of DF
input samples. This model can be used for ideal sampling..
Netlist Form
SRDC:Name n1 n2 DF=val [Rin=val][Rout=val]
Netlist Example
SRDC:1 1 2 DF=16
Miscellaneous18-410
Sampling Rate Downsampler for Real Signal (SRDR)
Sampling Rate Downsampler for Real Signal (SRDR)

SRDR
DF The factor by None 8 [1, Inf)/Integer

which the input
signal is
downsampled
Ports
Notes
This model downsamples a real input signal. It outputs the first sample for each block of DF input
samples. This model can be used for ideal sampling.
Netlist Form
SRDR:Name n1 n2 DF=val [Rin=val][Rout=val]
Netlist Example
SRDR:1 1 2 DF=16
Miscellaneous18-411
Sampling Rate Upsampler for Complex Signal
Sampling Rate Upsampler for Complex Signal (SREC)

SREC
EF Factor by which the None 8 [1, Inf)/Integer

input signal is
upsampled
Ports
Notes
1. This model expands the sampling rate of the complex input signal. Beginning with the first
input sample, each input sample followed by EF - 1 zeros are written to the output port.
Netlist Form
SREC:Name n1 n2 EF=val [Rin=val][Rout=val]
Netlist Example
SREC:1 1 2 EF=16
Miscellaneous18-412
Sampling Rate Upsampler for Real Signal (SRER)
Sampling Rate Upsampler for Real Signal (SRER)

SRER
EF The factor by None 1 [1, Inf)/Integer

which the input
signal is upsampled
Ports
Notes
This model expands the sampling rate of the real input signal. Beginning with the first input sam-
ple, each input sample followed by EF - 1 zeros are written to the output port.
Netlist Form
SRER:Name n1 n2 EF=val [Rin=val] [Rout=val]
Netlist Example
SRER:1 1 2 EF=16
Miscellaneous18-413
Voltage Controlled Switch: Type 1 (SWITCH1)

SWITCH1
VTHRESHOLD Control voltage Volt 0.5 (-1e+020, 1e20)/

threshold Real
Ports
Notes
1. This model performs voltage-controlled switching. The control voltage is the voltage at the
second input port represented by _V2:
_V2 = V2I . cos(2πf2c t) - V2Q. sin (2πf2c t),
where, V2I + jV2Q is the voltage complex envelope at the second input port, and f2c is its carrier
frequency. The output carrier frequency equals to the carrier frequency of the first input signal.
Miscellaneous18-414
The voltage complex envelope (V3I + jV3Q) at the output port is determined by
V31 + jV3Q = V1I + jV1Q for V2 > VTHRESHOLD, and

V31 + jV3Q = 0 elsewhere,
where V1I + jV1Q is the voltage complex envelope at the first input port.
Netlist Form
SWITCH1:Name n1 n2 n3 [VTHRESHOLD=val] [Rin1=val][Rin2=val]
[Rout=Val]
Netlist Example
SWITCH1:1 1 2 3 VTHRESHOLD=1V
Miscellaneous18-415

SWITCH2

threshold Real
Ports
Input1 First input signal (complex)
Input2 Second input signal, control signal (complex)
Output1 First output signal (complex)
Output2 Second output signal (complex)
Notes
This model performs voltage-controlled switching. The control voltage is represented by _V2:
Miscellaneous18-416
_V2 = V2I . cos (2πf2c t) - V2Q. sin (2πf2c t)
where , V2I + jV2Q is the voltage complex envelope at the second input port, and f2c is its carrier
frequency. The carrier frequency at output ports equals to the carrier of the first input port. The
voltage complex envelopes (V3I + jV3Q) and (V4I + jV4Q) at the first and second output ports are
determined by
V31 + jV3Q = V1I + jV1Q and V41 + jV4Q = 0 for V2 > VTHRESHOLD,
V41 + jV4Q = V11 + jV1Q and V31 + jV3Q = 0 elsewhere,
where V1I + jV1Q is the voltage complex envelope at the first input port.
Netlist Form
SWITCH2 n1 n2 n3 n4 [VTHRESHOLD=val] [Rin1=val] [Rin2=val]
[Rout1=val] [Rout2=val]
Netlist Example
SWITCH2:1 1 2 3 4 VTHRESHOLD = 1V
Miscellaneous18-417

SWITCH3

threshold Real
Ports
Input1 First input signal (complex)
Input2 Second input signal (complex)
Input3 Third input signal, control signal (complex)
Notes
1. This model performs voltage-controlled switching. The control voltage is represented by V3:
Miscellaneous18-418
_V3 = V3I . cos(2πf3c t) - V3Q. sin (2πf3c t)
Where, V3I + jV3Q is the voltage complex envelope at the third input port, and f3c is its carrier
frequency. The carrier frequency f4c and voltage complex envelope (V4I + jV4Q) at output port
are determined by
f4c = f1c, and (V4I + jV4Q)) = (V11 + jV1Q) for the condition V3 > VTHRESHOLD, and
f4c = f2c, and (V4I + jV4Q) = (V2I + jV2Q) elsewhere
where, f1c, V1I + jV1Q are the carrier frequency and voltage complex envelope at the
first input port, and f2c, V2I + jV2Q are the carrier frequency and voltage complex
envelope at the second input port.
Netlist Form
SWITCH3:Name n1 n2 n3 n4 [VTHRESHOLD=val]
[Rin1=val][Rin2=val] [Rin3=val] [Rout=val]
Netlist Example
SWITCH3:1 1 2 3 4 VTHRESHOLD=1V
Miscellaneous18-419
Voltage Controlled Amplifier (VCA)

VCA
G Gain of amplifier None 1 (-Inf, Inf)/Real
FORMAT_G Format of gain: 0 for None 0 [0, 1]/Integer

linear scale, 1 for dB
Ports
Input1 Input1 signal (Complex)
Input2 Input2 signal (Complex)
Output Output signal (Complex)
Notes
1. This model performs voltage-controlled amplification. The gain of the amplifier could be a
function of the control voltage determined by an equation given in G. The control voltage is
represented by _V2
_V2 = V2I . cos (2πf2c t) - V2Q. sin (2πf2c t),
Miscellaneous18-420
where V2I + jV2Q is the voltage complex envelope at the second input port, and f2c is its carrier
frequency. The output carrier frequency equals to the carrier frequency of the first input signal.
The voltage complex envelope at the output port (V3I+jV3Q) is calculated by
V3I + V3Q = GAIN . (V1I + V1Q ).
V3 I + jV3Q = GAIN ⋅ (V1I + jV1Q )
Where, V1I + jV1Q is the voltage complex envelope at the first input port, and GAIN is calcu-
lated by the given equation G.
2. Case 1: The default equation format
If FORMAT_G isn’t specified, then GAIN = G. For example, if G = (10+_V2) and if
FORMAT_G isn’t specified, then GAIN=(10+_V2).
3. Case 2: The dB format:
If FORMAT_G is set to 1, then the equation is calculated in dB. For example, if
G = (10 +_V2) and FORMAT_G = 1, then
GAIN = 10 (10 + _V 2 ) / 20
Netlist Form
VCA:Name n1 n2 n3 G=(equation) [FORMAT_G=val] [Rin1=val]
Netlist Example
VCA:1 1 2 3 G=(-10+ V2) FORMAT_G=1
Miscellaneous18-421
Window (WINDOW)
Window (WINDOW)
WINDOW
NSAMP Number of input samples to None 64 [1, Inf)/Integer

window per invocation
WINDOW_LENGTH Length of window in None 16 [1, Inf)/Integer

samples
WINDOW_SHIFT Initial shift of window in None 1 [0, Inf)/Integer

samples
WINDOW_TYPE 0: Bartlett None 0 [0, 8]/Integer

1: Hanning
2: Rectangular
3: Hamming
4: Blackman
5: Blackman-Harris (3 term)
6: Blackman-Harris (4 term)
7: Gaussian (alpha=3)
8: De la Valle-Poussin.
Ports
Miscellaneous18-422
Window (WINDOW)
Notes
1. This model windows a real signal using various window functions. During each invocation,
this model processes NSAMP input samples. The number of samples windowed is determined
by WINDOW_LENGTH. The position of the window’s left edge is determined by
WINDOW_SHIFT.
Netlist Form
WINDOW:Name n1 n2 NSAMP=val WINDOW_LENGTH=val
WINDOW_SHIFT=val WINDOW_TYPE=val [Rin=val][Rout=val]
Netlist Example
WINDOW:1 1 2 NSAMP=256 WINDOW_LENGTH=40 WINDOW_SHIFT=10
WINDOW_TYPE=2
Miscellaneous18-423
19
Modulators
Modulators19-424
Amplitude Modulator (AMMOD)

AMMOD
Property Description Units Default Range
FC Carrier frequency Hz 1000000 [0, Inf)/Real
P Carrier power Watt 0 [0, Inf)/Real
REF Input signal voltage level for 100 Volt 1 [-1e6, 1e6]/Real
percent AM
TYPE Type of AM modulator None 1 [1, 2]/Integer

(optional):
1: Conventional AM modulator
2: Suppressed carrier
RIN Input impedance Ohm Inf (0, Inf]
ROUT Output impedance Ohm 0 [0, Inf)
Ports
Output Output of amplitude modulator (complex)
Notes
1. This model performs amplitude modulation (AM). The input to this model is assumed to be a
baseband signal vin(t). The output is an amplitude modulated bandpass signal with a carrier
frequency FC and a carrier power P.
Modulators19-425
There are two different types of amplitude modulation. The output in-phase and quad-phase
envelopes are given as follows, respectively
1.TYPE = 1 for conventional AM modulation

vout,i(t) = A • (1 + vin(t)/REF)
vout,q(t) = 0
2.TYPE = 2 for suppressed carrier

vout,i(t) = A • vin(t)/REF
vout,q(t) = 0
A = SQRT(8 • ROUT • P) for FC < input sampling rate/2 (i.e., sampled carrier output)
or
A = SQRT(4 • ROUT • P) for FC > input sampling rate/2 (i.e., complex envelope output)
Netlist Form
AMMOD:Name n1 n2 FC=val P=val REF=val [TYPE=val][Rin=Val]
[Rout=Val]
Netlist Example
AMMOD:1 1 2 FC=1MHz P=0.002W RFE=1mV TYPE=1
Modulators19-426
PI/4 DQPSK Modulator (DQPSKMOD)

DQPSKMOD
RIN1 Input impedance Ohm Inf (0, Inf]
ROUT1 Output1 impedance Ohm 0 [0, Inf)
ROUT2 Output2 impedance Ohm 0 [0, Inf)
Ports
Input Integer symbol values A(n) ( real)
Output1 in-phase output of modulator ( real)
Output2 Quadrature output of modulator (real}
Notes
1. This model performs PI/4DQPSK modulation. The input to this model is assumed to be the
symbol values A(n) = 0, 1, 2, 3 for n ≥ 0. The modulation information is stored differentially in
the phase. Specifically, the in-phase and quadrature outputs of the modulator are given by
cos(theta(n)) and sin(theta(n)) respectively, where
theta(-1) = PI/4, and
theta(n) = theta(n-1) + delta_theta(n),n ≥ 0
PI/4 if A(n) = 0
3 * PI/4 if A(n) = 1
delta_theta(n) =
7 * PI/4 if A(n) = 2
Modulators19-427
5 * PI/4 if A(n) = 3
Netlist Form
DQPSKMOD:Name n1 n2 n3 [Rin=Val] [Rout=Val]
Netlist Example
DQPSKMOD:1 1 2 3
Modulators19-428
Edge Modulator (EDGEMOD)

EDGEMOD
ROUT1 Output impedance Ohm 0 [0, Inf)
Ports
Output1 Output of AM modulator (complex)
Output2 Output of AM modulator (complex)
Notes
1. This model converts each three input bits into a pair of in-phase and quadrature output signals
based on the EDGE 8PSK modulation. The in-phase and quadrature output values at time
index n are calculated using equations
VI ( n ) = cos(θ n + θ n ,offset )
and
VQ (n ) = sin (θ n + θ n ,offset )
respectively; where n is the total number of received symbols. The EDGE 8PSK modulation
uses the following mapping of input-bit triplets onto each phase θn:
Modulators19-429
3π π π π 3π π
000 → 010 → 011 → 100 → − 101 → − 110 → −
4 , 001 → π , 2, 4, 2, 4 , 4,
111 → 0 .
Where θn, offset is the additional phase shift at the time index n, equal to n x 3π/8.
Form
EDGEMOD:Name n1 n2 n3 [Rin=val], [Rout1=val], [Rout2=val]
Example
EDGEMOD:1 1 2 3
References
1. GSM 05.04 (i.e., ETSI EN 300 959): “Digital cellular telecommuneications system (Phase 2+);
Modulation”
Modulators19-430
Frequency Modulator (FMMOD)

FMMOD
SEN Frequency deviation sensitivity, Hz/V 0 [-1e6, 1e6]/Real

in Hz/Volt
PHASE Output phase shift Deg 0 (-Inf, Inf)/Real
Ports
Output Output of frequency modulator (complex)
Notes
1. This model performs frequency modulation (FM). The input to this model is assumed to be a
baseband signal vin(t). The output is an FM modulated bandpass signal with carrier frequency
FC and carrier power P. The output in-phase and quad-phase envelopes are given as follows,
respectively
vout,i(t) = A • cos(θ(t)+phase)
vout,q(t) = A • sin(θ(t)+phase)
Modulators19-431
where
θ(t) = ∫ ( 2 π SEN • vin(t)) dt
and
or
Netlist Form
FMMOD:Name n1 n2 FC=val P=val SEN=val [PHASE=Val] [Rin=Val]
[Rout=Val]
Netlist Example
FMMOD:1 1 2 FC=1MHz P=0.002W SEN=1.2 PHASE=45deg
Modulators19-432
Gaussian Minimum Shift Keying Modulator (GMSK)

GMSK
NB Number of bits per None 1 (0, 8]/Integer

symbol
MOD_INDEX Modulation index None 0.5 (0, 1]/Integer

of GMSK
modulator
NUM_SAMPLES Number of samples None 8 (0, Inf]/Integer

per symbol
RESPONSE_LENGTH Length of Gaussian None 4 (0, Inf]/Real

filter impulse
response in
symbols
NORMALIZED_BW Normalized Hz 0.3 (0, 1]/Integer

bandwidth of
Gaussian filter
Modulators19-433
Ports
Input Input symbols in the range 0, 1, ...., M - 1, where M = 2NB (real)
Output1 in-phase output of GMSK modulator (real)
Output2 Quadrature output of GMSK modulator (real)
Notes
1. This model modulates a sequence of input symbols that have values in the range 0 to M – 1 ,
where M = 2NB.
The input to this model must be the symbol values Ai, where 0 ≤ Ai ≤ M 1, and M = 2NB.
Each Ai input symbol value is then internally converted to the symbol value Ki, where
Ki = 2 * (Ai + 1) – M. This implies that the values Ki may assume are
– (M – 1), ...., –5, –3, –1, +1, +3, +5, ....., +(M – 1).
For example, when NB = 1 (i.e., each symbol is represented by one bit as in the binary case),
the values Ki may assume would be -1 and +1 only.
Each Ki symbol value (representing NB bits) is then upsampled by NUM_SAMPLES by add-

ing NUM_SAMPLES - 1 zeros after each Ki symbol value. In other words,
NUM_SAMPLES represents the number of samples per symbol inside the GMSK modulator.
Upsampling is performed because this model involves a Gaussian filtering process to fre-
quency modulate the carrier.
The n-th sample of the in-phase and quadrature outputs of the GMSK modulator is given by
cos(theta(n)) and sin(theta(n)) respectively, where
theta(n) = 2 * PI * MODULATION_INDEX * SUM_1(Ki * q[n - i]) +

PI * MODULATION_INDEX * SUM_2(Ki)
where the limits of SUM_1 are from i = n - RESPONSE_LENGTH + 1 to n, and
the limits of SUM_2 are from i = 0 to n - RESPONSE_LENGTH.
The filter coefficients q[i], 0 ≤ i ≤ RESPONSE_LENGTH * NUM_SAMPLES - 1, are

determined from integrating a Gaussian filter's impulse response [1]. The duration of this
impulse response (in samples) is RESPONSE_LENGTH * NUM_SAMPLES.
The frequency response of the Gaussian filter is determined by the normalized bandwidth
(NORMALIZED_BW) which is given by B * T, where B is the 3dB-bandwidth of the
Gaussian filter and T is the symbol duration. For example, the bit rate in the GSM system
(NB = 1) is 3.69 µS, therefore, a normalized bandwidth of NORMALIZED_BW = 0.3 (used
Modulators19-434
by the GSM system) should correspond to a Gaussian filter's 3dB-bandwidth of 81.25 KHz.
Netlist Form
GMSK:Name n1 n2 n3 NB=val MODULATION_INDEX=val
NUM_SAMPLES=val + RESPONSE_LENGTH=val NORMALIZED_BW=val
[Rin=Val] [Rout=Val]
Netlist Examples
1. Example 1:
GMSK:1 1 2 3 NB=1 MODULATION_INDEX=0.5 NUM_SAMPLES=2
+ RESPONSE_LENGTH=3 NORMALIZED_BW=0.3
The parameters in this example correspond to those used by the GSM system. A typical input
sequence and the corresponding output sequence are shown in the following table:
Input Modified
in-phase Quadrature
to unsampled
Output Output
GMSK Input
1 +1.000 1.000 0.009
0.000 0.994 0.111
0 -1.000 0.884 0.468
0.000 0.563 0.826
0 -1.000 0.571 0.821
0.000 0.930 0.368
. . . .
. . .
. . . .
. . .
2. Example 2:
Modulators19-435
GMSK 1 2 3 NB=2 MODULATION_INDEX=0.5 NUM_SAMPLES=3 +

RESPONSE_LENGTH=4 NORMALIZED_BW= 0.25
Modified
Input to in-phase Quadrature
unsampled
GMSK Output Output
Input
2 +1.000 1.000 0.001
0.000 1.000 0.008
0.000 0.999 0.039
1 -1.000 0.992 0.126
0.000 0.952 0.305
0.000 0.839 0.544
1 -1.000 0.676 0.737
0.000 0.600 0.800
0.000 0.703 0.711
2 +1.000 0.901 0.434
0.000 1.000 0.000
0.000 0.901 -0.434
2 +1.000 0.703 -0.711
0.000 0.606 -0.796
0.000 0.703 -0.711
3 +3.000 0.903 -0.438
0.000 0.999 0.034
0.000 0.823 0.568
3 +3.000 0.260 0.966
Modulators19-436
0.000 -0.610 0.793
0.000 -0.966 -0.259
0 -3.000 0.074 -0.997
0.000 1.000 -0.029
0.000 0.222 0.975
. . . .
. . .
. . .
. . . .
References
1. Raymond Steele, Mobile Radio Communications, Pentech Press, 1992.
Modulators19-437
I-Q Modulator (IQMOD)

IQMOD
CP Carrier power Watt 0.01 [0, Inf)/Real
VREF Input signal voltage Volt 1 [-10e-6, 10e6]/Real

level
PHIQ I-Q phase imbalance Deg 0 [-180, 180]/Real
Ports
Input1 First input signal (real)
Input2 First second signal (real)
Notes
1. For a given in-phase and quadrature baseband signals VIin (t ) and VQin (t ) , the output voltage
Modulators19-438
is computed according to:

{
Vout (t ) = Re U (t )e j 2πFct }
where
[
Re{U (t )} = ( A / VREF ) V Iin (t ) − VQin (t ) sin( PHIQ ) , and ]
Im {U (t )} = ( A / VREF )[V Qin (t ) cos( PHIQ ) ]
With
A = 2 • 50 • CP (CP in Watts)
Netlist Form
IQMOD:Name n1 n2 n3 FC=val CP=val VREF=val PHIQ=val
[Rin=Val] [Rout=Val]
Netlist Example
IQMOD:1 1 2 3 FC=0HZ CP=.01W VREF=1V PHIQ=0DEG
Modulators19-439
Logarithmic Amplifier (LOGAMP)

LOGAMP
SEN Log sensitivity, in V/dB 0 [0, Inf)/Real

voltage units per dB
PL Low input power Watt 0 [1e-23, 1e17]/Real
E Peak log error, in dB dB 0 [0, 200]/Real
EC Log error cycle, in dB dB 1 [0, 200]/Real
Ports
Notes
1. This model performs logarithmic amplification. The input to this model is assumed to be a
bandpass signal with in-phase and quad-phase envelopes vin,i(t) and vin,q(t). The output is a
bandpass signal and has same carrier frequency as the input. The output in-phase and quad-
phase envelopes are logarithmically amplified as follows
vout,i(t) = M2(t) • vin,i(t)/A1(t)
vout,q(t) = M2(t) • vin,q(t)/A1(t)
where
Modulators19-440
A1(t) = SQRT(vin,i(t)2 + vin,q(t)2)

M2(t) = 20 • SEN • LOG10(A1(t)/VL)+ SEN • E • sin(θ)for A1(t) > VL
M2(t) = 0 for A1(t) ≤ VL
VL = SQRT(2 • 50 • PL)
θ = 2 • π • (PA - 10 • LOG10(PL))/EC
PA = 10 • LOG10(A1(t)2/(2 • 50))
Netlist Form
LOGAMP:Name n1 n2 SEN=val PL=val E=val EC=val [Rin=Val]
[Rout=Val]
Netlist Example
LOGAMP:1 1 2 SEN=1.2 PL=10W E=0.75dB EC=10dB
Modulators19-441
Phase Modulator (PMMOD)

PMMOD
SEN Phase deviation Radian/ 1 [-1e6, 1e6]/Real

sensitivity, in rad Sec/Volt
per second per
volt
Ports
Output Output of phase modulator (complex)
Notes
1. This model performs phase modulation. The input to this model is assumed to be a baseband
signal vin(t). The output is a phase modulated bandpass signal with carrier frequency FC and
carrier power P. The output in-phase and quad-phase envelopes are given as follows, respec-
tively
vout,i(t) = A • cos(θ(t))
vout,q(t) = A • sin(θ(t))
where
Modulators19-442
θ(t) = SEN • vin(t)

and
or
Netlist Form
PMMOD:Name n1 n2 FC=val P=val SEN=val [Rin=Val] [Rout=Val]
Netlist Example
PMMOD:1 1 2 FC=1MHz P=0.002W SEN=1.2
Modulators19-443
Phase Shift Keying Modulator (PSKMOD)

PSKMOD
M The order of the None 2 [2, 128]/Integer

signal space.
M = 2: BPSK
M = 4: QPSK, etc.
Ports
Input Input signal of symbols in the range 0,....., M -1 ( integer)
Output1 The real part of the complex output signal (real)
Output2 The imaginary part of the complex output signal (real)
Notes
1. This model maps the integer input symbols, each in the range 0,...., M -1, into a complex (real
and imaginary) output value. The complex value of the output is given by
exp(j* 2*PI*k/M) M = 2
Modulators19-444
exp(j* 2*PI*(k+1/2)/M), M = 4, 6, 8, ..
Netlist Form
PSKMOD n1 n2 n3 M=val [Rin=Val] [Rout=Val]
Netlist Example
PSKMOD:1 1 2 3 M=4
Modulators19-445
Quadrature Amplitude Modulator (QAMMOD)

QAMMOD
M Order of QAM None 4 (0, Inf)/Integer

constellation
Ports
Output1 in-phase output (real)
Output2 Quadrature output (real)
Notes
1. For a given stream of input bits, this model combines every incoming N bits, where
N = Log 2 ( M )
and M is the order of the constellation space (i.e. M=4 for 4-QAM, M=16 for 16-QAM, and
M=64 for 64-QAM).
Each incoming N bits are split into half, N/2 bits are used to compute the in-phase output sam-
ple and the other N/2 bits are used to compute the corresponding quadrature output sample.
Modulators19-446
For each N/2 input bits (per I and Q), the corresponding in-phase and quadrature output sam-
ples are computed according to
I = 2M I + 1 − M
Q = 2M Q + 1 − M
Where, MI and MQ are the corresponding decimal values of the N/2 in-phase and quadrature
binary bits. The output (I and Q) symbol rate is equal to 1/N times the input bit rate.
Netlist Form
QAMMOD:Name n1 n2 n3 M=val [Rin=Val] [Rout=Val]
Netlist Example
QAMMOD:1 1 2 3 M=4
Modulators19-447
20
Nonlinear RF
Nonlinear RF20-448
Amplifier (AMP)
Amplifier (AMP)
AMP
FILE File name that holds the None Optional String

data
DEVICE The data section name None Optional String

(for .FLP data format
only)
MS11 Magnitude of S11 in dB dB -1e+020 (-Inf, 200]/Real
PS11 Phase of S11 Deg 0 [-180, 180]/Real
MS21 Magnitude of S21 in dB dB 0 (-Inf, 200]/Real
OIP2 Output power at second dBm 0 [0, Inf)/Real

order intercept point
Nonlinear RF20-449
Amplifier (AMP)
OIP3 Output power at third dBm 0 [0, Inf)/Real

P1dB Output power at 1 dB dBm 0 [0, Inf)/Real

compression point
Psat Output power at dBm 0 [0, Inf)/Real

saturation
TEMP Local temperature Cel 25 (0, Inf)/Real
NF Noise figure in dB dB 0 [0, 200]/Real
FMIN Minimum noise figure dB 0 [0, 200]/Real

in dB
MGO Magnitude of optimum None 0 [0, Inf)/Real

noise figure reflection
coefficient
PGO Phase of optimum noise Deg 0 (-Inf, Inf)/Real

figure reflection
coefficient
RN Real equivalent Ohm 0 [0, Inf)/Real

normalized noise
resistance
MINF Harmonics below Hz 0 [0, Inf)/Real

MINF ignored
MAXF Harmonics above GHz 100 [0, Inf)/Real

MAXF ignored
MOD Model name None Optional String

corresponding to the
.model block
INTERP Interpolation method None cubic (linear, cubic)
Nonlinear RF20-450
Amplifier (AMP)
Notes
1. OIP3(dBm) = P1dB(dBm) + 10.64 dB.

2. Either OIP3 or P1dB can be specified, but not both.
3. If noise figure (NF) and the noise parameters (FMIN, MGO, PGO, and RN) are both specified,
the noise parameters will be used for noise calculations.
4. For more accurate calculations, measured or circuit simulation data can be supplied using:
• FLP (old format)
• Extended NMF (Neutral Model Format)
Note NMF, or Neutral Model Format, is designed to be a common file format that allows
data transfer among microwave simulators. Designer supports the linear table-based
data subset of the NMF specification. The full MDE Neutral Model Format
Specification must be obtained from the MAFET consortium.
• S2P
• CITI
FLP data files should have a ".flp" extension (e.g., AmpData.flp) and extended NMF files
should have a ".nmf" extension (e.g., AmpData.nmf).
Measured data will override model parameters. For example, if the MS21 parameter is speci-
fied and at the same time measured S-parameter data is referenced in an external data file, the
calculations will be based on the measured S-parameter data.
5. Amplifier measured data can be one or a combination of the following:
• AM-AM and AM-PM compression data
• S, Y, Z, and ABCD parameters
• NF
• Noise parameters: FMIN, GOPT, RN
• IP3
6. Measured data can be a function of several independent variables like input frequency (Tone1
or Freq), input power (P1), and temperature (TEMP).
7. Refer to the example project AmpDataFileExamples and the following external data files in
the directory Examples\System:
• The data file Compression_and_Sparam.flp is an example of AM-AM/AM-PM first
harmonic compression data and S-parameters in FLP format. This data file is used by the
design H1_Compression_and_Sparam_FLP. Note that the DEVICE parameter is always
specified with FLP data files.
• The data file Compression_and_Sparam.nmf is an example of AM-AM/AM-PM first
harmonic compression data and S-parameters in extended NMF. This data file is used by
Nonlinear RF20-451
Amplifier (AMP)
the design H1_Compression_and_Sparam_NMF. Note that no DEVICE parameter is

specified with NMF data files.
• The data file CompressionVsFreq.nmf is an example of frequency-dependent first har-
monic compression data using extended NMF. This data file is used by the design
H1_Compression_vs_Freq.
• The data file H1_and_H2_Compression.nmf is an example of first and second harmonic
compression data specified in extended NMF. This data file is used by the design
H1_H2_Compression.
• The data file OIP3_and_Sparam.nmf is an example of specifying OIP3 and S-parame-
ters versus input frequency using extended NMF. This data file is used by the design
OIP3_vs_Freq.
• The data file s2pn.s2p is an example of S2P data (including noise parameters). This data
file is used by the design S2P_With_Noise.
• The data file Sparam_and_NF.nmf is an example of S-parameters and noise figure ver-
sus input frequency (Tone1) and temperature (TEMP) using extended NMF. This data file
is used by the design Sparam_and_NF_vs_Freq_and_Temp.
Nonlinear RF20-452
Amplifier (AMP)
The format for specifying data in extended NMF is:

! Start of First Block
BEGIN BLOCK
! Start with Block Header
VAR PARAMETER = Xn UNIT:string INTERPOLATION:YES|NO
. . . . .
. . . . .
VAR PARAMETER = X2 UNIT:string INTERPOLATION:YES|NO
! X0 is the parameterized table variable
! End of Header
!
! Start of DataSet1
VAR Xn = val
.
.
VAR X2 = val
VAR X1 = val
BEGIN DATA
% X0 A(string) B(string) C(string)… ! Required
val val val val
val val val val
… … … …
val val val val
END
! End of DataSet1
!
! Start of DataSet2
VAR Xn = val
.
.
VAR X2 = val
VAR X1 = val
BEGIN DATA
% X0 A(string) B(string) C(string)… ! optional
val val val val
val val val val
… … … …
val val val val
END
.
END BLOCK
Nonlinear RF20-453
Amplifier (AMP)
Note that for the extended NMF data shown above:
• A(string) in a data set is used to define the name of the column and describe the unit/for-
mat of each data column.
• A is the name
• string = string1 UNIT:string2
• string1 is optional and represents the format information. The format can assume
one of the following values:
REAL (default)
RI (expects a 2-column data with no header required for the second imaginary
column )
MA (expects a 2-column data with no header required for the second angle col-
umn )
dB (expects a 2-column data with no header required for the second angle col-
umn )
• UNIT:string2 is optional and represents the unit information e.g., pF, dB, dBm,
...etc.
• A data block must always start with BEGIN BLOCK and end with END BLOCK unless
a data file has a single data block, in which case these two statements are not required.
• A data set within a data block always starts with BEGIN DATA and ends with END.
• Data sets within a given data block must be of the same type and have the same number of
columns. The header of a data set is only required for the first data set and assumed
optional for the remaining data sets. If a header is used with each data set, the same header
must be used for all data sets within a given data block
• Multiple data blocks supporting multiple data formats are allowed to be present in a single
NMF data file with each data block identified by its corresponding BEGIN BLOCK and
END BLOCK statements.
• Multiple data blocks supporting the same data format are not allowed.
Netlist Form
AMP:Name n1 n2 [MS11=val] [MS12=val] . . . [T=val]
Netlist Example
AMP:1 12 15 MS21=-5dB NF=2.5 OIP3=17dBm
Nonlinear RF20-454
Frequency Multiplier (FMULT)

FMULT
N Multiplier factor None 1 [1, Inf)/Integer
Pin Reference single tone input dBm 0 (-Inf, 200]/Real

power for specified harmonic
conversions
G1 Power gain of input tone in dB dB 0 (-Inf, 200]/Real
G2 Power gain of second harmonic dB -1e+020 (-Inf, 200]/Real

relative to input tone in dB
G3 Power gain of third harmonic dB -1e+020 (-Inf, 200]/Real

G4 Power gain of fourth harmonic dB -1e+020 (-Inf, 200]/Real

Nonlinear RF20-455
G5 Power gain of fifth harmonic dB -1e+020 (-Inf, 200]/Real

G6 Power gain of sixth harmonic dB -1e+020 (-Inf, 200]/Real

G7 Power gain of seventh harmonic dB -1e+020 (-Inf, 200]/Real

G8 Power gain of eighth harmonic dB -1e+020 (-Inf, 200]/Real

G9 Power gain of ninth harmonic dB -1e+020 (-Inf, 200]/Real

MINF Harmonics below MINF ignored Hz 0 [0,Inf)/Real
MAXF Harmonics above MAXF GHz 100 [0,Inf)/Real

ignored
Notes
1. This model produces an output spectrum according to the specified harmonic conversion gains
(G1, G2, ..G9). For example, a single tone input power of 0dBm and G2 = -20dBm would
result in a second harmonic output power of -20dBm.
2. This model supports conversion gain for harmonics beyond the 9th harmonic. This can be done
by specifying GN, N > 9, in the netlist property of the FMULT component.
3. The specified conversion gains are based on a single tone reference power Pin. If multiple
input tones are present at the input of the FMULT element, unwanted harmonics and intermod-
ulation products will be generated.
4. For frequency domain analysis, specifying the parameter Pin is not necessary since the simula-
tor will use the tone with the maximum input power as the reference input power. This will
result in an ideal linear harmonic transformation for a single tone input. In other words, the
conversion gain will be independent of the input power for a single tone input. This is not the
case if more than one tone is present at the input.
5. For discrete-time domain analysis, it is necessary to accurately specify the reference input
power Pin used for the specified conversion gains. For discrete-time analysis, the frequency
multiplier is not independent of the input power for single or multitone inputs.
6. MINF and MAXF are used to block out unwanted output harmonics for frequency domain
analysis only.
Nonlinear RF20-456
Netlist Form
FMULT:Name n1 [n2] [N=val] [MS11=val] . .
Netlist Example
FMULT:1 1 2 N = 2 PIN = 0dBM G1 = -20 G2 = 20 G3 = -10 ...
Nonlinear RF20-457
Mixer (MIXER)
Mixer (MIXER)
MIXER
FILE File name that holds None Optional String

the data

(for .FLP data files
only)
MS11 Magnitude of S11 in dB -1e+020 (-Inf, 200]/Real

dB
MS22 Magnitude of S22 in dB -1e+020 (-Inf, 200]/Real

dB
CONVGAINMAG RF to IF gain in dB dB 0 (-Inf, 200]/Real
Nonlinear RF20-458
Mixer (MIXER)
CONVGAINPHASE RF to IF phase shift Deg 0 [-180,180]/Real
LOTOIFISOLATION LO to IF isolation in dB 200 [0, 200]/Real

dB
RFTOIFISOLATION RF to IF isolation in dB 200 [0, 200]/Real

dB
IFTORFISOLATION IF to RF isolation in dB 200 [0, 200]/Real

dB
OIP2 Output power at dBm 0 [0, Inf)/Real

second order intercept
point

P1dB Output power at 1dB dBm 0 [0, Inf)/Real

compression point

saturation
TEMP Local temperature Cel 298 (0, Inf)/REAL
NF Noise figure in dB dB 0 [0, 200]/Real
FMIN Minimum noise figure dB 0 [0, 200]/Real

in dB
MGO Magnitude of None 0 (0, Inf)/Real

optimum noise figure
reflection coefficient
PGO Phase of optimum Deg 0 (-Inf, Inf)/Real

coefficient
Nonlinear RF20-459
Mixer (MIXER)

normalized noise
resistance
NRF RF frequency None 1 (-Inf, Inf)/Integer

multiplier
NLO LO frequency None -1 (-Inf, Inf)/Integer

multiplier
MAXO Maximum order for None 10 (0, Inf)/Real

spurs
MINF Spurs below MINF Hz 0 (0, Inf)/Real

ignored
MAXF Spurs above MAXF GHz 100 (0, Inf)/Real

ignored
MINP Spurs below MINP Watt 0 (0, Inf)/Real

ignored
FLO LO Frequency Hz 1 (0, Inf)/Real
PLO LO Power Watt 1 (-Inf, Inf)/Real
F1 First frequency offset Hz 0 (10, Inf)/Real

from FLO
F2 Second frequency Hz 0 (F1, Inf)/Real

offset from FLO
M2 Phase noise Deg -180 [-180,0]/Real

magnitude at F2
TYPE 0 for low Q None 0 0,1

1 for High Q
mod Model name None Optional String

.model block
Nonlinear RF20-460
Mixer (MIXER)
Notes
1. Mixer S-parameters and noise parameters are treated as if they were measured on a two-port
black box. The fact that the input and output frequencies are different is ignored during analy-
sis. The input frequency is always used for interpreting any measurement data associated with
this element.
2. The nonlinear figures of merit (OIP2, OIP3, P1dB, and PSAT) are specified based on the refer-
ence LO power (PLO).
3. OIP3(dBm) = P1dB(dBm) + 10.64 dB.
5. This model accepts MIXERSPURS data table. Refer to the MIXERSPURS data table example
and discussion in the Three Port Mixer (MIXER3P) model in this chapter.
6. This model also accepts all the linear and nonlinear two-port measurement data used by the
amplifier (AMP) model. Refer to examples of measured data for the AMP model in this chap-
ter.
7. The oscillator noise parameters are specified in a fashion similar to those of the one port oscil-
lator element (OSC). For more information on that, please refer to the Sources chapter.
Netlist Form
Mixer:Name n1 n2 [T=val] [MS11=val] . . .
Netlist Example
MIXER:A 12 15 CONVGAINMAG =-5dB OIP3=17dBm
Nonlinear RF20-461
Three Port Mixer (MIXER3P)

MIXER3P
FILE File name that holds the None Optional String

data

(for .FLP data files only)
PS22 Phase of S22 Deg 0. [-180, 180]/Real
CONVGAINMAG RF to IF gain in dB dB 0 (-Inf, 200]/Real
CONVGAINPHASE RF to IF phase shift Deg 0 [-180,180]/Real
Nonlinear RF20-462
LOTOIFISOLATION LO to IF isolation in dB dB 200 [0, 200]/Real
RFTOIFISOLATION RF to IF isolation in dB dB 200 [0, 200]/Real
IFTORFISOLATION IF to RF isolation in dB dB 200 [0, 200]/Real
OIP2 Output power at second dBm 0 [0, Inf)/Real


P1dB Output power at 1 dB dBm 0 [0, Inf)/Real

compression point

saturation
TEMP Local temperature Cel 25 (0, Inf)/REAL
NF Noise Figure in dB dB 0 [0, Inf)/Real
FMIN Minimum noise figure dB 0 [0, 200)/Real

in dB
MGO Magnitude of optimum None 0 [0, Inf)/Real

coefficient
PGO Phase of optimum noise Deg 0 [-180, 180]/Real

figure reflection
coefficient

normalized noise
resistance
NRF RF frequency multiplier None 1 (-Inf, Inf)/Real
NLO LO frequency multiplier None -1 (-Inf, Inf)/Real
Nonlinear RF20-463
PLO Reference LO power Watt 1 [0,Inf)/Real
MAXO Maximum order for None 10 (0, Inf)/Real

spurs
MINF Spurs below MINF Hz 0 (0, Inf)/Real

ignored
MAXF Spurs above MAXF GHz 100 (0, Inf)/Real

ignored
MINP Spurs below MINP Watt 0 [0, Inf)/Real

ignored
mod Model name None Optional String

.model block
Notes
1. Mixer S-parameters and noise parameters are treated as if they were measured on a two-port
black box. The fact that the input and output frequencies are different is ignored during analy-
sis. The input frequency is always used for interpreting any measurement data associated with
this element.
2. Refer to <Install>\Examples\System\MixerDataFileExamples.adsn for three design exam-
ples using FLP and NMF MIXERSPURS data tables.
3. The nonlinear figures of merit (OIP2, OIP3, P1dB, and PSAT) are specified based on the refer-
ence LO power (PLO) parameter.
4. OIP3(dBm) = P1dB(dBm) + 10.64 dB.
6. If a MIXERSPURS data table is supplied, analysis will incorporate this table in a way similar
to the 2-port mixer model. The main difference is that the LO frequency and power are deter-
mined from the signal driving the LO port (as opposed to being specified for the 2-port mixer
model). The fundamental frequencies at the input (first) port and the LO (third) port will gen-
erate spurs at the output according to the supplied MIXERSPURS data table.
7. Note that the input and LO power levels may be optionally specified (see below) in MIXER-
SPURS data tables when performing frequency domain analysis. Specifying these power lev-
els is required for discrete time analysis. The measured or simulated MIXERSPURS data is
assumed to be applicable to the specified input LO and RF power levels. If during simulations,
Nonlinear RF20-464
the signals driving the input and/or LO ports have power levels different from those specified
in the supplied data table, the generated output spurs will be adjusted based on the actual
power levels. The adjustment is typically reasonable for LO levels not exceeding the reference
LO power by 3dBm and for RF levels not exceeding the reference RF power by 7dBm.
8. For frequency domain analysis, if a MIXERSPURS data table is referenced by the mixer, but
the table includes no information on the reference LO and/or RF power levels, then the online
reference LO power parameter PLO and the input tone with the maximum input power are
used as the reference LO and RF powers respectively for the MIXERSPURS data table.
9. If no MIXERSPURS data is supplied, then the nonlinear and isolation figures of merit are used
to compute the output signal.
10. An example of a MIXERSPURS data table (FLP format) is shown below:
MIX_1 3-PORT ! This is the device name and number of ports
* First Mixer Spur Table
* Input signal level (dBm) LO level (dBm)
MIXERSPURS MAXORDER = 10 PLO=10dBm PRF=-20dBm
*0 1 2 3 4 5 6 7 8 9 10
20 18 32 40 50 60 70 80 90 100 110
30 0 40 50 60 70 80 90 100 110
40 20 50 60 70 80 90 70 110
50 30 60 70 80 70 80 110
60 40 70 70 80 90 100
70 50 80 90 100 110
80 60 90 100 110
90 70 100 100
100 80 110
110 100
120
11. For any MIXERSPURS data table:
NRF = The row number = harmonic number for the input carrier frequency (FRF)
NLO = The column number = harmonic number for the LO frequency (FLO)
PRF = The reference input power level, in dBm
PLO = The reference LO power level, in dBm
SPUR(NRF x FRF + NLO x FLO) = The power level of the NRF x NLO IM product, in dB,
relative to the fundamental output power level.
For example, in the above MIXERSPURS data table, NRF = 0, 1, 2, ….10 and NLO = 0, 1,
2,..10 with NRF + NLO <= MAXO (default = 10).
Nonlinear RF20-465
Also, in the above data table SPUR(3 x FRF + 2 x FLO) = 50dB implies the power level of the
3 x FRF + 2 x FLO intermodulation product is 50 dB below the power level of the fundamental
output frequency. Note that SPUR(FRF + FLO) = 0 since the fundamental power relative to
itself is simply zero. Also note that the above (triangular) table assumes that each frequency
and its corresponding image have the same power level. For example, SPUR (3 x FRF + 2 x
FLO) is assumed to have the same power level as SPUR(3 x FRF - 2 x FLO).
If the actual input RF power is not equal to the specified reference RF power PRF and/or the
actual LO input power is not equal to the specified reference LO power PLO, then the output
IM products given above will be further adjusted. The adjustment is typically reasonable for
LO levels not exceeding the reference LO power by 3dBm and for RF levels not exceeding the
reference RF power by 7dBm.
Netlist Form
Mixer3P:Name n1 n2 n3 [T=val] [MS11=val] ....
Netlist Example
MIXER3p:A 12 15 17 CONVGAINMAG =-5dB OIP3=17dBm
Nonlinear RF20-466
20
Probes
Probes20-467
Adjacent Channel Power Ratio Probe (ACPRP)

ACPRP
Name Probe name None Required String
NSAMP Number of input None 1024 (0, Inf)/Integer

samples used for
acpr calculations
per invocation
IN_BAND Maximum Hz 1000 (0, ≤ MAX_OFFSET]/Real

_OFFSET frequency offset
of inband
spectrum
OUT_BAND Minimum Hz 1000 (0, ≤ MAX_OFFSET]/Real

_OFFSET frequency offset
of outband
spectrum
MAX_ Maximum Hz 100000 (0, Inf)/Real

OFFSET frequency offset
from center
frequency
INITSAMP Number of initial None 0 [0, Inf)/Integer

samples removed
from waveform
Probes20-468
Ports
Notes
1. For a given random input signal
V in ( t ) = A ( t ) cos ( 2 π f c t + θ ( t ) )
this model computes the average power in the main band ( i.e. desired band) as well as the
average power in the adjacent band ( i.e. undesired band), and then computes the ACPR as
ACPR = Power in adjacent bands/ Power in main bands = Area(B+B′) / Area(A+A’)
The calculated ACPR quantity will be more accurate for longer input sequences. During each
invocation of this model, a block of NSAMP input samples is used to compute the power spec-
trum of the input. This power spectrum is then used in the fashion described above to compute
the ACPR. As more input blocks become available at the input, the ACPR calculations will be
adjusted accordingly and tend to become more accurate.
Netlist Form
ACPRP:Name n1 NSAMP=val IN_BAND_OFFSET=val
OUT_BAND_OFFSET=val
+ MAX_OFFSET=val [INITSAMP=val] [Rin=val]
Netlist Example
ACPRP:My_Acprp NSAMP=256 IN_BAND_OFFSET=10KHZ
OUT_BAND_OFFSET=10KHZ MAX_OFFSET=15KHZ
Probes20-469
Average Power Probe (AVGPP)

AVGPP
INITSAMP Number of initial samples None 0 [0, Inf)/Integer

removed from waveform
Ports
Notes
1. The results of this probe may only be viewed in the SWEEP/Network Function domain. They
may not be viewed in the time or spectral domain. For a given input signal
This average power probe takes the samples of the incoming input complex envelope signal
Probes20-470
jθ ( t ) and computes the average power by

A ( t )e
N–1 jθ ( k∆t ) 2
1 A(k∆t)e
avgp = -------
R in ∑ ----------------------------------------
N
k=0
Where ∆t is the time sampling step, N is the total number of samples available at the input, and
Rin is the load impedance looking into the input port of the probe.
Netlist Form
AVGPP:Name n1 [Initsamp=val] [Rin=val]
Netlist Example
AVGPP:My_Avgpp 1
Probes20-471
Bit Error Rate Probe (BERP)

BERP
INITSAMP1 Number of initial samples None 0 [0, Inf)/Integer

removed from input1 waveform
INITSAMP2 Number of initial samples None 0

removed from input2 waveform
Ports
Notes
1. This model is used to calculate the BER in a digital communications systems by comparing a
transmitted stream of binary bits (Input1) with the corresponding received data stream
(Input2). The total error count (ErrorCount) is incremented by 1 each time a mismatch is
Probes20-472
detected between the two input streams. The final BER value is computed as:
ErrorCount
BER = -------------------------------
TotalCount
Systems with low BERs require an increased number of bits to be transmitted through the sys-
tem to obtain an accurate measure of BER
Netlist Form
BERP:Name n1 n2 [Initsamp1=val] [Initsamp2=val] [Rin1=val]
[Rin2=val]
Netlist Example
BERP:My_Berp 1 2
Probes20-473
Bandwidth Power Probe (BP)
Bandwidth Power Probe (BP)

BP
n1
BP
NAME Probe name None Required String
NSAMP Number of samples used None 1024 [0, Inf)/Integer

for calculation per
invocation
MINF Minimum frequency of the Hz 0 [0, Inf)/Real

band to be measured
MAXF Maximum frequency of Hz 1000 (MINF, Inf)/Real

the band to be measured
RIN Input impedance Ohm 50 (0, Inf)/Real
Ports
Notes
This probe calculates the power of the signal (across the input impedance RIN) in the frequency
band starting from MINF to MAXF.
Netlist Form
BP:NAME n1 [NSAMP=val][MINF=val][MAXF=val] [RIN=val]
Netlist Example
BP:1 1 NSAMP=1024 MINF=100Hz MAXF=1MHz
Probes20-474
Complementary Cumulative Distribution Function
Complementary Cumulative Distribution Function Probe (CCDFP)

CCDFP
nbin Number of histogram bins None 64 [1, Inf)/Integer
nsamp Number of samples used None 1024 [1, Inf)/Integer

for histogram
Initsamp Number of initial samples None 0 [0, Inf)/Integer

Ports
Notes
1. The Complementary Cumulative Distribution Function (CCDF) probe is equal to 1 minus the
value of CDFP. Refer to the notes of CDFP to see how CDF is calculated.
Netlist Form
CCDFP:NAME n1 nbin=val nsamp=val [Initsamp=val] [Rin=val]
Netlist Example
CCDFP:1 1 nbin=64 nsamp=65536
Probes20-475
Cumulative Distribution Function Probe (CDFP)

CDFP
nsamp Number of samples used None 1024 [1, Inf)/Integer

for histogram

Ports
Notes
1. The Cumulative Distribution Function (CDF) probe is similar to the Histogram probe. After
determining the histogram function, it is normalized by the total number of samples. After the
normalization is performed, a running sum is created to build the CDF.
2. The maximum and minimum values for the input signal waveform are determined for histo-
gram bin calculations. The histogram bins exist at intervals of dx = (Max_Input - Min_Input)
/ nbin. The bin centers are located at x[n] = (n + 0.5)*dx + Min_Input.
3. The total number of input samples per bin are determined and displayed versus the x-axis. If
the user specifies a nsamp value larger than the total number received from the source, the
Probes20-476
actual number of samples received will be used for the histogram calculation.
Netlist Form
CDFP:NAME n1 nbin=val nsamp=val [Initsamp=val] [Rin=val]
Netlist Example
CDFP:1 1 nbin=64 nsamp=65536
Probes20-477
Crest Factor Probe (CFP)
Crest Factor Probe (CFP)

CFP

Ports
Notes
1. This probe calculates the crest factor (the ratio of the peak value to RMS value of a waveform)
of an incoming signal. Suppose the input signal is ν(n), n = 1, 2, ...N . The crest factor is calcu-
lated as follows:
max ( v ( n ) ) -
CrestFactor = ----------------------------------------------
1 N 2
sqrt  ---- ∑ v ( n ) 
Nn = 1 
Form
CFP:NAME n1 [Initsamp=val] [Rin=val]
Example
CFP:1 2
Probes20-478
Error Vector Magnitude Probe (EVMP)

EVMP
Initsamp1 Number of samples removed None 0 [0, Inf)/Integer

from input1 waveform



RIN1 Input1 impedance Ohm Inf [0, Inf)/Real
Ports
Probes20-479
Input1 Received in-phase signal (real)
Input2 Received quadrature signal (real)
Input3 Reference in-phase signal (real)
Input4 Reference quadrature signal (real)
Notes
1. This probe calculates the error vector magnitude of a measured signal vector and an ideal (ref-
erence) signal vector (see the diagram).
Expressed using vector representation, the error vector magnitude (EVM) is simply:
|C | = | A − B |
The assumption here is that there is no constant offset between the measured and ideal signals.
That is, both vectors have a common origin. In here, the measured and referenced signals will
invariably have different peak levels due to attenuation, distortion,.. etc.
Consequently, the magnitudes for A and B need to be normalized, in our case, to the peak ref-
erence magnitude. For N input samples, the EVM reported by this probe is given by:
Probes20-480
N
1
∑ ---N-
2
C(n )
EVM = n=1 - × 100 o ⁄ o
--------------------------------------
MAX { B ( n ) 2 }
Netlist Form
EVMP:NAME n1 n2 n3 n4 [Initsamp1=val] [Initsamp2=val]
[Initsamp3=val] [Initsamp4=val] [Rin1=val] Rin2=val] Rin3=val]
Rin4=val]
Netlist Example
EVMP:1 1 2 3 4
Probes20-481
Frequency Trajectory Probe (FTRAJP)
Frequency Trajectory Probe (FTRAJP)

FTRAJP
Properties Description Units Default Range/Type
INITSAMP Number of initial samples None 0 [0,Inf)/Integer

RIN Probe Name Ohm inf (0, Inf]/Real
Ports
Notes
1. Given an input signal to this probe of the form:
V in ( t ) = A ( t ) cos ( 2 πf c t + θ ( t ) )
the measurement obtained by means of this probe is simply the frequency trajectory (i.e., vari-
ations) freq(t) of the input signal with respect to time:
freq ( t ) = f c + dθ ( t -)
------------
2 πdt
The derivative in the above expression is computed using a fine time step which is equal to the
inverse of the sampling frequency of the envelope of the input signal.
Netlist Form
FTRAJP:Name n1 [Initsamp=val] [Rin=val]
Netlist Example
FTRAJP:My_Ftrajp 1
Probes20-482
Histogram Probe (HISTP)

HISTP
nsamp Number of samples used for None 1024 [1, Inf)/Integer

histogram

Ports
Notes
1. The maximum and minimum values for the input signal waveform are determined for histo-
gram bin calculations. The histogram bins exist at intervals of dx = (Max_Input - Min_Input)
/ nbin. The bin centers are located at x[n] = (n + 0.5)*dx + Min_Input.
The total number of input samples per bin are determined and displayed versus the x-axis, rep-
resented by the bin locations. If the user specifies a nsamp value larger than the total number
received from the source, the actual number of samples received will be used for the histogram
calculation.
Probes20-483
Form
HISTP:NAME n1 nbin=val nsamp=val [Initsamp=val] [Rin=val]
Example
HISTP:1 1 nbin=64 nsamp=65536
Probes20-484
Current Probe (IP)
Current Probe (IP)

IP
Notes
The S-Parameters describing this model are given by:
S 11 = S 22 = 0
S 12 = S 21 = 1
The above S-Parameter value simply describe a connection element. The current probe measures
the current flowing through the branch.
Netlist Form
IP:Name n1
Netlist Example
IP:my_ip 1
Probes20-485
Peak-to-Average Power Probe (PAPP)
Peak-to-Average Power Probe (PAPP)

PAPP

Ports
Notes
1. This probe calculates the peak to average power ratio of an incoming signal.
If the input signal is v ( n ) , n ∈ [ 1, N ] , then the peak-to-average power ratio is calculated as fol-
lows:
2
max ( v ( n ) )
PAP = -------------------------------
N
-
1 2
---- ∑ v ( n )
N
n=1
Netlist Form
PAPP:Name n1 [Initsamp=val] [Rin=val]
Netlist Example
PAPP:my_papp 2
Probes20-486
Probability Density Function Probe (PDFP)

PDFP
nsamp Number of samples used for None 1024 [1, Inf)/Integer

histogram

Ports
Notes
1. The Probability Density Function (PDF) probe is similar to the Histogram probe. After deter-
mining the histogram function, it is normalized by the total number of samples. The total num-
ber of input samples per bin are determined and displayed versus the x-axis, represented by the
bin locations. If the user specifies a nsamp value larger than the total number received from
the source, the actual number of samples received will be used for the calculation.
Netlist Form
PDFP:NAME n1 nbin=val nsamp=val [Initsamp=val] [Rin=val]
Probes20-487
Netlist Example
PDFP:my_pdfp 1 nbin=64 nsamp=65536
Probes20-488
Phase Noise Probe (PNP)

PNP
n1
PNP
Properties Description Units Default Range
NAME Probe name None Required String
FMIN Minimum measurement Frequency 100 [100, 1e6]/Real

frequency
WINDOW 0 for Bartlett, None 1 [0,8] /Integer

_TYPE
1 for Hanning,
2 for Rectangular,
3 for Hamming,
4 for Blackman,
5 for Blackman-Harris (3
term),
6 for Blackman-Harris (4
term)
7 for Gaussian (alpha=3),
8 for de la Valle-Poussin.

Ports
Probes20-489
Notes
1. In general, this phase noise probe (PNP) takes the noise signal from the PN pin of the VCODI-
VBYN (combined VCO and Frequency Divider component) and outputs the single side band
noise spectrum. If you plot the data with the dB operation, the units will be dBc/Hz.
2. Due to the statistical nature of the noise simulation, the number of samples need to be simu-
lated should be at least 10*fs/FMIN, where fs is the sampling rate. The more samples are sim-
ulated, the more accurate the spectrum is. If not enough samples are sent, this model may not
generate any plot, and the simulator will give a warning message saying not enough samples
after the simulation is completed.
3. Normally, RIN should be set to 1ohm when measuring phase noise.
4. This probe always assumes the input signal is the base-band phase noise signal. If you want to
measure the phase noise for a carrier signal, you need to extract the phase noise (e.g. using a
complex multiplier) first, and then feed this extracted noise signal to the probe. Also note that
you will have to remove the unwanted samples in a PLL simulation during the locking period
Netlist Form
PNP:NAME n1 [FMIN=val] [WINDOW_TYPE=val][INISTSAMP=val]
[RIN=val]
Netlist Example
PNP:1 1 FMIN=100Hz WINDOW_TYPE=1 RIN=1ohm
Probes20-490
Power Probe (PP)
Power Probe (PP)

PP
Notes
1. The S-Parameters describing this model are given by:
S11 = S22 = 0
S12 = S21 = 1
The above S-parameter values simply describe a connection element. As a result of that, the input
voltage V1 at node n1 and the output voltage V2 at n2 are equal and the current at node n1 and n2
is the same. This implies that the power measured at both nodes is the same and given by
P = Re{VI *} , where V1 = V2 = V and I 1 = I 2 = I
Netlist Form
PP:Name n1
Netlist Example
PP:My_pp 1
Probes20-491
Power Spectral Density Probe (PSDP)

PSDP
FFTL Number of input samples used for None 256 [8, Inf)/Integer
spectral estimation per invocation (must be a
power of 2)
TYPE 0 for nonperiodic signals and 1 for None 0 [0, 1]/Integer

periodic
WINDOW 0 for Bartlett, None 1 [0, 8]/Integer

_TYPE
1 for Hanning,
2 for rectangular,
3 for Hamming,
4 for Blackman,
5 for Blackman-Harris (3 term),
6 for Blackman-Harris (4 term)
7 for Gaussian (alpha=3),
8 for de la Valle-Poussin.

Ports
Probes20-492
Notes
1. For a given random input signal
this model takes blocks of the incoming input samples ( each block of length FFTL samples),
and computes the resulting power spectrum density S(ω) for each block according to
2
V in ( ω )
S ( ω ) = ---------------------
-
R in
where Vin(ω) is the frequency spectrum of the input complex envelope ( A(t)ejθ(t) ) computed
using an FFT of length FFTL, and Rin is the load impedance looking into the input port of the
PSD.
2. The resulting power spectrum is then averaged out over the total number of available input
blocks (each of length FFTL samples). The averaging process is done according to the Welch
Method [1] for spectral estimation. The averaging process becomes more accurate as more
input samples are used in the estimation process. The averaging process then yields an estimate
of the power spectral density of the random input signal.
3. The user should set the TYPE parameter to 0 if the expected spectral estimate is continuous.
Non-periodic signals always yield continuous power spectral densities. If, on the other hand,
the spectral estimate is expected to be discrete (i.e., input is periodic), the user should set the
TYPE parameter to 1.
4. It is important to note that from a software point of view, a periodic signal (e.g., a sinusoid)
will not yield a discrete spectrum unless the frequency of the periodic signal, the simulation
time step, and the number of samples representing the signal all meet a certain criterion.
Netlist Form
PSDP:Name n1 FFTL=val [TYPE=val] [WINDOW_TYPE=val][INITSAMP=val]
+ [RIN=val]
Netlist Example
PSDP:My_Psdp 1 FFTL=256 Window_type=2 TYPE=0
References
1. J. G. Proakis and D. G. Manolakis, “Introduction to Digital Signal Processing”, Macmillan
Probes20-493
Root Mean Square Probe (RMSP)

RMSP

Ports
Input Input1 signal (complex)
Notes
1. The results of this probe may be viewed only in the SWEEP/Network Function domain. They
may not be viewed in the time or spectral domain. Assuming the following input signal
,
the RMS probe takes the samples of the incoming input complex envelop signal A(t)ejθ(t) and com-
putes the root mean square by
Probes20-494
N–1 jθ ( k∆t ) 2
A(k∆t)e
V rms = ∑ ---------------------------------------
N
-
k=0
Where ∆t is the time sampling step and N is the total number of samples available to the input
port.
2. Using this element to probe an electrical node will load that node by Rin.
Netlist Form
RMSP:Name n1 [Initsamp=val] [Rin=val]
Netlist Example
RMSP:My_rmsp 1
Probes20-495
Signal to Noise & Distortion Probe (SINADP)

SINADP
INITSAMP1 Number of initial samples None 0 [0,Inf)/Integer

removed from input1
waveform
INITSAMP2 Number of initial samples None 0 [0,Inf)/Integer

removed from input2
waveform
Notes
1. This model is used to calculate the signal to noise and distortion ratio (SINAD) in a digital
communications system by computing the average power E(Vv+n (t))2 for the received input
stream with noise and distortion (Signal+Noise+Distortion) and the average E(Vv (t))2 of the
corresponding input stream without noise (Signal). The average noise power is computed as:
2
E { ( Vv + n ( t ) – Vv ( t ) ) }
The final SINAD value is computed as:
Probes20-496
(
E (Vv (t ))
2
)
(
E N (t )
2
)
Systems with a high SINAD ratio require a large number of samples be transmitted through the
system to obtain an accurate measure of SINAD.
Netlist Form
SINADP:NAME n1 n2 [Initsamp1=val] [Initsamp2=val] [Rin1=val]
[Rin2=val]
Netlist Example
SINADP:my_sinadp 1 2
Probes20-497
Signal Probe (SP)
Signal Probe (SP)

SP

Ports
Input Input signal (real, complex)
Notes
1. This probe yields the voltage of the input signal Vin(t). This voltage signal may be viewed in
the time or spectral domain.
2. For baseband signals (i.e., zero carrier frequency), this probe yields the input voltage signal in
the time domain and its spectrum in the frequency domain.
The baseband frequency domain response Vin(f) is computed at a set of discrete frequency
points according to:
N–1
V k – N 1-
---- df = --- ∑ Vin ( nts ) exp ( –j 2 π nts kdf )
 2  N
n=0
where:
k = 0, 1, 2, . . . N-1
Probes20-498
Signal Probe (SP)
ts = Input signal time step

N = The next power of 2 larger than the total number of samples available at the input port, and
1-
df = -------
Nt s
3. For passband input signals of the form V in ( t ) = A ( t ) cos ( 2πf c t + θ ( t ) ) , this probe will
yield the complex input voltage { A ( t )e j θ ( t ) } in the time domain and its spectrum in the fre-
quency domain.
4. The passband frequency domain response Vin(f) is computed at a set of discrete frequency
points according to:
N–1
N 1
V f c +  k – ---- df = ---- ∑ A ( nts ) exp { j θ ( nts ) } exp { –j 2 π nts kdf }
2 N
n=0
where:
k = 0, 1, 2, . . . N-1
ts = Input complex envelope time step
N = The next power of 2 larger than the total number of samples available at the input port.
df = 1/Nts
Netlist Form
SP:Name n1 [Initsamp=val] [Rin=val]
Netlist Example
SP:My_sp 1
Probes20-499
Voltage Probe (VP)
Voltage Probe (VP)

VP
Notes
1. This probe assumes an infinite input impedance and is therefore more suited for probing sig-
nals generated by electrical elements. The measurements obtained by this probe are similar to
those of the Signal Probe (SP). For more information on that, please refer to the SP component
in this chapter.
Netlist Form
VP:Name n1
Netlist Example
VP:My_vp 1
Probes20-500
1
Sources
Sources1-10
Additive White Gaussian Noise Source, Real
Additive White Gaussian Noise Source, Real (AWGNS)

AWGNS
o
NSAMP Number of samples None 100 [1, Inf)/Integer
Seed Random Seed None 0 [0, Inf)/Integer
Noise_Power Noise power Watt 1 [0, Inf)/Real
Sample_Rate Output bit rate in Hz Hz 1000 (0, Inf)/Integer
FC Carrier frequency in Hz 0 [0, Inf)/Real

Hz
Ports
Notes
This model generates a real additive white Gaussian noise signal. The output voltage is given by
V out ( t ) = A ( t ) cos ( 2 π f c t )
Where A(t) is a random white Gaussian processes with a standard deviation given by
σ = 4 × Rout × NoisePower for envelope analysis
Sources1-11
Additive White Gaussian Noise Source, Real
or
σ = 8 × Rout × NoisePower for instantaneous analysis
Netlist Form
AWGNS:Name n1 NSAMP=val [SEED=val] Noise_Power=val
+ Sample_Rate=val [FC=val] [ROUT=val]
Netlist Example
AWGNS:1 1 nsamp=1024 seed=10 Noise_Power=10dbm
+ Sample_Rate=200KHz
Sources1-12
Periodic Binary Bit Generator (BGEN)

BGEN
o
BIT_PATTERN Pattern of bits to None 0101 String

generate during each
period in binary
format
PERIOD Period of the None 1 (0, Inf)/Integer

generated binary
sequence
NB Total number of None 100 (0, Inf)/Real

binary bits to generate
BR Bit rate of the Hz 1000 (0, Inf)/Real

generated binary
sequence
T True output value Volt 1 (-Inf, Inf)/Real
F False output value Volt 0 (-Inf, Inf)/Real
Ports
Output Output signal consisting of a periodic binary sequence (real)
Sources1-13
Notes
This model generates a periodic binary sequence of T's and F's with a BR bit rate . The period of
this bit sequence is given by PERIOD and the bits generated during each period are specified by
BIT_PATTERN in binary format. For example, if BIT_PATTERN is set to 1010 and PERIOD is
set to 4, then output sequence will be FTFTFTFT..... Note that the pattern always starts with the
least significant bit of BIT_PATTERN. It is common that the parameters T and F are set to the
default values of 1 and 0 respectively. In this case, this model outputs a binary sequence.
Netlist Form
BGEN:Name n1 NB=val BIT_PATTERN=val PERIOD=val BR=val
+ [Rout=Val]
Netlist Example
BGEN:1 1 NB=200 BIT_PATTERN=10 PERIOD=4 BR=2KHZ
Sources1-14
Pseudo Random Binary Source (BSRC)
Pseudo Random Binary Source (BSRC)

BSRC
NB Total number of binary None 100 (0, Inf)/Real

bits to generate
BR Bit rate of the generated Hz 1000 (0, Inf)/Real

binary sequence
Ports
Output Output signal (integer)
Notes
This model generates NB random binary bits (0's and 1's) with equal probability. The output bit rate
is specified by BR.
Netlist Form
BSRC:Name n1 NB=val BR=val SEED=val [Rout=Val]
Netlist Example
BSRC:1 1 NB=200 BR=100KHZ SEED=57824
Sources1-15
Additive White Gaussian Noise Source, Complex
Additive White Gaussian Noise Source, Complex (CAWGNS)

CAWGNS
Seed Random Seed None 0 [0, Inf)/Integer
Noise_Power Noise power Watt 1 [0, Inf)/Real
Sample_Rate Output bit rate in Hz Hz 1000 (0, Inf)/Integer
FC Carrier frequency in Hz Hz 0 [0, Inf)/Real
Ports
Notes
This model generates a complex additive white Gaussian noise signal. The output voltage is given
by
V out ( t ) = A ( t ) cos ( 2 π f c t ) – B ( t ) sin ( 2 π f c t )
Where A(t) and B(t) are independent random white Gaussian processes each with a standard devia-
tion given by
Sources1-16
Additive White Gaussian Noise Source, Complex
σ = 2 × Rout × NoisePower for envelope analysis
or
σ = 4 × Rout × NoisePower for instantaneous analysis
Netlist Form
CAWGNS:Name n1 NSAMP=val [SEED=val] Noise_Power=val
+ Sample_Rate=val [FC=val] [ROUT=val]
Netlist Example
CAWGNS:1 1 nsamp=1024 seed=10 Noise_Power=10dbm
+ Sample_Rate=200KHz
Sources1-17
Constant Source Complex (CCONST)

CCONST
REAL_CONST Real part Volt 1 (-Inf, Inf)/Real
IMAG_CONST Imaginary part Volt 1 (-Inf, Inf)/Real
NSAMP Number of samples None 100 (0, Inf)/Integer

to output
SAMPLE_RATE Output sample rate Hz 1000 (0, Inf)/Real
Ports
Notes
1. This model outputs a stream of complex samples, each of value REAL_CONST + jIMAG_CONST
for a total of NSAMP samples The sampling rate of the output signal is SAMPLE_RATE Hz.
Netlist Form
CCONST:Name n1 REAL_CONST=val IMAG_CONST=val NSAMP=val
+ SAMPLE_RATE=val [Rout=Val]
Netlist Example
CCONST:1 1 REAL_CONST=1V IMAG_CONST=1V NSAMP=100
Sources1-18
+ SAMPLE_RATE=1KHZ
Sources1-19
Data File Source, Complex (CFILESRC)

CFILESRC
NSAMP Number of samples to None 100 (0, Inf)/Integer

read from external file
SAMPLE_RATE Rate at which samples Hz 1000 (0, Inf)/Real

output from source file
FILE Name of the external None <Filename> String

file
Ports
Notes
This model reads complex type data from an external file and outputs it at a rate equals to
SAMP_RATE. The file should simply contain the ascii data to be read out. The data should be
stored on a sample by sample basis the sample’s real value followed by its imaginary value. If the
file contains fewer than NSAMP data points, then the data in the file is read in a periodic fashion
until NSAMP samples are output.
Sources1-20
Netlist Form
CFILESRC:Name n1 NSAMP=val SAMPLE_RATE=val File= val
+[Rout=Val]
Netlist Example
CFILESRC:1 1 NSAMP=1000 SAMPLE_RATE=3.5MHZ
Sources1-21
Digital Clock (DCLK)

DCLK
Period Clock time period, Sec 1 (0, Inf)/Real

in time units
Delay Clock delay from Sec 0 [0, Inf)/Real

time zero, in time
units
Duty Clock duty cycle None 0.5 [0, 1]/Real
Sample_Rate Sample rate Hz 0 (0, Inf)/Real
Phase Output phase shift Deg 0 (-Inf, Inf)/Real
Ports
Output The output clock signal (real)
Notes
1. The output amplitude of the clock signal is either 0V or 1V. In the time interval 0 ≤ t < Delay,
the output is 0V and at time t=Delay, the clock is at 1V. For time t ≥ Delay, the output oscil-
Sources1-22
lates with the specified period and duty values.

Netlist Form
DCLK:Name n1 PERIOD=val DELAY=val DUTY=val NSAMP=val
+ SAMPLE_RATE=val [Phase=val] [Rout=Val]
Netlist Example
DCLK:1 5 PERIOD=1us DELAY=3us DUTY=0.5 NSAMP=200
+ SAMPLE_RATE=2KHZ Phase=45
Sources1-23
Impulse Waveform Generator (IMPULSE)

IMPULSE
Property Description Unit Default Range/Type
NSAMP Number of samples of None 100 [1,INF)/Integer

the output waveform
SAMPLE_RATE Output sample rate Hz 1000 (0,INF)/Real
A Amplitude of impulse Volt 1 (-INF,INF)/Real

waveform
D Number of delay None 20 [0,INF)/Integer

samples
Ports
Notes
This model generates an impulse signal with amplitude A and delay D.
Netlist Form
IMPULSE:Name n1 NSAMP=val Sample_Rate=val A=val D=val
+ [ROUT=val]
Sources1-24
Netlist Example
IMPULSE:1 1 nsamp=1024 Sample_Rate=200KHz A=1 D=20
Sources1-25
One Port Oscillator (OSC)

OSC
SAMPLE_RATE Output sample rate MHz 102.4 (0, Inf)/Real
PLO Average Power at Watt 0.01 [0, Inf)/Real

oscillator output
FLO Center frequency MHz 1 [0, Inf)/Real
NOISEON Noise: 1 for On, 0 for None 1 [0, 1]/Integer

Off
F1 Frequency offset from Hz 0 (0, Inf)/Real

FLO, region 1
F2 Frequency offset from Hz 0 (0, Inf)/Real

FLO, region 2
M2 Phase noise magnitude dB -180 (-Inf, 0]/Real

at F2 (i.e. phase noise
floor) in dB
TYPE 0: Low loaded Q None 0 [0, 1]/Integer

1: High loaded Q
Sources1-26
PHASE Output Phase Shift Deg 0 (-Inf, Inf)/Real
SEED Random seed used for None 0 [0, Inf)/Integer

phase noise generation
Wavetype Output waveform type None 0 [0, 1]/Integer

0: Sinusoid
1: Sawtooth
Ports
Notes
1. All phase noise data must be provided if output is to include phase noise effects
2. In general, the output voltage of this model is given by:
V out ( t ) = A cos ( 2 π f c t + PHASE + θ n ( t ) )
where
A = 4 R out P LO for envelope analysis

or
A = 8 R out P LO for instantaneous analysis

and θn(t) is the random phase noise component at time t. This phase noise component will only
be nonzero if the NOISEON parameter is set to 1, otherwise, the oscillator will be assumed
noiseless.
The power spectral density of the random phase noise processes is given by the Leeson’s
model [1]
2
 f lo f 
-  1 + ----c- • FkT
L ( f m ) = 10 log  1 + --------------------------- ---------- ( dB )
2  f m 2 p lo 
 ( 2 f m q load )
where fc is the flicker noise frequency and qload is the loaded Q. The noise floor M2 is simply:
Sources1-27
M 2 = FkT
----------
2 p lo
3. The frequency offsets F1 and F2 must be consistent with the specified oscillator TYPE as
shown in the phase noise plots below. For a low qload, F1 and F2 correspond to fc and flo/
2qload respectively while for a high qload, F1 and F2 correspond to flo/2qload and fc respec-
tively.
4. A random phase noise process is generated by filtering a white Gaussian random sequence
through a filter with a frequency response H(fm), where
H ( fm ) = L ( fm )
This frequency response is decomposed into three regions: near-carrier region (fm ≤ F1), far-
carrier region (F1 < fm < F2) and the White noise region (fm ≥ F2). Regions one and two are
represented in the frequency domain using 8192 frequency points each. Region one will typi-
cally use a much smaller frequency resolution than region 2. Region 3 is simply modeled as an
additive white Gaussian process. The total random phase noise process is simply the sum of
the contributions from each region.
Since in general the sampling frequency of the generated phase noise process is less than the
actual output sampling frequency FS, linear interpolation is applied in the time domain on the
generated phase noise process θn(t) to ensure it has the same sampling rate as that of the output
signal.
Netlist Form
OSC:Name n1 FLO=val PLO=val NSAMP=val SAMPLE_RATE=val
+ [PHASE=val] [F1=val] [F2=val] [FDEV=val] [M2=val] [TYPE=val]
Sources1-28
+ [SEED=val] [Wavetype=val] [Rout=val]
Netlist Example
OSC:1 1 FLO=800MHZ PLO=10dbm NSAMP=1000 SAMPLE_RATE=1MHZ
+ PHASE=90 F1=150Hz F2=10KHz FDEV=100KHz M2=-180dB TYPE=0
References
1. Ulrich L. Rohde, J. Whitaker, and T.T.N. Bucher, “Communications Receivers” McGraw-Hill,
1996.
Sources1-29
Periodic Binary Bits Generator, Waveform Output
Periodic Binary Bits Generator, Waveform Output (PBGEN)

PBGEN
Bit_Pattern Pattern of bits to None 0101 String

period in binary
format
Period Period of the None 1 (0, Inf)/Integer

generaged binary
sequence
NB Total number of None 100 (0, Inf)/Integer


generated binary
sequence
T True output value Volt 1 (-Inf,Inf)/Real
F False output value Volt 0 (-Inf,Inf)/Real
V0 Initial value Volt 0 (-Inf,Inf)/Real
TS Sampling time Sec 1e-6 (0,Inf)/Real
TR Rise time Sec 0 [0,Inf)/Real
Sources1-30
Periodic Binary Bits Generator, Waveform Output
FTF Fall time Sec 0 [0,Inf)/Real
Ports
Notes
This model outputs a periodic waveform defined by the user specified parameters.
This generated output waveform is a periodic binary waveform of T's and F's with a BR bit rate and
a TS sampling period. The period of this bit sequence, in bits, is given by PERIOD and the bits gen-
erated during each period are specified by BIT_PATTERN in binary format. For example, if
BIT_PATTERFN = 1010, PERIOD = 4 bits, BR = 10 bits/sec, TS = 50 ms, then output sequence
will be (in samples) FFTTFFTTFFTTFFTTFF..... Note that the resulting number of samples per bit
in this case is 2 = 1/(TS*BR). Also note that the pattern always starts with the least significant bit of
BIT_PATTERN. It is common that the parameters T and F are set to the default values of 1 and 0
respectively. In this case, this model outputs a binary sequence.
Netlist Form
PBGEN:NAME n1 n2 Bit_Pattern=val Period=val [NB=val] [BR=val] [T=val] [F=val] [V0=val]
[TS=val] [TR=val] [TF=val] [Rout1=val] [Rout2=val]
Netlist Example
PBGEN:1 1 2 Bit_Pattern=10 Period=6 NB=1024
Sources1-31
Periodic Binary Bits Generator, Differential
Periodic Binary Bits Generator, Differential Waveform Outputs

(PBGEND)
PBGEND
Bit_Pattern Pattern of bits to None 0101 String

period in binary format
Period Period of the generaged None 1 (0, Inf)/Integer

binary sequence in bits
NB Total number of binary None 100 (0, Inf)/Integer

bits to generate
BR Bit rate of the generated Hz 1000 (0, Inf)/Real

binary sequence
T True output value Volt 1 (-Inf,Inf)/Real
F False output value Volt 0 (-Inf,Inf)/Real
V0 Initial value Volt 0 (-Inf,Inf)/Real
TS Sampling time Sec 1e-6 (0,Inf)/Real
TR Rise time Sec 0 [0,Inf)/Real
Sources1-32
Periodic Binary Bits Generator, Differential
TF Fall time Sec 0 [0,Inf)/Real
Rout1 Output1 impedance Ohm 0 [0,Inf)/Real
Rout2 Output2 impedance Ohm 0 [0,Inf)/Real
Ports
Notes
This model outputs a periodic binary waveform to the first output defined by the user specified
parameters. The second output is simply the negative of the first output.
This generated “positive” output waveform is a periodic binary waveform of T's and F's with a BR
bit rate and a TS sampling period. The period of this bit sequence, in bits, is given by PERIOD and
the bits generated during each period are specified by BIT_PATTERN in binary format. For exam-
ple, if BIT_PATTERFN = 1010, PERIOD = 4 bits, BR = 10 bits/sec, TS = 50 ms, then output
sequence will be (in samples) FFTTFFTTFFTTFFTTFF..... Note that the resulting number of sam-
ples per bit in this case is 2 = 1/(TS*BR). Also note that the pattern always starts with the least sig-
nificant bit of BIT_PATTERN. It is common that the parameters T and F are set to the default
values of 1 and 0 respectively. In this case, this model outputs a binary sequence.
Netlist Form
PBGEND:NAME n1 n2 Bit_Pattern=val Period=val [NB=val] [BR=val] [T=val] [F=val] [V0=val]
[TS=val] [TR=val] [TF=val] [Rout1=val] [Rout2=val]
Netlist Example
PBGEND:1 1 2 Bit_Pattern=10 Period=6 NB=1024
Sources1-33
Pseudo Random Binary Source (PRBS)

PRBS
PRBS n1
NB Total number of Sec 100 [1, Inf)/Integer


generated binary
sequence in Hz
V0 Initial value Volt 0 (-Inf, Inf)/Real
TS Sampling time Sec 1e-006 (0, Inf)/Real
TR Rise time Sec 0 [0, Inf)/Real
TF Fall time Sec 0 [0, Inf)/Real
SEED Random seed None 0 [0, Inf)/Real
Ports
Sources1-34
Notes
This model generates the Pseudo Random Binary signal, and output it as a waveform according to
the specified parameters.
Netlist Form
PRBS:Name n1 NB=val BR=val TS=val [T=val] [F=val] [V0=val]
[TR=val] [TF=val] [SEED=val] [Rout=val]
Netlist Example
PRBS:1 1 NB=100 BR=1000 TS=1e-6
Sources1-35
Pseudo Random Binary Source:Differential
Pseudo Random Binary Source:Differential Waveform Outputs

(PRBSD)
PRBSD
NB Total number of Sec 100 [1, Inf)/Integer


generated binary
sequence in Hz
V0 Initial value Volt 0 (-Inf, Inf)/Real
TS Sampling time Sec 1e-006s (0, Inf)/Real
TR Rise time Sec 0 [0, Inf)/Real
TF Fall time Sec 0 [0, Inf)/Real
SEED Random seed None 0 [0, Inf)/Real
Sources1-36
Pseudo Random Binary Source:Differential
Ports
Notes
This model generates the Pseudo Random Binary signal, and output it as a waveform according to
the specified parameters to the first output. The signal at the second output is simply the negative of
the first output.
Netlist Form
PRBSD:Name n1 NB=val BR=val TS=val [T=val] [F=val] [V0=val]
[TR=val] [TF=val] [SEED=val] [Rout1=val] [Rout2=val]
Netlist Example
PRBSD:1 1 NB=100 BR=1000 TS=1e-6
Sources1-37
Periodic Pulse Waveform Generator (PULSE)

PULSE

of the output
waveform
PERIOD Time period of Sec 0.01s (0, Inf)/Real

pulse
A Amplitude of pulse Volt 1 (-Inf, Inf)/Real
DUTY Duty cycle None 0.5 [0, 1]/Real
T1 Pulse rise time Sec 0 [0, Inf)/Real
T2 Pulse fall time Sec 0 [0, Inf)/Real
Ports
Sources1-38
Notes
This model generates a periodic pulse voltage waveform, as follows:
T1 T2
Period Duration
NSAMP
DURATION = -------------------------------
SampleRate
T = PERIOD • DUTY
Netlist Form
PULSE:Name n1 NSAMP=val SAMPLE_RATE=val PERIOD=val A=val
DUTY=val [T1=val] [T2=val] [Rout=Val]
Netlist Example
PULSE 1 NSAMP=1000 SAMPLE_RATE=100KHZ
+ PERIOD=10mS A=1V DUTY=0.3
Sources1-39
Piecewise Linear Source (PWL)

PWL
T1....Tn Time instance Sec 0 [0, Inf)/Real
V1....Vn Voltage at corresponding Volt 0 [0, Inf)/Real

time instance
File File name None Optional String
NSAMP Number of samples of the None 100 (0, Inf)/Real

output waveform
Ports
Notes
1. This model outputs a piece wise linear waveform. The waveform is defined by either the
parameters T and V, or by the external file. The external file should be text file with only two
columns of data, the first column being time points and the second column being voltage
points. Note that the external file is predominant over the parameters T and V when both are
specified.
2. Linefeeds are optional in external files, which means that:
Sources1-40
#sv
00
10
21
31
4 1 5 1 6 2 7 2 8 0 9 0 10 1
will be parsed the same as:
00
10
21
31
41
51
62
72
80
90
10 1
Netlist Form
PWL:Name n1 [T1...Tn=val] [V1...Vn=val] [File=val] NSAMP=val
SAMPLE_RATE=val [Rout=Val]
Netlist Example
PWL:1 1 NSAMP=1000 SAMPLE_RATE=100KHZ T1=1s T2=2s T3=4s V1=1v
V2=5.2v V3=1.3v
PWL:1 1 NSAMP=1000 SAMPLE_RATE=100KHZ FILE=”pwl.txt”
Sources1-41
Constant Source, Real (RCONST)
Constant Source, Real (RCONST)

RCONST
CONSTANT Constant value Volt 1 (-Inf, Inf)/Real
NSAMP Number of Samples None 100 (0, Inf)/Integer
Ports
Notes
This model outputs a stream of real samples, each of value CONSTANT (for a total of NSAMP
samples). The sampling rate of the output signal is SAMPLE_RATE Hz.
Netlist Form
RCONST:Name n1 Constant=val NSAMP=val Sample_Rate=val
[Rout=Val]
Netlist Example
RCONST:1 1 Constant=1V NSAMP=100 Sample_Rate=1KHZ
Sources1-42
Data File Source, Real (RFILESRC)

RFILESRC

to read from
external file
SAMPLE_RATE Rate at which Hz 1000 (0, Inf)/Real

samples output
from source file
File Name of the None <Filename> String

external data file
Ports
Notes
This model reads real type data from an external file and outputs it at a rate equals to
SAMPLE_RATE. The file should have no header information, it should simply contain the ascii
data to be read out. If the file contains fewer than NSAMP data points, then the data in the file is
read in a periodic fashion until NSAMP samples are output.
Netlist Form
RFILESRC:Name n1 NSAMP=val SAMPLE_RATE=val FILE=val
+[Rout=val]
Sources1-43
Netlist Example
RFILESRC:1 1 NSAMP=1000 SAMPLE_RATE=3.5MHZ FILE=”data.txt”
Sources1-44
Periodic Sawtooth Waveform Generator
Periodic Sawtooth Waveform Generator (SAWTOOTH)

SAWTOOTH

of the output
waveform
PERIOD Time period of Sec 0.01 [0, Inf)/Real

sawtooth
A Amplitude of Volt 1 (0,Inf)/Real

sawtooth
Ports
Output Output of voltage waveform generator (real)
Notes
This model generates a periodic sawtooth voltage waveform with a total duration calculated by:
NSAMP
Duration = -------------------------------
SampleRate
Sources1-45
Periodic Sawtooth Waveform Generator
Netlist Form
SAWTOOTH:Name n1 NSAMP=val SAMPLE_RATE=val PERIOD=val A=val
[Rout=Val]
Netlist Example
SAWTOOTH:1 1 NSAMP=1000 SAMPLE_RATE=100KHZ PERIOD=10mS A=1V
Sources1-46
Sine Wave (SIN)
Sine Wave (SIN)

SIN
SAMPLE_RATE Output sample rate MHz 102.4 (0, Inf)/Real
F Output frequency MHz 1 [0, Inf)/Real
AMPLITUDE Amplitude Volt 1 (-Inf, Inf)/Real
OFFSET Voltage offset Volt 0 (-Inf, Inf)/Real
PHASE Output Phase Shift Deg 0 (-Inf, Inf)/Real
Ports
Notes
The output voltage of this model is given by:
V out ( t ) = ASin ( 2 π ft + PHASE ) + OFFSET
Sources1-47
Sine Wave (SIN)
where A is the amplitude. Note that the sampling rate must be at least twice larger than the fre-
quency of the sinusoid.
Netlist Form
SIN:Name n1 [NSAMP=val] [SAMPLE_RATE=val][F=val]
[AMPLITUDE=val] [OFFSET=val] [PHASE=val] [Rout=val]
Netlist Example
SIN:1 n1 NSAMP=2048 SAMPLE_RATE=10MHz F=1MHz AMPLITUDE=2v
OFFSET=0.5v PHASE=45
Sources1-48
Periodic Square Waveform Generator (SQRSRC)

SQRSRC

of the output
waveform

square
A Amplitude of Volt 1V (0,Inf)/Real

square
Ports
Sources1-49
Notes
1. This model generates a periodic square voltage waveform with a total duration calculated by:
NSAMP
DURATION = -------------------------------
SampleRate
Netlist Form
SQRSRC:Name n1 NSAMP=val SAMPLE_RATE=val PERIOD=val A=val
[Rout=Val]
Netlist Example
SQRSRC:1 1 NSAMP=1000 SAMPLE_RATE=100KHZ PERIOD=10mS A=1V
Sources1-50
Step Waveform Generator (STEPGEN)

STEPGEN
NSAMP Total number of None 100 [1,INF)/Integer

sample of the
output waveform
SAMPLE_RATE Output sample rate Hz 1000 (0,INF)/Real
A Amplitude of step Volt 1 (-INF,INF)/Real

waveform
NSAMP_A Number of samples None 20 [0,INF)/Integer

with amplitude A
Ports
Notes
This model generates a step signal. The first NSAMP_A samples are of amplitude A, while the rest
of the samples are of 0 value.
Netlist Form
STEPGEN:Name n1 NSAMP=val Sample_Rate=val A=val NSMAP_A=val [ROUT=val]
Sources1-51
Netlist Example
STEPGEN:1 1 nsamp=1024 Sample_Rate=200KHz A=1 NSAMP_A=20
Sources1-52
Periodic Step Waveform Generator (STEPSRC)

STEPSRC

of the output
waveform
PERIOD Time period of step Sec 0.01 [0, Inf)/Real
A Amplitude of step Volt 1v (0,Inf)/Real
T1 Start time of step Sec 0s [0, Inf)/Real
T2 Stop time of step Sec 1s [0, Inf)/Real
Ports
Sources1-53
Notes
1. This model generates a periodic step voltage waveform, as follows:
A T1 T2
Period
Duration
NSAMP
DURATION = -------------------------------
SampleRate
Netlist Form
STEPSRC:Name n1 NSAMP=val SAMPLE_RATE=val PERIOD=val A=val
+ T1=val T2=val [Rout=Val]
Netlist Example
STEPSRC:1 NSAMP=1000 SAMPLE_RATE=100KHZ PERIOD=10mS A=1V T1=5mS
+ T2=8mS
Sources1-54
Periodic Triangle Waveform Generator (TRIANGLE)

TRIANGLE

of the output
waveform

triangle
A Amplitude of Volt 1 (0,Inf)/Real

triangle
Ports
Notes
This model generates a periodic triangle voltage waveform, with a total duration calculated by:
NSAMP
Duration = -------------------------------
SampleRate
Sources1-55
Netlist Form
TRIANGLE:Name n1 NSAMP=val SAMPLE_RATE=val PERIOD=val A=val
+ [Rout=Val]
Netlist Example
TRIANGLE:1 1 NSAMP=1000 SAMPLE_RATE=100KHZ PERIOD=10mS A=1V
Sources1-56
Data File Source, Digital (WINIQSIMSRC)

WINIQSIMSRC
FILE Name of the ibn file None <Filename> String

to read from the .ibn
file
Ports
Notes
1. This model reads I-Q data from a user specified WINIQSIM generated .ibn file and sends them
to the output.
Netlist Form
WINIQSIMSRC:Name n1 n2 file=val NSAMP=val [Rout1=val]
+ [Rout2=val]
Sources1-57
Netlist Example
WINIQSIMSRC:1 1 2 file=”gsm.ibn” NSAMP=128
Sources1-58
2
Vector
Vector2-59
Merge Two Buses (BUSMERGE)

BUSMERGE
Ports
Input1 First input signal (complex vector)
Input2 Second imput signal (complex vector)
Output Output signal (complex vector)
Notes
This model merges two buses (or vectors). Suppose the first bus input has a width W1 and the sec-
ond bus input has a width W2, then the output bus has a width W1 + W2. The first W1 entries of the
output bus comes from the first bus, the next W2 entries comes from the second bus.
Netlist Form
BUSMERGE:NAME n1 n2 n3 [Rin1=val] [Rin2=val] [Rout=val]
Vector2-60
Netlist Example
BUSMERGE:1 1 2 3
Vector2-61
Convert Width-M Input Bus to Width-N Output Bus
Convert Width-M Input Bus to Width-N Output Bus (BUSSPLIT)

BUSSPLIT
Start Start index None 0 [0, 2048]/Integer
Stop Stop index None 1023 [0, 2048]/Integer
Ports
Input Input signal (complex vector)
Notes
This model takes a bus and outputs another bus. The output bus is formed by picking the entries of
the input bus starting at index “start” and stopping at index “stop”. The indices must be in the range
of the width of the input bus signal.
Netlist Form
BUSSPLIT:NAME n1 n2 start=val stop=val [Rin=val] [Rout=val]
Netlist Example
BUSSPLIT:1 1 2 start = 0 stop = 1023
Vector2-62
Complex Vector to Real Vector Converter (CVTORV)
Complex Vector to Real Vector Converter (CVTORV)

CVTORV
IORQ in-phase (1) None 1 [0, 1]/Integer

Quadrature (0)
Ports
Output Output signal (real vector)
Notes
The output real vector will take the real part of the complex vector of the input signal if IORQ=1;
otherwise, if IORQ=0, the output vector will take the imaginary part of the complex vector of the
input signal.
Netlist Form
CVTORV:NAME n1 n2 [IORQ=val] [Rin=val] [Rout=val]
Netlist Example
CVTORV:1 1 2 IORQ = 1
Vector2-63
Parallel to Serial Converter (PTOSCONV)
Parallel to Serial Converter (PTOSCONV)

PTOSCONV
Width Width used to None 8 [0, 2048]/Integer

convert from
parallel to serial
Ports
Notes
This model converts the complex vector signal from parallel to serial. Suppose the width of the
input vector is “w”, the parameter “width” determines the how many entries in the vector are sent
to the output. If “width” is greater than “w”, every entry in the input vector will be sent to the out-
put port. The output signal has a sampling rate of input sampling rate times outWidth, where out-
Width is minimum of “w” and “width”.
Netlist Form
PTOSCONV:NAME n1 n2 [width=val] [Rin=val] [Rout=val]
Netlist Example
PTOSCONV:1 1 2 width = 8
Vector2-64
Real Vector to Complex Vector Converter (RVTOCV)
Real Vector to Complex Vector Converter (RVTOCV)

RVTOCV
IORQ in-phase (1) None 1 [0, 1]/Integer

quadrature(0)
Ports
Input Input signal (real vector)
Notes
The output complex vector will take the input signal as the real part if IORQ=1; otherwise, if
IORQ=0, the output vector will take the input signal as the imaginary part.
Netlist Form
RVTOCV:NAME n1 n2 [IORQ=val] [Rin=val] [Rout=val]
Example
RVTOCV:1 1 2 IORQ = 1
Vector2-65
Serial to Parallel Converter (STOPCONV)
Serial to Parallel Converter (STOPCONV)

STOPCONV
Width Width of the output None 8 [1, 2048]/Integer

vector
Ports
Notes
This model converts a serial input signal to a parallel output signal (a vector). It takes “width” sam-
ples from the input signal to form one output vector sample. The output signal sampling rate is 1/
width of the input sampling rate.
Netlist Form
STOPCONV:NAME n1 n2 width=val [Rin=val] [Rout=val]
Netlist Example
STOPCONV:1 1 2 width = 16
Vector2-66
Add Two Complex Vector Signals (VADD)

VADD
Ports
Input1 Input1 signal (complex vector)
Notes
This model adds two vector signals. Note that the two input vector signals must have same width.
Netlist Form
VADD:NAME n1 n2 n3 [Rin1=val] [Rin2=val] [Rout=val]
Vector2-67
Netlist Example
VADD:1 1 2 3
Vector2-68
Vector Fast Fourier Transform (VFFT)
Vector Fast Fourier Transform (VFFT)

VFFT
Fftl Fourier transform None 1024 [1, Inf)/integer

length
Ports
Notes
This model performs FFT on the incoming vector signal. If the width of the input vector signal is
smaller than “fftl”, zeros are padded. If “fftl” is not a power of 2, it will be modified to the next
power of 2.
Netlist Form
VFFT:NAME n1 n2 fftl=val [Rin=val] [Rout=val]
Netlist Example
VFFT:1 1 2 fftl = 256
Vector2-69
Vector Inverse Fast Fourier Transform (VIFFT)
Vector Inverse Fast Fourier Transform (VIFFT)

VIFFT
Fftl Fourier transform None 1024 [1, Inf)/integer

length
Ports
Notes
This model performs IFFT on the incoming vector signal. If the width of the input vector signal is
smaller than “fftl”, zeros are padded. If “fftl” is not a power of 2, it will modified to the next power
of 2.
Netlist Form
VIFFT:NAME n1 n2 fftl=val [Rin=val] [Rout=val]
Netlist Example
VIFFT:1 1 2 fftl = 256
Vector2-70
Scale a Complex Vector Signal (VSCALE)
Scale a Complex Vector Signal (VSCALE)

VSCALE
Gain Magnitude of the None 1 [0, Inf)/Real

voltage gain
Phase Phase of the Deg 0 [-180, +180]/Real

voltage gain
Ports
Output Input signal (complex vector)
Notes
This model scales the input vector signal by a factor determined
by the two parameters gain and phase.
Netlist Form
VSCALE:NAME n1 n2 Gain=val Phase=val [Rin=val] [Rout=val]
Netlist Example
VSCALE:1 1 2 Gain=2 Phase = 45
Vector2-71
Subtract Two Complex Vector Signals (VSUB)

VSUB
Ports
Notes
This model subtracts two vector signals. Note that the two input vector signals must have same
width.
Vector2-72
Netlist Form
VSUB:NAME n1 n2 n3 [Rin1=val] [Rin2=val] [Rout=val]
Netlist Example
VSUB:1 1 2 3
Vector2-73
3
WCDMA Multi-Antenna
WCDMA Multi-Antenna3-74
Multipath Nonfading Channel for Linear Antenna
Multipath Nonfading Channel for Linear Antenna Array (MNCHLAA)

MNCHLAA
J Number of antennas None 2 [1, 16]/Integer
C Antenna array Meter 0.1 (0, Inf)/Real

spacing

(samples)
GAIN1 Magnitude of the None 1 [0, Inf)/Real

complex gain factor
for first path
PHASE1 Phase of the complex Deg 0 [-180, 180)/Real

gain factor for first
path
A1 DOA of first path Deg 0 [-180, 180)/Real
D2~D12 Delay of nth path None 0 [0, Inf)/Integer

(samples)
GAIN2 Magnitude of the None 0 [0, Inf)/Real

~GAIN12 complex gain factor
of all other paths
PHASE2 Phase of the complex Deg 0 [-180, 180)/Real

~PHASE12 gain factor for all
other paths
A2~A12 DOA of all other Deg 0 [-180, 180)/Real

paths
Ports
Output Multipath nonfading signal, in complex envelope format, for all

antennas (complex)
Notes
1. This model can be used to simulate a Multipath Nonfading Channel and then generate the sig-
nal at each antenna when Linear Antenna Array is used in the receiver.
lope representation, the channel gain factor is specified by:
L−1
h (t ) = ∑ Gaini e j Phasei δ (t − τ i )
i =0 (1 ≤ L ≤ 12) (1)
where L is the number of paths, Gain and Phase are magnitude and phase of the complex gain
for the ith path, τi => 0 is the channel delay which can be expressed by Di samples.
3. The above does not consider linear antenna array. A uniformly spaced linear antenna array
with J elements[1][2] is considered, as shown in Fig.1.
Signal
}C Antenna 2
Antenna 1
θi
Antenna n
Antenna J
Fig. 1 Block diagram of Linear Antenna Array
Assuming a signal with wavelength λ arrives at the linear antenna array from a direction,
which is called direction of arrival (DOA) θi, and taking the first element in the array as phase
reference, the relative phase shift of the received signal at the nth element can be expressed as
2πC (n − 1)
ψ i ,n = sin θ i
λ (2)
where C is the array spacing. The vector channel impulse response for the J elements can be
expressed as
L−1
h (t ) = ∑ Gaini e j Phasei β (θ i )δ (t − τ i )
i =0 (1 ≤ L ≤ 12) (3)
where β(θi)s the array response vector, which is given by
β (θ i ) = e [ jψ i ,1
e
jψ i , 2
… e ]
jψ i , J T
(4)
T
where [ ] denotes the matrix transpose.
4. Note that J samples are outputted successively for each input sample.
Netlist Form
MNCHLAA:NAME n1 n2 L=val J=val C=val D1=val Gain1=val
Phase1=val A1=val + [D2=val . . . A12=val] [RIN=val]
[ROUT=val]
Netlist Example
MNCHLAA:1 1 2 L=2 J =2 C = 0.17 D1 = 0 Gain1 = 1.0 Phase1 =
0DEG A1 = 0DEG D2 = 150 + Gain2 = 0.1 Phase2 = 0DEG A2 = 10DEG
References
1. S. C. Swales, M. A. Beach, et al, “The performance enhancement of multibeam adaptive base-
station antennas for cellular land mobile radio systems,” IEEE Trans. Veh. Technol., vol. 39,
pp. 56–67, Feb. 1990.
2. S. Tanaka, A. Harada, et al, “Experiments on coherent adaptive antenna array diversity
for wideband DS-CDMA mobile radio,” IEEE Journal on Selected Areas in Communica-
tions, vol. 18, No.8, pp.1495-1504, Aug. 2000.
Multipath Rayleigh Fading Channel for Linear
Multipath Rayleigh Fading Channel for Linear Antenna Array

(MRFCHLAA)
MRFCHLAA
J Number of antennas None 2 [1, 16]/Integer
VM Mobile velocity in None 12 [0, Inf)/Real

km/h
C Antenna array Meter 0.15 (0, Inf)/Real

spacing
SEED Random seed None 0 (0, Inf)/Real

(samples)
P1 Relative power of dB -1e+020 (-Inf, 0]/Real

first path in dB
A1 DOA of first path Deg 0 [-180, 180)/Real
D2~D12 Delay of nth path None 0 [0, Inf)/Integer

(samples)
P2~P12 Relative power of all dB -1e+020 (-Inf, 0]/Real

other paths in dB
A2~A12 DOA of all other Deg 0 [-180, 180)/Real

paths
Ports
Output Multipath Rayleigh fading signal, in complex envelope format, for

all antennas (complex)
Notes
1. This model can be used to simulate a Multipath Rayleigh Fading Channel and then generate
the signal at each antenna when Linear Antenna Array is used in the receiver.
2. The Doppler power spectrum for Multipath Rayleigh Fading Channel is given by [1][2]:
−1 2
 3b   f − f c 2 
 1 −    f − fc < fm
S Ez ( f ) =  ω m   f m  

 0 others
(1)
where b is the average received power, fm = ωm/2π is the maximum Doppler shift given by Vm/
λ where Vm is mobile velocity and λ is the wavelength of the transmitted signal at frequency
fc.
lope representation, the channel impulse response can be expressed as
L−1
h (t ) = ∑ α i (t )e jϕi ( t )δ (t − τ i )
i =0 (1 ≤ L ≤ 12) (2)
where L is the number of paths, the amplitude αi(t) for the ith path is Rayleigh distributed ran-
dom variable, the phase shift φ(t) is uniformly distributed, τi =>0 is the channel delay.
Since the Rayleigh fading process αi(t)ejφi(t) is complex, the in-phase process and quadrature
process for each path are implemented separately, as shown in Fig.1.
H( f )
White Gaussian
− fm 0 fm
x (n )
H( f )
White Gaussian
− fm 0 fm
Fig. 1 Block diagram of Rayleigh fading simulator
Based on Eqn.(2), both the in-phase process and the quadrature process can be generated by
passing a White Gaussian noise process through a baseband filter which has the following fre-
quency response:
   f  2  −1 4
 K 1 −    f < fm
H ( f ) =    f m  

 0 others (3)
where K is constant to normalize the frequency response. The above frequency response is
generated in the frequency domain using FFT with length = 2048 points. Each point (0 <= K
<= length -1) corresponds to a certain frequency (fk) by means of the following equation:
fk = k x fs (4)
where fs is the frequency sampling interval typically chosen to be on the order of fm/10.
The above frequency response has an even real part and an odd imaginary part to guarantee
that the filtering process will generate a real in-phase and quadrature correlated Gaussian pro-
cesses. Each two generated Gaussian processes are combined to generate a Rayleigh fading
process. It is important to point out that whether in-phase process or quadrature process is cor-
related among different points but the two processes are generated independently and there-
fore, uncorrelated.
Assume that channel delay for each path can be expressed by Di samples. Each generated Ray-
leigh fading process corresponds to a path with a user-specified delay Di and relative power Pi,
0 <= i <= L-1. The expected output along the ith fading path should be the input signal delayed
by Di samples and Rayleigh-faded with the specified ith relative power Pi. The total average
power contribution from all paths is always normalized to unity. This is accomplished by set-
ting the standard deviation of the ith generated in-phase and quadrature correlated Gaussian
processes to
P
σi = i
L −1
2∑ Pl
l =0
(5)
These time series of the generated fading process is further increased in the time domain to
match the sampling rate of the input signal. This is accomplished by linearly interpolating the
fading process (i.e., inserting fading points between each two originally generated fading
points).
4. The above does not consider linear antenna array. A uniformly spaced linear antenna array
with J elements[3][4] is considered, as shown in Fig.2.
Signal
}C Antenna 2
Antenna 1
θi
Antenna n
Antenna J
Fig. 2 Block diagram of Linear Antenna Array
Assuming a signal with wavelength λ arrives at the linear antenna array from a direction,
which is called direction of arrival (DOA) θi, and taking the first element in the array as phase
reference, the relative phase shift of the received signal at the nth element can be expressed as
2πC (n − 1)
ψ i ,n = sin θ i
λ (6)
where C is the array spacing. The vector channel impulse response for the J elements can be
expressed as
L−1
h (t ) = ∑ α i (t )e jϕi ( t ) β (θ i )δ (t − τ i )
i =0 (1 ≤ L ≤ 12) (7)
where β(θi) is the array response vector, which is given by
[
β (θ i ) = e
jψ i ,1
e
jψ i , 2
… e ]
jψ i , J T
(8)
T
where [ ] denotes the matrix transpose.
5. Note that J samples are outputted successively for each input sample.
Netlist Form
MRFCHLAA:NAME n1 n2 L=val J=val VM=val C=val [SEED=val] D1=val
P1=val A1=val + [D2=val . . . A12=val] [RIN=val] [ROUT=val]
Netlist Example
MRFCHLAA:1 1 2 L=2 J =2 VM = 12.0 C = 0.17 SEED = 7359749 D1 =
0 P1 = 0 A1 = 0DEG +D2 = 150 P2 = 0 A2 = 10DEG
References
3. S. C. Swales, M. A. Beach, et al, “The performance enhancement of multibeam adaptive base-
station antennas for cellular land mobile radio systems,” IEEE Trans. Veh. Technol., vol. 39,
pp. 56–67, Feb. 1990.
4. S. Tanaka, A. Harada, et al, “Experiments on coherent adaptive antenna array diversity
for wideband DS-CDMA mobile radio,” IEEE Journal on Selected Areas in Communica-
tions, vol. 18, No.8, pp.1495-1504, Aug. 2000.
4
WCDMA Rake Receiver
WCDMA Rake Receiver4-83

Despreader (DESPREADER)
DESPREADER
G Spreading factor None 32 [2, Inf]/Integer
S Number of samples None 4 [1, 128]/Integer

per chip
DMAX Maximum multipath None 31 [0, Inf)/Integer

delay for multi-path
(samples)
Ports
Input1 Received signal in complex envelope format (complex)
Input2 Multipath delays, in terms of samples (integer)
Input3 Spreading code (complex)

Output Symbols after despreading on each path (complex)
Limits
0 ≤ Dmax ≤ (N p + N d ) × G × S − 1
Notes
1. The despreader model can be used to resolve the received multi-path signal and despread sym-
bols on each path in DS/CDMA systems. For detailed algorithm, please refer to the matched
filter model.
2. Note that L samples are outputted successively for each symbol.
Netlist Form
DESPREADER:NAME n1 n2 n3 n4 L=val G=val [S=val] [DMAX=val]
+[RIN1=val] [RIN2=val] [RIN3=val] [ROUT=val]
Netlist Example
DESPREADER:1 1 2 3 4 L =2 G = 32 S = 4 DMAX = 20
References
2. A. J. Viterbi, CDMA: Principles of Spread Spectrum Communication, Wesley Publishing
Company, 1995.
3. K. Higuchi, H. Andoh, et al, “Experimental evaluation of combined effect of coherent
RAKE combining and SIR-based fast transmit power control for reverse link of DS-
CDMA mobile radio,” IEEE Journal on Selected Areas in Communications, vol. 18, No.8,
pp.1526-1535, Aug. 2000.

Channel Estimation (LICE)

LICE
PURPOSE Data demodulation {0} None 0 [0, 1]/Integer

Power control {1}
NP Number of pilot symbols None 4 [0, INF)/Integer
ND Number of data symbols None 36 [0, INF)/Integer
N0 Number of the first pilot None 0 [0, INF)/Integer

symbol
PHASE Additional phase of pilot Deg 0 [-180, 180)/Real

symbols
Rin1 Input1 Impedance Ohm Inf (0,INF]/Real
Rin2 Input2 Impedance Ohm Inf (0,INF]/Real
Rout Output impedance Ohm 0 [0,INF)/Real

Limits
0 ≤ N0 ≤ Nd − 1
Notes
1. The Linear interpolation channel estimation model can be used to estimate channel characteris-
tics for all paths using pilot symbols.
2. Algorithm description: Let ri(n,k) be the nth received symbol at the output of the matched fil-
ter in the kth slot for the ith resolved path, and p(n,k) be the nth local standard pilot symbol in
the kth slot. The instantaneous channel estimation of the ith resolved path is performed using
the pilot symbols belonging to the kth slot as follows
1 r (n + N , k )
N p −1
ηˆl (k ) = ∑ pl (n + N 0 , k )
Np n =0 0
(1)
where Np is the number of pilot symbols per slot, N0 is the number of the first pilot symbol.
The instantaneous channel estimation is used for Power control. We can extend the observa-
tion interval to more than one slot to add coherently several consecutive channel estimates for
Data demodulation. The channel estimation is performed by a first order interpolation filter,
and the following equation (2) is used for channel estimation of the first slot:
 ηˆl (k ) 0 ≤ n < N0 + N p

η~l (n, k ) =  n − N 0 − (N p − 1) 2  n − N 0 − (N p − 1) 2
1 − ηˆl (k ) + ηˆl (k + 1) N0 + N p ≤ n < Ns
 Ns  Ns
The following equation (3) is used for channel estimation of the other slots:
 N 0 + (N p − 1) 2 − n  N + (N p − 1) 2 − n 
 ηˆl (k + 1) + 1 − 0 ηˆl (k ) 0 ≤ n < N0
 N s  N s 

ηl (n, k ) = 
~ ηˆl (k ) N0 ≤ n < N0 + N p

1 − n − N 0 − (N p − 1) 2 ηˆ (k ) + n − N 0 − (N p − 1) 2 ηˆ (k + 1) N0 + N p ≤ n < Ns
 Ns  l
 Ns
l

where Ns = Np + Nd is number of symbols per slot. Finally, L samples are outputted succes-
sively for each symbol.
3. In order to understand this model better, a block diagram of Rake receiver used in time-multi-

plexed pilot channel is given, as shown in Fig.1
Signal Matched
Rake Demodulated
Filter
Combiner Symbol
Channel
Code Estimation
Pilot
Fig. 1 Block diagram of Rake receiver

Netlist Form
LICE:NAME n1 n2 n3 [PURPOSE=val] L=val NP=val ND=val [N0=val]
[PHASE=val] + [RIN1=val] [RIN2=val] [ROUT=val]
Netlist Example
LICE:1 1 2 3 PURPOSE = 0 L =2 NP = 4 ND = 16 PHASE = 0DEG
References
1. F. Adachi, K. Ohno, et al, “Coherent multicode DS-CDMA mobile radio access,” IEICE
Trans. Commun., vol. E79-B, pp. 1316–1325, Sept. 1996.
2. S. Sampei and T. Sunaga, “Rayleigh fading compensation for QAM in land mobile radio com-
munications,” IEEE Trans. Veh. Tech., vol. 42, no. 2, pp. 137–147, May 1993.

Matched Filter (MATCHFILTER)

MATCHFILTER
METHOD Pilot Assisted {0} / None 0 [0, 1]/Integer

Perfect {1}
G Spreading factor None 32 [2, Inf)/Integer
S Number of samples per None 4 [1, 128]/Integer

chip
K Number of slots for None 1 [1, Inf)/Integer

block-average power
delay estimation
NP Number of pilot symbols None 4 [1, Inf)/Integer
ND Number of data symbols None 36 [0, Inf)/Integer
N0 Number of the first pilot None 0 [0, Inf)/Integer

symbol
DMAX Maximum multipath None 31 [0, Inf)/Integer

delay (samples)
D0~D15 Multipath delays None 0 [0, Inf)/Integer

(samples)

Ports
Input3 Pilot symbols (complex)
Output Despread symbols of the current slot (complex)
Limits
0 ≤ N0 ≤ Nd − 1
Notes
1. The matched filter model can be used to resolve the received multi-path signal and despread
symbols on each path in DS/CDMA systems. The block diagram of the matched filter is shown
in Fig.1. If Method is set to Pilot Assisted {0}, the received signal is despread using the esti-
mated multi-path delays (i.e., the output of the Multi-Path Search). If Method is set to Perfect
{1}, the received signal is despread using the given parameter values D0 ~ DL-1.
Signal
Despread symbols
Despread on each path
Multi-Path
Search
Sample
Selection
Code
Pilot

Fig. 1 Block diagram of matched filter
2. Slot Structure
The slot structure is shown in Fig.2. Each slot comprises Np pilot symbols and Nd data sym-
bols. N0 is the number of the first pilot symbol, i.e, the N0 ~ (N0 + Np -1) symbols are pilots.
Slot
0 1 N0 N0 + N p − 1 N p + Nd −1
Pilot Symbols
Fig.2 Slot structure

3. Sample Selection: Because of channel delay and shaping filter, the optimum sample position
should be found to maximize the output power and minimize inter-symbol interference. The
input signal is a discrete one sampled at the rate of 1/Ts in simulation. To determine the opti-
mum sample position is to select an optimum sample from the S samples during a chip. The
optimum sample position can be determined by comparing correlation values between the
received signal starting at each sample point and the corresponding spreading code.
Assume complex vector x [ ] stores the received signal sampled at the rate of 1/Ts. Thus the
correlation value between the received signal and the spreading code is given by
1 G −1 S −1
R1 ( j ) = ∑ ∑ x[i × S + k + j ] × c ∗ [i ]
2G i =0 k =0 (1)
4. where G is the spreading factor and S is the number of samples per chip and the vector c [ ]
stores the corresponding spreading code. The factor 1/2 is used to remove changes of symbol
power caused by spreading and despreading. When the jth sample point of input signal hits the
first chip of that symbol (which is spread by the spreading code c [ ]), the magnitude of the cor-
relation value will be the greatest among these samples.
In this model, there are (Dmax+1) correlation values, where Dmax is the possible maximum
path delay in terms of samples. Once the (Dmax+1) correlation values are calculated, the sam-
ple position where the magnitude of the correlation value is the greatest is selected. If this sam-
ple is the jth sample, then j mod S becomes the optimum sample position (SOPT..
Because all NF pilot symbols in a slot are known for the matched filter in the receiver, their
correlation values are added to increase processing gain. However, pilot symbols are not the
same in a slot, these correlation values must be divided by the corresponding pilot symbol val-
ues before the addition. So (Dmax+1) values are produced. If the jth one has the greatest mag-
nitude, then the (J mod S) sample position for each chip is selected as the optimum sample
position for the current slot.
In a practical situation, it is very difficult to search, slot by slot. This model allows us to use the
block-average power delay profile (K>1) [3]. First, the instantaneous power delay profile is
measured by using pilot symbols belonging to each slot and, then, average them over multiple
slots.
5. Multi-Path Search: The transmitted signal arrives at the receiver via different paths and delays.
To use more signal power, multi-path delays of the received signal of the desired user are
determined and signals on each resolved paths are combined. Because it is difficult to deter-
mine the relative multi-path delays at the precision of TS, multi-path delays are determined at
the precision of Tc, where Dc = Tc x S is chip duration. Let Dc be the maximum delay in terms
of chips, i.e., Dc equals the largest integer which is not larger than Dc/S, can be expressed as
Dc = Ds S  (2)
6. After the optimum sample position DOPT has been determined by Sample Selection, the corre-
lation values between the received signal at each possible delay, in terms of chips, are calcu-
lated as follows:
R2 ( j ) = [
1 G −1 S −1
]
∑ ∑ x (i + j ) × S + k + Sopt × c∗ [i ]
2G i =0 k =0 (3)
7. As in Sample Selection, the correlation values of different pilot symbols on the same path are
divided by the corresponding pilot symbol values and added. Dc + 1 results of additions are
obtained. In these results, L with the greatest magnitude are selected, the corresponding paths
that belong to L results are determined as L valid paths. The Multi-Path Search process can
also use the block-average power delay profile (K>1) [3].
8. Despread: After multi-path delays are obtained by the Multi-Path Search, symbols on each
path in current slot are despread. If Method is set to Perfect {1}, symbols on each path in cur-
rent slot are despread using the given parameter values D0~DL-1, rather than the multi-path
delays are obtained by the Multi-Path Search. The despreading process is the same as the pro-
cess of calculating correlation value. Finally, L samples are outputted successively for each
symbol.
Netlist Form
MATCHFILTER:NAME n1 n2 n3 n4 [METHOD=val] L=val G=val [S=val]
[K=val] NP=val ND=val + [N0=val] [DMAX=val] [D0=val,…,
D15=val] [RIN1=val] [RIN2=val] [RIN3=val] [ROUT=val]
Netlist Example
MATCHFILTER:1 1 2 3 4 METHOD = 0 L =2 G = 32 S = 4 DMAX = 20 NP
= 4 ND = 16 D0 = 1 D1 = 9

References
Company, 1995.
3. K. Higuchi, H. Andoh, et al, “Experimental evaluation of combined effect of coherent RAKE
combining and SIR-based fast transmit power control for reverse link of DS-CDMA mobile
radio,” IEEE Journal on Selected Areas in Communications, vol. 18, No.8, pp.1526-1535,
Aug. 2000.

Multipath Search (MPATHSEARCH)

MPATHSEARCH

Perfect {1}

per chip

block-average
power delay
estimation
NP Number of pilot None 4 [1, Inf)/Integer

symbols
ND Number of data None 36 [0, Inf)/Integer

symbols
N0 Number of the first None 0 [0, Inf)/Integer

pilot symbol

DMAX Maximum None 31 [0, Inf)/Integer

multipath delay
(samples)

(samples)
Ports
Input2 Optimum sample position (integer)
Output Multipath delays, in terms of samples (integer)
Limits
0 ≤ Dmax ≤ (N p + N d ) × G × S − 1
, 0 ≤ D0 ,…, D15 ≤ Dmax
Notes
1. The multi-path search model can be used to search multi-path and estimate multi-path delays
under the condition that the optimum sample position is known. If Method is set to Pilot
Assisted {0}, the multi-path delays are estimated using the corresponding spreading code and
pilot symbols. For detailed algorithm, please refer to the matched filter model. If Method is set

to Perfect {1}, the multi-path delays are set to D0 ~ DL-1.

2. Note that L delay values are outputted successively for each symbol.
Netlist Form
MPATHSEARCH:NAME n1 n2 n3 n4 n5 [METHOD=val] L=val G=val
[S=val] [K=val] NP=val ND=val
+ [N0=val] [DMAX=val] [D0=val,…, D15=val] [RIN1=val] [RIN2=val]
Netlist Example
MPATHSEARCH:1 1 2 3 4 5 METHOD = 0 L =2 G = 32 S = 4 DMAX = 20
NP = 4 ND = 16 D0 = 1 D1 = 9
References
Company, 1995.
pp.1526-1535, Aug. 2000.

Multipath Delay Estimation (MPDE)

MPDE

Perfect {1}

per chip

block-average
power delay
estimation

symbols

symbols

pilot symbol
DMAX Maximum None 31 [0, Inf)/Integer

multipath delay
(samples)


(samples)
Ports
Input1 Received signal in complex envelope format

(complex)
Input2 Optimum sample position (integer)
Output Multipath delays, in terms of samples (integer)
Limits
0 ≤ N 0 ≤ N d − 1 , 0 ≤ Dmax ≤ (N p + N d ) × G × S − 1 , 0 ≤ D0 ,… , D15 ≤ Dmax
Notes
1. The multi-path delay estimation model can be used to search multi-path and estimate multi-
path delays. If Method is set to Pilot Assisted {0}, the multi-path delays are estimated using the
corresponding spreading code and pilot symbols. This component consists of the sample selec-
tion and multi-path search, as shown in Fig.1. For detailed algorithm, please refer to the

matched filter model. If Method is set to Perfect {1}, the multi-path delays are set to D0~DL-
2. Note that L delay values are outputted successively for each symbol.
Signal
Multi-Path Multi-Path Delays
Search
Sample
Selection
Code
Pilot
Fig. 1 Block diagram of multipath delay estimation

Netlist Form
MPDE:NAME n1 n2 n3 n4 [METHOD=val] L=val G=val [S=val] [K=val]
NP=val ND=val [N0=val]+ [DMAX=val] [D0=val,…, D15=val]
[RIN1=val] [RIN2=val] [RIN3=val] [ROUT=val]
Netlist Example
MPDE:1 1 2 3 4 METHOD = 0 L =2 G = 32 S = 4 DMAX = 20 NP = 4 ND
= 16 D0 = 1 D1 = 9
References
Company, 1995.
pp.1526-1535, Aug. 2000.

MPSK Symbol Decision (MPSKSD)

MPSKSD
M Order of the signal None 4 [2, 1024]/Integer

space (default: 4,
i.e., QPSK)
PHASE Additional phase of Deg 0 [-180, 180)/Real

symbols
Ports
Input Symbol before decision (complex)
Output Symbol after decision (complex)
Notes
1. The MPSK Symbol Decision model can be used to make the symbol decision for MPSK sig-
nals.
Netlist Form
MPSKSD:NAME n1 n2 M=val [PHASE=val] [RIN=val] [ROUT=val]
Netlist Example
MPSKSD:1 1 2 M =4 PHASE = 0DEG

References

Rake Combiner (RAKECOMBINER)

RAKECOMBINER
Ports
Input2 Channel estimates (complex)
Output Rake-combined signal (complex)
Notes
1. The Rake Combiner model can be used to generate a Rake-combined signal.
2. Rake-combining is performed based on maximum ratio criteria. Maximal ratio criteria is a
weighted signal combining method in which the weighting factor for each signal to be com-
bined is the strength of the signal if the phase factor is not considered. Let rl(n,k) be the nth
received symbol at the output of the matched filter in the kth slot for the lth resolved path, and
nl(n,k) be corresponding channel estimate. The output of the Rake Combiner for the nth sym-
bol of the kth slot is represented by

L −1
rd (n, k ) = ∑ ~
~ rl (n, k )η~l* (n, k )
l =0 (1)
where L is the number of resolved paths, * denotes the complex conjugate. In order to under-
stand this model better, a block diagram of Rake receiver used in time-multiplexed pilot chan-
nel is given, as shown in Fig. 1.
Signal Matched
Rake Demodulated
Filter
Combiner Symbol
Channel
Code Estimation
Pilot
Fig. 1 Block Diagram of Rake Receiver

Netlist Form
RAKECOMBINER: NAME n1 n2 n3 L=val [RIN1=val] [RIN2=val]
[ROUT=val]
Netlist Example
RAKECOMBINER:1 1 2 3 L =2
References
pp.1526-1535, Aug. 2000.
2. T. Dohi, Y. Okumura, et al, “Further results on field experiments of coherent wideband DS-
CDMA mobile radio,” IEICE Trans. Commun., vol. E81-B, pp. 1239–1247, June 1998.

Sample Selection (SAMPSELECT)

SAMPSELECT
METHOD Pilot Assisted {0} None 0 [0, 1]/Integer

Perfect {1}

per chip

block-average
power delay
estimation integer

symbols

symbols

pilot symbol
DMAX Maximum delay None 16 [0, Inf)/Integer

for multi-path
(samples)

S0 Perfect sample None 0 [0, 127]/Integer

position
Ports
Input1 Received signal on complex envelope format (complex)
Output Optimum sample position (integer)
Limits
0 ≤ N0 ≤ Nd − 1
0 ≤ Dmax ≤ (N p + N d ) × G × S − 1
0 ≤ S0 < S
Notes
1. The sample selection model can be used to determine the optimum sample position for each
slot in DS/CDMA systems. If Method is set to Pilot Assisted {0}, the optimum sample position
is estimated using the corresponding spreading code and pilot symbols. For detailed algorithm,
please refer to the matched filter model. If Method is set to Perfect {1}, the optimum sample
position is the value of the parameter S0.
Netlist Form
SAMPSELECT:NAME n1 n2 n3 n4 [METHOD=val] G=val [S=val] [K=val]
NP=val ND=val [N0=val]+ [DMAX=val] [S0=val] [RIN1=val]
Netlist Example
SAMPSELECT:1 1 2 3 4 METHOD = 0 G = 32 S = 4 DMAX = 20 NP = 4 ND
= 16 S0 = 1

References:
Company, 1995.
pp.1526-1535, Aug. 2000.

SIR Measurement (SIRM)

SIRM

symbols

symbols

pilot symbol
N1 The first symbol None 0 [0, Inf)/Integer

used for signal
power
measurement
N2 The last symbol None 39 [0, Inf)/Integer

used for signal
power
measurement

Ports
Output1 Signal power (real)
Output2 Interference power (real)
Limits
0 ≤ N 0 ≤ N d − 1 , 0 ≤ N1 < N 2 ≤ N p + N d − 1
Notes
1. The SIR Measurement model can be used for signal power and interference power measure-
ment.
2. Signal power measurement: Define signal power the average of squared value of magnitude of
symbols after Rake-Combining. Assuming r(n,k) is the nth received symbol at the output of the
matched filter in the kth slot, then average signal power starting from symbol N1 and ending on
symbol N2, which can be expressed as
N2
1
S (k ) = rl (n, k )
2
∑
N 2 − N 1 + 1 n = N1 (1)
3. Interference power measurement: Interference power, assisted by pilot symbols, is calculated
as the average of squared magnitude of differences between the received and estimated pilot
symbols. The average signal power of pilot symbols after Rake-Combining is calculated as fol-
lows
r (n + N 0 , k )
N p −1 2
2
Ppilot (k ) = ∑
Np n =0 p (n + N 0 , k )
(2)
where Np is number of pilot symbols per slot, N0 is the number of the first pilot symbol, p(n,k)
is the nth local standard pilot symbol in the kth slot. Interference power is calculated as follows
2
1 N p −1
Ppilot (k )
I (k ) = ∑ r (n, k ) − p (n, k )
Np n =0 2
(3)
4. If the SIR Measurement model is used for Fast Transmission Power Control, large time delay
caused by Channel estimation is not allowed. Therefore, we separate the Rake combining pro-
cess for SINR Measurement from that for date demodulation. In order to understand the idea
better, a block diagram of SIR Measurement model with Rake receiver used in time-multi-
plexed pilot channel is given, as shown in Fig.1
Signal Matched
Rake Demodulated
Filter
Combiner Symbol
Channel
Code Estimation
Rake SIR S
Combiner Measurement I
Channel
Estimation
Pilot

Netlist Form
SIRM:NAME n1 n2 n3 n4 NP=val ND=val [N0=val] [N1=val]
[N2=val] + [RIN1=val] [RIN2=val] [ROUT1=val] [ROUT2=val]
Netlist Example
SIRM:1 1 2 3 4 PURPOSE = 0 L =2 NP = 4 ND = 16 N0 = 0 N1 = 0 N2
= 19
References
Company, 1995.
2. H. Andoh, M. Sawahashi, and F. Adachi, “Channel estimation filter using time-multiplexed
pilot channel for coherent Rake combining in DS-CDMA mobile radio,” IEICE Trans. Com-
mun., vol. E81-B, no. 7, pp. 1517–1526, July 1998.
3. K. Higuchi, H. Andoh, et al, “Experimental evaluation of combined effect of coherent RAKE
combining and SIR-based fast transmit power control for reverse link of DS-CDMA mobile
radio,” IEEE Journal on Selected Areas in Communications, vol. 18, No.8, pp.1526-1535,
Aug. 2000.

Transmission Power Control (TPC)

TPC
SIR Target (dB) None 0 (-Inf, 200]/Real
FORGETTOR Forgetting factor None 0.1 [0.0, 1.0]/Real
INIT_SLOT Number of initial None 10 [0, Inf)/Integer

invalid slots
Ports
Input1 Signal power (real)
Input2 Interference power (real)
Output Transmission power control command: +1/ -1 (Integer)
Notes
1. The Transmission Power Control model can be used generate transmission power control com-
mands (+/- 1) with an interval of one slot. +1 indicates increasing transmission power, and -1

indicates reducing transmission power.

2. Let I(k) be the interference power at the kth slot. Before being used to calculate SINR, the
input interference power is pre-averaged using a first-order filter with forgetting factor as fol-
lows
I (k ) = (1 − µ )I (k − 1) + µ I (k ) (1), where µ is the forgetting factor.
3. The measured SIR λ(k) the kth slot is defined as
λ (k ) = 10 log(S (k ) I (k )) (2)
This value λ(k) is compared to a pre-determined Target SIR (dB), if greater, transmission
power control command -1 will be output, otherwise, +1 will be output.
Netlist Form
TPC:NAME n1 n2 n3 SIR=val [FORGETTOR =val] [INIT_SLOT =val]
Netlist Example
TPC:1 1 2 3 SIR = 0 FORGETTOR=1.0 INIT_SLOT =1
References
Company, 1995.
2. H. Andoh, M. Sawahashi, and F. Adachi, “Channel estimation filter using time-multiplexed

Channel Estimation (WMSA)

WMSA
PURPOSE Data demodulation {0} None 0 [0, 1]/Integer

Power control {1}
L Number of paths None 2 [1,16]/Integer
K Number of taps in each None 1 [1, 16]/Integer

side

symbols

symbols

pilot symbol
PHASE Additional phase of Deg 0 [180, -180]/Integer

pilot symbols
A0~A15 Weighting factor None 0 [0, Inf)/Integer

Ports
Output Channel estimates (complex)
Limits
0 ≤ N0 ≤ Nd − 1
Notes
1. The weighted multi-slot averaging (WMSA) channel estimation model can be used to estimate
channel characteristics for all paths using pilot symbols. The WMSA channel estimation is
shown in Fig.1.
2. Algorithm description: Let rl(n,k) be the nth received symbol at the output of the matched filter
in the kth slot for the lth resolved path, and p(n,k) is the nth local standard pilot symbol in the
kth slot. The instantaneous channel estimation of the lth resolved path is performed using the
pilot symbols belonging to the kth slot as follows
1 r (n + N , k )
N p −1
ηˆl (k ) = ∑ pl (n + N 0 , k )
Np n =0 0
(1)
where Nf is the number of pilot symbols per slot, N0 is the number of the first pilot symbol. In
the case of slow fading, since the channel gain remains almost the same over a period of sev-
eral slots, we can extend the observation interval to more than one slot to add coherently sev-
eral consecutive channel estimates. We apply a linear filter with 2K taps. The filter output is
expressed as
K −1 K −1
η~l (k ) = ∑ α −iηˆl (k − i ) + ∑ α iηˆl (k + i + 1)
i =0 i =0 (2)
where αi is the real-valued weighting factor (or tap coefficient). Since the magnitude of the
autocorrelation function of the time-varying complex-valued channel gain is an even function
with respect to the time difference, the contribution from the past and future channel gains to
the channel estimate should be the same. Therefore, we set the filter coefficients, αi and α-i,
equal to each other. Term nl(k) is used as the channel estimate at all symbol positions in thee
kth slot, so the channel estimate is represented as

η~ (n, k ) = η~ (k )
l l for
n = 0,1,… , N p + N d − 1
(3)
rl (n, k ) 1 N p −1
η̂l (k + K ) ηˆl (k + 1) η̂l (k ) ηˆl (k − (K − 1))
Np
∑ (⋅) D D D D D
n =0
α K −1 α1 α0 α0 α −1 α −(K −1)
η~l (k )
Channel estimate
Fig. 1 Block diagram of WMSA channel estimation
3. In order to understand this model better, a block diagram of Rake receiver used in time-multi-
plexed pilot channel is given, as shown in Fig.2.
Signal Matched
Rake Demodulated
Filter
Combiner Symbol
Channel
Code Estimation
Pilot

References
1. [1]K. Higuchi, H. Andoh, et al, “Experimental evaluation of combined effect of coherent
pp.1526-1535, Aug. 2000.
2. [2]H. Andoh, M. Sawahashi, and F. Adachi, “Channel estimation filter using time-multiplexed


WCDMA Transmitter
WCDMA Transmitter-116
Gold Sequence Generator (GOLD)

GOLD
Range/Type/
Type
L Length of shift None 5 [2, 63]/Integer

register
N Period of the m- None 31 [1, Inf)/Integer

sequence
PL1 The first primitive None 37 [1, Inf)/Integer

polynomial (low 32
bits) in decimal
PH1 The first primitive None 0 [0, Inf)/Integer

polynomial (high
32 bits) in decimal
PL2 The second None 37 [1, Inf)/Integer

primitive
polynomial (low 32
bits) in decimal
PH2 The second None 0 [0, Inf)/Integer

primitive
polynomial (high
32 bits) in decimal
SL1 Initial state of the None 1 [0, Inf)/Integer

first shift register
(low 32 bits) in
decimal
SH1 Initial state of the None 0 [0, Inf)/Integer

first shift register
(high 32 bits) in
decimal
SL2 Initial state of the None 1 [0, Inf)/Integer

second shift
register (low 32
bits) in decimal
SH2 Initial state of the None 0 [0, Inf)/Integer

second shift
register (high 32
bits) in decimal
NC Number of chips None Required [0, Inf)/Integer
RC Chip rate of the m- Hz 1000 (0, Inf)/Real

sequence
T True output value None -1 (-Inf, Inf)/Real
Ports
Output Truncated Gold sequence (real)
Notes
1. The Gold Sequence Generator model is used to generate Gold sequence.
2. The Gold sequence can be generated by taking modulo-2 sum of two m-sequences with
different offset in Galois field. Not all pairs of m-sequences do generate Gold sequence and
those which generate Gold sequence are called preferred pairs. A typical LFSR structure used
to be generate a family of Gold sequences is illustrated in Fig.1. For detailed description of
LFSR, please refer to the m-sequence Generator model.
3. As in the m-sequence Generator model, that the primitive polynomial in binary is gog1...gL
and the initial state of the shift register in binary is SL-1SL-2...S0.
g0 g1 g2 gL−2 g L −1 gL
sL −1 sL −2 s2 s1 s0
Gold
Sequence
g0 g1 g2 gL−2 g L −1 gL
sL −1 sL −2 s2 s1 s0
Fig. 1 Block diagram of Gold Sequence Generator

Netlist Form
GOLD:NAME n1 L=val [N =val] [PL1=val] [PH1 =val] [PL2=val] [PH2
=val] [SL1=val] [SH1 =val] + [SL2=val] [SH2 =val] NC=val
[RC=val] [T=val] [F =val] [ROUT=val]
Netlist Example
GOLD:1 1 L = 5 N=31 PL1 = 41 PH1 = 0 PL2 = 41 PH2 = 0 SL1 = 31
SH1 = 0 SL2 = 1 SH2 = 0 NC = 124 + RC = 1khz T= 1 F= 0
References
2. R. L. Peterson, R. E. Ziemer, and D. E. Borth, Introduction to Spread Spectrum Communica-
tions. Prentice Hall International Editions, 1995.
M-Sequence Generator (MSEQ)

MSEQ
L Length of shift register None 5 [2, 63]/Integer
N Period of the m-sequence None 31 [1, Inf)/Integer
PL Primitive polynomial (low None 37 [1, Inf)/Integer

32 bits) in decimal
PH Primitive polynomial (high None 0 [0, Inf)/Integer

32 bits) in decimal
SL Initial state of the shift None 1 [0, Inf)/Integer

register (low 32 bits) in
decimal
SH Initial state of the shift None 0 [0, Inf)/Integer

register (high 32 bits) in
decimal
NC Number of chips None 0 [0, Inf)/Integer
RC Chip rate of the m-sequence Hz 1000 (0, Inf)/Real
T True output value None -1 (-Inf, Inf)/Integer
F False output value None 1 (-Inf, Inf)/Integer
Ports
Output Truncated m-sequence (real)
Notes
1. The m-sequence Generator model can be used to generate m-sequence.
2. The m-sequence can be generated using Linear Feedback Shift Register (LFSR) with a primi-
tive polynomial[2]. For a given primitive polynomial, there are two methods[2] of implement-
ing LFSR, i.e, Galois feedback generator and Fibonacci feedback generator. Since m-sequence
has the maximum possible period for a L-stage LFSR, it is also called maximal length
sequence. The maximum period of a L-stage LFSR can be proven to be 2L-1. The structure of
Linear Feedback Shift Register with Fibonacci feedback generator is shown in Fig.1. The
primitive polynomials g(D) is given by
g (D ) = g 0 + g1 D + g 2 D 2 + … + g L D L (1)
3. Table I shows a list of primitive polynomials for Linear Feedback Shift Register[2]. In the
table, all polynomials are specified by an octal number that defines the coefficients of g(D).
The octal number gives the coefficients of g(D) beginning with go on the right and proceeding
to gL in the last nonzero position on the left. For example, a L-tage LFSR uses the entry [367].
Expanding the octal entry 367 into binary form, we obtain
3 6 7 octal
0 1 1 1 1 0 1 1 1 binary
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
g7 g6 g5 g4 g3 g2 g1 g0 coefficient
Therefore, g (D ) = 1 + D + D 2 + D 4 + D 5 + D 6 + D 7
In Table I, each entry in brackets represents one primitive polynomial as a series of octal num-
bers, explained in the above example. The entries following by an asterisk correspond to cir-
cuit implementation with only two feedback connections, which are very useful for high-speed
applications. No reciprocal polynomial is listed in Table I. Since the reciprocal polynomial of a
primitive polynomial is also primitive, each entry in this table can be used to generate two dis-
tinct m-sequences.
g0 g1 g2 gL−2 g L −1 gL
sL −1 sL − 2 s2 s1 s0 m-sequence
Fig. 1 Block diagram of m-sequence Generator (Fibonacci feedback generator)

4. Note that the primitive polynomial in binary is g0g1...gL and the initial state of the shift register
in binary is SL-1SL-2...S0 .
5. A list of primitive polynomials is tabulated in the following table:
Degree Octal Representation of primitive polynomial (g0 on left to gLon right)

2 [7]*
3 [13]*
4 [23]*
5 [45]*, [75], [67]
6 [103]*, [147], [155]
7 [211]*, [217], [235], [367], [277], [325], [203]*, [313], [345]
8 [435], [551], [747], [453], [545], [537], [703], [543]
9 [1021]*, [1131], [1461], [1423], [1055], [1167], [1541],
[1333], [1605], [1751], [1743], [1617], [1553], [1157]
10 [2011]*, [2415], [3771], [2157], [3515], [2773], [2033],
[2443], [2461], [3023], [3543], [2745], [2431], [3177]
11 [4055]*, [4445], [4215], [4055], [6015], [7413], [4143],
[4563], [4053], [5023], [5623], [4577], [6233], [6673]
12 [10123], [15647], [16533], [16047], [11015], [14127],
[17673], [13565], [15341], [15053], [15621], [15321],
[11417], [13505]
13 [20033], [23261], [24623], [23517], [30741], [21643],
[30171], [21277], [27777], [35051], [34723], [34047],
[32535], [31425]
14 [42103], [43333], [51761], [40503], [77141], [62677],

[44103], [45145], [76303], [64457], [57231], [64167],
[60153], [55753]
15 [100003]*, [102043], [110013], [102067], [104307], [100317],
[177775], [103451], [110075], [102061], [114725], [103251],
[100021]*, [100201]*
16 [210013], [234313], [233303], [307107], [307527], [306357],
[201735], [272201], [242413], [270155], [302157], [210205],
[305667], [236107]
17 [400011]*, [400017], [400431], [525251], [410117], [400731],
[411335], [444257], [600013], [403555], [525327], [411077],
[400041]*, [400101]*
18 [1000201]*, [1000247], [1002241], [1002441], [1100045],
[1000407], [1003011], [1020121], [1101005], [1000077],
[1001361], [1001567], [1001727], [1002777]
19 [2000047], [2000641], [2001441], [2000107], [2000077],
[2000157], [2000175], [2000257], [2000677], [2000737],
[2001557], [2001637], [2005775], [2006677]
20 [4000011]*, [4001051], [4004515], [6006031], [4442235]
21 [10000005]*, [10040205], [10020045], [10040315], [10000635],
[10103075], [10050335], [10002135], [17000075]
Netlist Form
MSEQ:NAME n1 L=val [N =val] [PL=val] [PH =val] [SL=val] [SH
=val] NC=val [RC=val] + [T=val] [F =val] [ROUT=val]
Netlist Example
MSEQ:1 1 L = 5 N=31 PL = 41 PH = 0 SL = 31 SH = 0 NC = 124 RC
= 1khz T= 1 F= 0
References
Power Amplifier (POWAMP)

POWAMP
METHOD Constant gain {0} None 0 [0, 2]/Integer

Input gain {1}
TPC command {2}
GAIN Initial power gain None 0 (-Inf, 200]/Real

in dB
STEP Step size of power None 1 [0, 200]/Real

adjustment in dB
N Number of samples None 200 [1, Inf)/Integer

in a slot
INIT_SLOT Number of initial None 10 [0, Inf)/Integer

invalid slots
RIN Input impedance Ohm Inf [0, Inf]/Real
Ports
Input1 Input signal in complex envelope format (complex)
Input2 Gain or transmission power control command (integer)
Notes
1. The Power Amplifier model can be used to amplify the input signal.
2. If Method is set to Constant gain {0}, the input signal at Input1 is amplified by Gain (dB).
3. If Method is set to Input gain {1}, Input2 must be connected and each sample corresponds N
samples (i.e., one slot) at Input1. The input signal at Input1 during the first InitSlot slots is
amplified by Gain (dB) and then the input signal of each slot at Input1 is amplified by the
value (dB) of the corresponding sample at Input2.
4. If Method is set to TPC command {2}, Input2 also must be connected and each sample corre-
sponds N samples at Input1, i.e., one slot. The input signal at Input1 during the first InitSlot
slots is amplified by Gain (dB) and then the input signal of each slot at Input1 is further ampli-
fied by Step (dB) if the value of the corresponding sample at Input2 (i.e., TPC command) is 1,
by -Step (dB) for TPC command is -1, or kept the power of the previous slot if TPC command
is 0, as shon in Fig.1.
Input1 Output
TPC Command (Input2)
step Delay
10 10
Fig. 1 Block diagram of Power Amplifier with Method = 2.

Netlist Form:
POWAMP:NAME n1 n2 n3 [METHOD =val] GAIN =val [STEP =val] [N
=val] [INIT_SLOT =val] +[RIN1=val] [RIN2=val] [ROUT=val]
Netlist Example
POWAMP:1 1 2 3 METHOD = 2 GAIN = 0 STEP = 1 N = 20 INIT_SLOT =1
References
1. S. Seo, T. Dohi, and F. Adachi, “SIR-based transmit power control of reverse link for coherent
DS-CDMA mobile radio,” IEICE Trans. Commun., vol. E81-B, no. 7, pp. 1508–1516, July
1998.
Random Sequence Generator (RANDSEQ)

RANDSEQ
NB Number of random None 100 [1, Inf)/Integer

binary bits to be
generated
BR Bit rate at the Hz 1000Hz (0, Inf)/Real

output
SEED Random Seed None 0 [0, Inf)/Integer
T True output value None -1 (-Inf, Inf)/Real
Ports
Output Random sequence, taking the value T or F, equal

probability (real)
Notes
1. The Random Sequence Generator model can be used to generate random sequence, taking the
value T or F or with equal probability.

Netlist Form
RANDSEQ:NAME n1 NB =val BR=val [SEED=val] [T=val] [F =val]
[ROUT=val]
Netlist Example
RANDSEQ:1 1 NB = 100 BR = 1khz SEED =14727 T= 1 F= 0
Spreader (SPREADER)
Spreader (SPREADER)
SPREADER
G Spreading Factor None 16 [1, Inf)/Integer
S Number of samples per chip None 4 [1, 128]/Integer
FC Carrier frequency in Hz Hz 0 [0, Inf)/Real
Rout Output impedance Ohm 0 [0, Inf]/Real
Ports
Input1 Input signal in complex envelope format (complex )
Output Symbols after spreading (complex)
Notes
1. The Spreader model can be used to perform spreading (i.e., each sample at Input1 multiplies G
Spreader (SPREADER)
samples at Input2 and thus G products are obtained) and then repeat the outcome S times.
Netlist Form
SPREADER:NAME n1 n2 n3 G =val S =val [FC =val] [RIN1=val]
Netlist Example
SPREADER:1 1 2 3 G = 31 S = 4
References

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CDMA/IS-95

IS-95 Access Channel Block Deinterleaver (ACCBD95)

Property Description Units Default Range/Type

RIN Input impedance Ohm Inf (0, Inf]/Real

ROUT Output impedance Ohm 0 [0, Inf)/Real

Input Input signal (real)

Output Output signal (real)

IS-95 Access Channel Block Interleaver (ACCBI95)

Property Description Units Default Range/Type

RIN Input impedance Ohm Inf (0, Inf]/Real

ROUT Output impedance Ohm 0 [0, Inf)/Real

Input Input signal (real)

Output Output signal (real)

IS-95 Add 8-Bit Tail Bits for Initializing Convolutional Coder

Property Description Units Default Range/Type

FDR Frame Data Rate Hz 1200 [1200Hz, 9600]/Real

RIN Input impedance Ohm Inf (0, Inf]/Real

ROUT output Impedance Ohm 0 [0, Inf)/Real

Input Input signal (real)

Output Output signal (real)

System” TIA/EIA/IS-95-A, May 1995.

IS-95 Finite Impulse Response Filter (FIRIS95)

Property Description Units Default Range/Type

RIN Input impedance Ohm Inf (0, Inf]/Real

ROUT Output impedance Ohm 0 [0, Inf)/Real

Input Input signal (real)

Output Output signal (real)

h[0]= h[47] = -0.025288315

h[11]= h[36] = -0.051178658

IS-95 Frame Quality Indicator (FQI95)

Property Description Units Default Range/Type

FDR Frame Data Rate Hz 4800 4800 or 9600

RIN Input impedance Ohm Inf (0, Inf]/Real

ROUT Output impedance Ohm 0 [0, Inf)/Real

Input Input signal (real)

Output Output signal (real)

IS-95 Forward Traffic Channel Block Deinterleaver (FTCBD95)

Property Description Units Default Range/Type

FDR Frame Data Rate Hz 9600 [1200 9600]/Integer

RIN Input impedance Ohm Inf (0, Inf]/Real

ROUT Output impedance Ohm 0 [0, Inf)/Real

Input Input signal (real)

Output Output signal (real)

IS-95 Forward Traffic Channel Block Interleaver (FTCBI95)

Property Description Units Default Range/Type

FDR Frame Data Rate Hz 9600 [1200 9600]/Integer

RIN Input impedance Ohm Inf (0, Inf]/Real

ROUT Output Impedance Ohm 0 [0, Inf)/Real

Input Input signal (real)

Output Output signal (real)

IS-95 Long Code Generator (LONGCD95)

Property Description Units Default Range/Type

NB Number of bits None 100 [0,INF)/Integer

BR Output bit rate MHz 1.2288 [0,INF)/Real

INITIAL_CONTENT Initial contents of the shift None 1 [0,INF)/Integer

File Name of the external file with None Required String

ROUT Output impedance Ohm 0 [0, Inf)/Real

Output Output signal (real)

IS-95 Reverse Traffic Channel Block Deinterleaver (RTCBD95)

Property Description Units Default Range/Type

FDR Frame Data Rate Hz 9600 [1200, 9600]/Real

RIN Input impedance Ohm Inf (0, Inf]/Real