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  • Design Rules

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    mayankfirst
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    Design rules provide guidelines for translating circuit concepts into actual silicon geometries during chip fabrication. There are two main approaches to specifying design rules: lambda rules which define dimensions in terms of a scaling parameter lambda, and micron rules which use absolute dimensions. Design rules define constraints for features on each fabrication layer as well as between layers. Examples of common layers in a 0.25 micron CMOS process are wells, active areas, polysilicon, and multiple metal layers with design rules specifying minimum widths, spacings, and inter-layer distances.

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    Design rules provide guidelines for translating circuit concepts into actual silicon geometries during chip fabrication. There are two main approaches to specifying design rules: lambda rules which define dimensions in terms of a scaling parameter lambda, and micron rules which use absolute dimensions. Design rules define constraints for features on each fabrication layer as well as between layers. Examples of common layers in a 0.25 micron CMOS process are wells, active areas, polysilicon, and multiple metal layers with design rules specifying minimum widths, spacings, and inter-layer distances.

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    99 vues14 pages

    Design Rules

    Transféré par

    mayankfirst
    Design rules provide guidelines for translating circuit concepts into actual silicon geometries during chip fabrication. There are two main approaches to specifying design rules: lambda rules which define dimensions in terms of a scaling parameter lambda, and micron rules which use absolute dimensions. Design rules define constraints for features on each fabrication layer as well as between layers. Examples of common layers in a 0.25 micron CMOS process are wells, active areas, polysilicon, and multiple metal layers with design rules specifying minimum widths, spacings, and inter-layer distances.

    Droits d'auteur :

    Attribution Non-Commercial (BY-NC)
    Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 14

    Inel-6080 VLSI Systems Design

    Design Rules for CMOS


    Lecture 7 Electrical and Computer Engineering Department University of Puerto Rico at Mayagez Fall 2008

    Design Rules
    Allow for a ready translation of a circuit concept into an actual geometry in silicon Provide a set of guidelines for constructing the fabrication masks
    Minimum line width Minimum spacing between objects

    Multiple design rule specification methods exist


    Scalable Design Rules (Lambda rules) Micron Rules

    DESIGN RULES AND LAYOUT

    Specifying Design Rules


    Lambda Rules:
    Expressed in terms of a scaling parameter: Lambda () Minimum line width: 2 Main disadvantages:
    Limited linear scaling Too conservative

    Micron Rules
    Express designs in absolute dimensions Pro: Allow taking full advantage of technology Con: Scaling and Porting becomes more complicated

    DESIGN RULES AND LAYOUT

    Design Rule Entities


    1. Layer Representations
    Substrates and/or Wells Diffusion Regions (Active areas)
    Select regions: For contacts to substrate or well

    Polysilicon Layers Metal Interconnects


    Contact: Metal to active Via: Metal to metal

    2. Intralayer Constraints 3. Interlayer Constraints

    DESIGN RULES AND LAYOUT

    CMOS Process Layers


    Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation

    Layers in 0.25m CMOS Process

    DESIGN RULES AND LAYOUT

    DESIGN RULES AND LAYOUT

    Intra-Layer Design Rules


    Same Potential 0 or 6 10 3 Active 3 2 Select Contact or Via Hole 2 2
    Metal2 3

    Different Potential 9 Polysilicon 2 Metal1 3


    4

    Well

    DESIGN RULES AND LAYOUT

    Single Transistor Layout


    Transistor 1

    DESIGN RULES AND LAYOUT

    Vias and Contacts


    2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

    2 2

    DESIGN RULES AND LAYOUT

    Select Layer
    2 3 2 1 3 3 Select

    Substrate

    Well

    DESIGN RULES AND LAYOUT

    CMOS Inverter Layout


    VDD
    GND In VD D

    M2
    A A

    Vin

    Vout

    M1

    Out (a) Layout

    A p-substrate n
    +

    A n p
    +

    Field Oxide

    (b) Cross-Section along A-A

    DESIGN RULES AND LAYOUT

    Layout Editor

    DESIGN RULES AND LAYOUT

    Design Rule Checker

    poly_not_fet to all_diff minimum spacing = 0.14 um

    DESIGN RULES AND LAYOUT

    Stick Diagrams
    VDD In 3 Out

    1
    GND
    Stick diagram of an inverter

    Dimensionless layout entities Only topology is important Final layout generated by compaction program (if available)

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