Chap 1 Digital Deisgn with ASM Chart

ASM Chart: Algorithmic staate chart can describe the behavior of the hardware with the step-by-step operations in precise units of time. 1.1 State Machine Charts

Fig. 1 Comonets of an ASM chart

Fig. 2 Example 1 of an ASM Block

Z1=A+BC=A+ABC

Fig. 3 Example 3 of an ASM Block (a) Parallel form

(b) Serial form

Fig. 4 Example 4 of an ASM

ASM charts composed only of rectangles and diamonds are said to describe Moore machines. ASM charts that also include ovals are said to describe Mealy machines.

Fig. 5 ASM with multi-bit output

Fig. 6 ASM with register transfer

Fig. 7 ASM with Decision

Fig. external status ASM Input

ASM

with

Fig. 9 Two ways to test multi-bit input ASM Outputs 1. External command outputs : Fig. 2

(a) External data input

(b) External status inputs

or Fig. 3. 2. External data outputs : register transfer as shown in Fig. 4. Conversion of a State Graph to an SM Chart

(a) State graph

(b) Equivalent ASM chart

(c) Timing Chart for ASM chart Fig. 10 An example of conversion Top-down design Pure behavioral example : childish division algorithm r1 = x; r2 = 0; while (r1>= y) { r1 =r1 y; r2 = r2 + 1; }

Fig. 11 Block diagram

 A software algorithm can be translated into an ASM with the following rules: 1. Each assignment statement is written by itself in RTN in a unique rectangle that is not followed by a diamond. 2. Each if or while is translated into an empty rectangle with a diamond to implement the decision.

(a) Algorithmic state machine

(b) The ASM operation for x = 5 and y = 7

(c) The ASM operation for x = 14 and y = 7 Fig. 12 ASM for

software paradign (COMUTE1 at top)

(a) Algorithmic state machine

(b) The ASM operation for x = 14 and y = 7 Fig. 13 ASM for software paradign (COMUTE1 at top)

 Eliminating state TEST

(a) Algorithmic state machine

(b) the ASM operation Fig. 14 Incorrect four-state division machine

(a) Algorithmic state machine

(b) the ASM operation Fig. 15 Correct four-state divison machine

(a) Algorithmic state machine

(b) the ASM operation Fig. 16 Incorrect user

interface (throws quotient away)

(a) Algorithmic state machine

(b) the ASM operation Fig. 17 Saving quotient in r3

Fig. 18 Handling quotient of zero

(a) Algorithmic state machine

(b) The operation for x = 14 and y = 7 Fig. 19 Incorrect rearrangement of states

(a) Algorithmic state machine

(b) The operation for x = 14 and y = 7 Fig. 20 Incorrect parallelization attempt

(a) Algorithmic state machine

(b) The operation for x = 14 and y = 7

(C) The operation for x = 7 and y = 7

(C) The operation for x = 5 and y = 7 Fig. 21 Correct parallelization

(b) The operation for x = 5 and y = 7 Fig. 22 Goto-less two-state childish division ASM

Fig. 23 Equivalent to figure 22 The hardware design from ASM

Fig. 24 System diagram

 First hardware design

* ALU is inspired by the 74**181, PASSB is 101010 and DFFERENCE is 011001. Fig. 25 First methodical architecture

ns = ~ps&pb|ps&(rlgey|pb), ldr1 = 1, clrr2 = ~ps, incr2 = ps, ldr3 = ps, muxctr1 = ps, aluctr1[5] = ~ps, aluctr1[4] = ps, aluctr1[3] = 1, aluctr1[2] = 0, aluctr1[1] = ~ps, aluctr1[0] = ps, ready = ~ps.

Fig. 26 The 1st mixed ASM corresponding to figures 22 and 25

Fig. 27 The 2nd mixed ASM corresponding to figures 22 and 25

 Second hardware design

Fig. 28 Central architecture design

IDLE 000, INIT 001, TEST 010, COMPUTE1 011, COMPUTE2 100.

Fig. 29 Mixed ASM corresponding to figure 12 and 28

 Methodical versus central ALU architectures Central ALU What does computation? One ALU

Methodical Registers themselves or registers tied to dedicated muxes and ALUs Only one register All kinds Many Faster Higher

What ALU output connects to? What kind of register? Number of <- per clock cycle Speed Cost

Every register Enabled One Slower Lower

Homework 1: Dice game (Digital system design using VHDL) The rules of the game are as follows: (1) After the first roll of the dice, the player wins if the sum is 7 or 11. The player loses if the sum is 2, 3, or 12. Otherwise, the sum the player obtained on the first roll is referred to as a point, and he or she must roll the dice again. (2) On the second or subsequent roll of the dice, the player wins if the sum equals the point, and he or she loses if the sum is 7. Otherwise, the player must roll again until he or she finally wins or loses. The block diagram for dice game:

The algorithm flowchart and ASM chart for dice game

State graph for dice game controller:

Dice game with test bench

ASM chart for dice game test: