library IEEE; use IEEE.std_logic_1164.

all; entity register_64 is port(clk : in std_logic; clear : in std_logic; input : in std_logic_vector (63 downto 0); output : out std_logic_vector (63 downto 0) ); end entity register_64; architecture behavior of register_64 is begin -- behavior reg_64: process(clk, clear) begin if clear='1' then -- only once output <= (others=>'0'); elsif clk'event and clk='1' then output <= input after 100 ps; end if; end process reg_64; end architecture behavior; -- of register_64 library IEEE; use IEEE.std_logic_1164.all; entity register_32 is port(clk : in std_logic; clear : in std_logic; input : in std_logic_vector (31 downto 0); output : out std_logic_vector (31 downto 0) ); end entity register_32; architecture behavior of register_32 is begin -- behavior reg_32: process(clk, clear) begin if clear='1' then -- only once output <= (others=>'0'); elsif clk'event and clk='1' then output <= input after 100 ps; end if; end process reg_32; end architecture behavior; -- of register_32 library IEEE; use IEEE.std_logic_1164.all; entity madd is port(c : in s : in b : in a : in sum : out cout : out end entity madd; -- multiplying full adder stage std_logic; -- one input, think carry in std_logic; -- one input, think previous sum std_logic; -- multiplier bit std_logic; -- multiplicand bit std_logic; -- carry save sum out std_logic); -- carry save carry out

architecture circuits of madd is -- multiplying full adder stage signal ab: std_logic; -- one bit of a times one bit of b begin

ab <= a and b; -- logic could be reduced, yet probably circuit designed sum <= (ab and s and c) or (ab and not s and not c) or (not ab and s and not c) or (not ab and not s and c) after 1 ps; cout <= (ab and s) or (ab and c) or (s and c) after 1 ps; end architecture circuits; -- of madd library IEEE; use IEEE.std_logic_1164.all; entity pipemul port(clk: in a : in b : in p : out end pipemul; is -- 32 x 32 = 64 std_logic; std_logic_vector(31 std_logic_vector(31 std_logic_vector(63 bit unsigned product multiplier -- new value each rising clock downto 0); -- multiplicand downto 0); -- multiplier downto 0)); -- product

architecture circuits of pipemul is constant N : integer := 31; -- last row number constant NS : integer := 8; -- number of stages, 4 rows each stage type arr is array(0 to N) of std_logic_vector(N downto 0); signal s : arr; -- partial temp sums signal c : arr; -- partial temp carries type parr is array(0 to NS) of std_logic_vector(63 downto 0); signal pin : parr; -- pipeline register input partial product signal pout : parr; -- pipeline register output partial product type aarr is array(0 to NS) of std_logic_vector(31 downto 0); signal ain : aarr; -- pipeline register input multiplicand a signal aout : aarr; -- pipeline register output multiplicand a signal bin : aarr; -- pipeline register input multiplier b signal bout : aarr; -- pipeline register output multiplier b signal tcin : aarr; -- pipeline register input temp carry signal tcout : aarr; -- pipeline register output temp carry signal clear : std_logic := '1'; -- one time clear begin -- circuits of pipemul clear <= '0' after 10 ps; -- registers greg: for j in 0 to NS generate pregj: entity WORK.register_64 aregj: entity WORK.register_32 bregj: entity WORK.register_32 cregj: entity WORK.register_32 end generate greg; pin(0) <= (others => '0'); tcin(0) <= (others => '0'); ain(0) <= a; bin(0) <= b;

port port port port -----

map(clk, map(clk, map(clk, map(clk,

clear, clear, clear, clear,

pin(j), ain(j), bin(j), tcin(j),

pout(j)); aout(j)); bout(j)); tcout(j));

initial partial product initial temp carry changes when a or b changes put on aout, bout, pout, tcout at clk

-- pass along multiplicand and multiplier mpy: for j in 0 to NS-1 generate ain(j+1) <= aout(j); -- wiring bin(j+1) <= bout(j); -- wiring end generate mpy; -- the internal part of the multiplier is nested generate -- the four levels of madd between stages must be coded -- stages

gmaddi: for i in 0 to NS-1 generate gmaddj: for j in 0 to N-1 generate maddj1: entity WORK.madd port map (pout(i)(j+4*i), tcout(i)(j), bout(i)(4*i), aout(i)(j), s(4*i)(j), c(4*i)(j)); maddj2: entity WORK.madd port map (s(4*i)(j+1), c(4*i)(j), bout(i)(4*i+1), aout(i)(j), s(4*i+1)(j), c(4*i+1)(j)); maddj3: entity WORK.madd port map (s(4*i+1)(j+1), c(4*i+1)(j), bout(i)(4*i+2), aout(i)(j), s(4*i+2)(j), c(4*i+2)(j)); maddj4: entity WORK.madd port map (s(4*i+2)(j+1), c(4*i+2)(j), bout(i)(4*i+3), aout(i)(j), s(4*i+3)(j), tcin(i+1)(j)); end generate gmaddj; gmaddjn: for j in N to N generate -- special left side maddj1n: entity WORK.madd port map (pout(i)(j+4*i), tcout(i)(j), bout(i)(4*i), aout(i)(j), s(4*i)(j), c(4*i)(j)); maddj2n: entity WORK.madd port map ('0', c(4*i)(j), bout(i)(4*i+1), aout(i)(j), s(4*i+1)(j), c(4*i+1)(j)); maddj3n: entity WORK.madd port map ('0', c(4*i+1)(j), bout(i)(4*i+2), aout(i)(j), s(4*i+2)(j), c(4*i+2)(j)); maddj4n: entity WORK.madd port map ('0', c(4*i+2)(j), bout(i)(4*i+3), aout(i)(j), s(4*i+3)(j), tcin(i+1)(j)); end generate gmaddjn; pin(i+1)(4*i-1 downto 0) <= pout(i)(4*i-1 downto 0); -- pass previous pin(i+1)(4*i ) <= s(4*i)(0); -- new bottom product bits pin(i+1)(4*i+1) <= s(4*i+1)(0); pin(i+1)(4*i+2) <= s(4*i+2)(0); pin(i+1)(4*i+3) <= s(4*i+3)(0); pmid: for j in 1 to N generate pin (i+1)(j+4*i+3) <= s(4*i+3)(j); end generate pmid; pin(i+1)(63 downto 4*i+35) <= pout(i)(63 downto 4*i+35); end generate gmaddi; addl: entity Work.add32 port map(pout(NS)(63 downto 32),tcout(NS),'0', p(63 downto 32), open); -- connect outputs p(31 downto 0) <= pout(NS)(31 downto 0); end architecture circuits;