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Abstract: A unidirectional three-phase AC/DC converter is proposed to obtain almost unity power
factor, draw sinusoidal line currents and keep the DC-bus voltage constant. Two active switches
and two power diodes are used in each converter leg to generate a three-level PWM waveform on
the AC terminal voltages. The proposed converter has simpler circuit configuration compared with
the conventional three-level PWM converters. The classical proportional-integral voltage controller
and the hysteresis current controller are adopted in the control scheme to achieve DC-bus voltage
regulation and line-current command tracking. A neutral-point voltage compensator is used to
balance the neutral-point voltage due to load change. The validity and effectiveness of the proposed
control algorithm is verified through simulations and experimental results.
IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005 485
vdc vdc
p vsa > 0 isa p
i1 io i1 io
Da 2 vC 1
L, r Da 2
L, r vC 1
isa a C1
isa a C1
vsa Sa1 Sa 2
load
o vsa
load
i2
o
vC 2
Da1 i2
C2
vC 2
i3
n C2
a
n
a
vsa Da 2 vdc
L, r a
vdc vsa > 0 isa
isa p
p io
Sa1 Sa 2 i1 io
Da1 L, r vC 1
vC 1
Db 2 C1 isa a C1
iso vsb L, r Sa 2
b o vsa
load
load
isb o
i2 i2
Sb1 Sb 2
vC 2
Db1 vC 2
C2
C2
i3
vsc Dc 2 n
L, r
c n
isc
Sc1 Sc 2 b
Dc1
vdc
b
vsa < 0 isa p
io
Fig. 1 Proposed unidirectional AC/DC converter v
L, r C1
a Single-phase circuit configuration
b Three-phase circuit configuration isa a C1
vsa Sa1
load
o
switch Sa1 and diode Da1 is equal to the DC-bus voltage. i2
No clamping capacitor or diode is needed in the proposed vC 2
C2
single-phase converter. A unipolar PWM voltage waveform
is generated on the voltage vao. Figure 1b shows the system n
configuration of the proposed three-phase three-level AC/ c
DC converter. It consists of three converter legs, three boost
inductors on the AC side and two capacitors in series on the vdc
DC side. Two power switches and two fast recovery diodes vsa < 0 isa p
are used in each leg. The main functions of the proposed io
vC 1
three-phase converter are current harmonic elimination, L, r
neutral-point voltage balance, unity power factor and DC- a
isa C1
link voltage regulation. Two control loops in the system vsa o load
achieve DC-link voltage regulation and line-current track-
ing. The hysteresis comparators in the inner control loop i2
track the line-current commands. The proportional-integral vC 2
Da1 C2
controller in the outer control loop maintains the DC-link
i3
voltage constant. n
d
2.2 Principle of operation
There are two independent active switches in the proposed Fig. 2 Operating states of proposed single-phase AC/DC converter
converter leg. Unipolar PWM voltage waveforms can be a State 1
generated on the AC terminal to neutral-point voltages. b State 2
c State 3
Before analysis of the proposed converter the following
d State 4
assumptions are made: the power switches are ideal; the
supply voltage is constant during one switching period;
Sxy ¼ 1 (or 0) if active switch Sxy is turned on (or off),
x ¼ aBc, y ¼ 1B2; and the capacitor voltages on the DC (vL ¼ vsavdc/2o0). Figure 2b gives the equivalent circuit of
side are equal (vC1 ¼ vC2 ¼ vdc/2). In each converter leg there second operating state. The line current flows through the
are four operation states shown in Fig. 2 to generate three body diode of active switch Sa1 and active switch Sa2. The
different voltage levels. Figure 2a gives the equivalent circuit AC-side voltage vao equals 0. The boost inductor voltage
of the first operating state. In this state, positive line current equals vsa. The line current isa is linearly increasing if the
flows through the body diode of active switch Sa1 and mains voltage vsa is positive. Figure 2c shows the equivalent
diode Da2 to charge capacitor C1. The AC-side voltage third operating state. The negative line current flows
vao equals vdc/2. The line current isa is linearly decreasing through switch Sa1 and the body diode of switch Sa2 to
in this state because the boost inductor voltage is negative obtain AC-side voltage vao ¼ 0. The line current is linearly
486 IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005
decreasing because vL ¼ vso0. The equivalent circuit of the Based on (1)–(6) the system equations of the proposed
fourth operating state is given in Fig. 2d. The line current converter can be rewritten as
flows through capacitor C2 and Da1 to generate AC 2 3
disa
terminal voltage vao ¼ vC2. The negative line current will 6 dt 7
6 disb 7
charge capacitor C2. The boost inductor voltage equals 6 7
6 dt 7
6 di 7
vsa+vC240 such that the line current is linearly increasing. 6 sc 7
6 dt 7
In state 4 only one diode Da1 is conducting as shown 6 7
6 dvC1 7
6 dt 7
in Fig. 2d. However, there are two devices conducting in 4
dvC2
5
states 1–3 (Fig. 2a–2c). dt
negative phase voltage, states 3 and 4 are selected to 1 C2Sa1 ½1 signðvsa Þ 1 C2Sb1 ½1 signðvsb Þ 1 C2Sc1 ½1 signðvsc Þ
generate voltage levels 0 (high voltage level) and vdc/2 (low 3
voltage level) on the AC terminal voltage, respectively. 1 L Sa2 signðvsa Þ 1 LSa1 ½1 signðvsa Þ
7
7
During each half cycle of mains voltage, the high voltage 1 L Sb2 signðvsb Þ 1 LSb1 ½1 signðvsb Þ 7
7
level on the AC side is used to decrease the line current and 7
1 L Sc2 signðvca Þ 1 L Sc1 ½1 signðvsc Þ 7
7
a low voltage level is adopted to increase line current. The 1 1 7
7
RC 5
same analysis of phase-b and phase-c can be achieved 1 RC 1
according to the same analysis. The system behaviour of the 1 RC2 1RC2
IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005 487
(1−Sa1)[sign(vsa )−1]−vC 2
i sa
vsa r L
(1−Sa2)sign(vsa)vC 1
(1−Sb1)[sign(vsb )−1]−vC 2
i so i sb
vsb r L
(1−Sb2)sign(vsb)vC 1
(1−Sc1)[sign(vsc )−1]−vC 2
i sc
v sc r L
(1−Sc 2)sign(vsc)vC 1
i1
(1-Sa2)sign(vsa)isa
(1-Sb2)sign(vsb)isb
(1-Sc 2)sign(vsc)isc
[Sa 2 sign(vsa)+
Sa1(1-sign(vsa))]isa
C1
[Sb2 sign(vsb)+ vC 1
Sb1(1-sign(vsb))]isb
R
(1-Sa1)[1-sign(vsa)]isa
(1-Sb1)[1-sign(vsb)]isb
(1-Sc 1)[1-sign(vsc)]isc
[Sc 2 sign(vsc)+ i2
Sc1(1-sign(vsc)]isc
vC 2
C2
i3
used to achieve an eight-bit signal which is input to the in the next line period. Therefore the capacitor voltage VC1 is
digital signal processor. The digital signal processor compensated. The resultant line-current commands are
generates three balanced sinusoidal waves using a look-up illustrated as
table with the input eight-bit digital signal. These balanced 2 3 2 3 2 3
isa ðtÞ Is sin ot 1
sinusoidal waves are synchronised to three-phase source 4 isb ðtÞ 5 ¼ 4 Is sinðot 2p=3Þ 5 þ Inpc 4 1 5
voltages and expressed as
2 3 2 3 isc ðtÞ Is sinðot þ 2p=3Þ 1
ea ðtÞ sin ot 2 3
4 eb ðtÞ 5 ¼ 4 sinðot 2p=3Þ 5 ð10Þ Is sinðotÞ þ Inpc
ec ðtÞ sinðot þ 2p=3Þ ¼ 4 Is sinðot 2p=3Þ þ Inpc 5 ð13Þ
Is sinðot þ 2p=3Þ þ Inpc
Input-current references are calculated by multiplying the
amplitude of the input-current commands and the gener-
ated unit sinusoidal waves 3.3 Line-current command tracking
2 3 2 3 2 3 Hysteresis current comparators track the input-current
isa ðtÞ ea ðtÞ Is sin ot
4 isb ðtÞ 5 ¼ Is 4 eb ðtÞ 5 ¼ 4 Is sinðot 2p=3Þ 5 references. The appropriate PWM generator obtains the
ð11Þ switching signals for the power switches. The line-current
isc ðtÞ ec ðtÞ Is sinðot þ 2p=3Þ errors between the measured line currents and the current
commands are sent to the hysteresis comparators to
3.2 Neutral-point voltage compensation generate the proper PWM signals for active switches. Based
To balance the neutral-point voltage under load variation a on the operation states shown in Fig. 2, there are three
voltage compensator is used in the control scheme to voltage levels vdc/2, 0 and vdc/2 generated in each converter
compensate the neutral-point voltage. This additional leg. One high voltage level and one low voltage level can be
current for neutral-point balance is given as selected during the positive and negative half cycle of phase
voltage to track the line current command. During the
Inpc ¼ K½VC2 VC1 ð12Þ
positive half cycle, high voltage levels vdc/2 and low voltage
where VC1 and VC2 are average voltages across capacitors C1 level 0 are generated on the AC terminal to neutral-point
and C2, respectively, and K is a small gain of the neutral- voltage. During the negative half cycle, high voltage level 0
point voltage compensator. To avoid a large DC term in the and low voltage level vdc/2 are generated on the AC side
line current command due to unbalance neutral-point to control the line current. The high voltage level is adopted
voltage, a limiter can be placed after the neutral-point to decrease the line current and low voltage level is used to
voltage compensator. If the DC capacitor voltage VC2 is increase the line current. Figure 4a shows the source
greater than VC1 , then a small DC value is added to the line- voltage, line current, PWM signals and AC-side voltage for
current command. Capacitor voltage VC1 will be increased each converter leg where x ¼ a, b, c. Figure 4b gives the
488 IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005
vsx power switch shown in Fig. 4b are expressed as
i*sx
i*sx+h Sa1 ¼ signðvsa Þ hysðDisa Þ ð14Þ
Sa2 ¼ signðvsa Þ hysðDisa Þ ð15Þ
isx i*sx −h
Sb1 ¼ signðvsb Þ hysðDisb Þ ð16Þ
Sb2 ¼ signðvsb Þ hysðDisb Þ ð17Þ
sign(vsx ) 1
0 Sc1 ¼ signðvsc Þ hysðDisc Þ ð18Þ
hys(isx ) 1
0 Sc2 ¼ signðvsc Þ hysðDisc Þ ð19Þ
1
Sx 1 0 where
1
Sx 2 1; ifDisx 4h
0 hysðDisx Þ ¼ ð20Þ
vdc /2 0; ifDisx o h
vxo 0
−vdc /2 1; if vsx 40
signðvsx Þ ¼ ð21Þ
a 0; if vsx o0
VC 2 K limiter
Is isa hys(isa)
i*sa isa
v*dc PI
isb Sa 2
IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005 489
vsa vsa vsb vsc
200V
0V
20A 50V
0A
isa isb isc
isa
10ms
vao
200V
0V
5ms
a
a
vsb
200V
0V isa isb isc
20A
0A
isb 10A
0A
Sb1 20V
0V
Sb 2 20V
0V iso
10ms 0A
v bo
200V
0V
5ms
b
b
vsc 200V
vC 1
0V 5V
20A
200V
0A
isc
vC 2
5V
20V 200V
Sc1
0V
20V
Sc 2
0V vC 1+vC 2 5V
10ms 400V
vco 200V
0V 10ms
c
c Fig. 7 Simulated results of proposed converter
Fig. 6 Simulated results of phase voltage, line current, PWM a Three-phase voltage and line current
signals and AC-side voltage b Three-phase current and line neutral current
a Converter leg a c Capacitor voltages on dc side
b Converter leg b
c Converter leg c
isa
a
vsb
isb vsb
vsc
isb
isc
vbo
IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005 491
vsa vC1
i sa
vsb vC2
isb
Io
vsc
isc
load change
a
Fig. 12 Measured results of the two capacitor voltages and load
vsa vsb vsc current from 3 to 5 A output load change
vC1, vC2 20 V/div.; Io 3 A/div.; time 20 ms/div.
5 Conclusions
492 IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005
12 Sinha, G., and Lipo, T.A.: ‘A four-level rectifier-inverter system 14 Rodriguez, J., Lai, J.-S., and Peng, F.-Z.: ‘Multilevel inverters: a
for drive applications’, IEEE Ind. Appl. Mag., 1998, 4, (1), survey of topologies, controls and applications’, IEEE Trans. Ind.
pp. 66–74 Electron., 2002, 49, (4), pp. 724–738
13 Lin, B.R., and Yang, T.Y.: ‘Single-phase half-bridge rectifier with 15 Meynard, T.A., Foch, H., Thomas, P., Courault, J., Jakob, R., and
power factor correction’, IEE Proc. – Elect. Power Appl., 2004, 151, Nahrstaedt, M.: ‘Multicell converters: basic concepts and industry
(4), pp. 443–450 applications’, IEEE Trans. Ind. Electron., 2002, 49, (5), pp. 955–964
IEE Proc.-Electr. Power Appl., Vol. 152, No. 3, May 2005 493