Birla Institute of Technology & Science, Pilani Work-Integrated Learning Programmes Division First Semester 2011-2012 Course Handout

Course No. Course Title Instructor : IS ZC351 : Computer Organization & Architecture : G. Geethakumari

Course Description Overview of logic design; Instruction set architecture; Assembly language programming; Pipelining; Computer Arithmetic; Control unit; Memory hierarchy; Virtual Memory; Input and output systems; Interrupts and exception handling; Implementation issues; Case Studies. Scope and Objectives This course aims at understanding the important components of a computing system, how these components are interrelated. Primarily focus on Memory system, ALU, I/O systems, Control unit and Interconnection structures (e.g. Buses). Also it attempts to look at the problems and methods of designing computers like pipelining, RISC architectures, and parallel processing architectures. The treatment on the architecture being general, an emphasis on Intel x86. Prescribed Text Books T1. Stallings William, Computer Organisation & Architecture, Pearson Education, 8th Ed., 2010.

Reference Books R1. R2. C Hamacher, Z Vranesic and S Zaky, Computer Organization by McGrawHill, 5th Ed. 2002 Hennenssy & D.A. Patterson, Computer Organization & Design, Morgan Kaufmann 4th Ed., 2009

IS ZC351

(Course Handout)

First Semester 2011-2012

Page 2

Plan of Self Study

Week No. 01-02

Topics Computer Organization vs. Computer Architecture, Structure and Functions of various components of a computer system, History of Computers, Intels 80x86 Architecture and Organization, Computer Performance parameters and assessment Top level view of computer function, Instruction fetch and execution, Interrupts and I/O functions, Interconnection of various components of a computer system, Bus Structure and Bus design principles (e.g. PCI Bus) Computer Memory System Overview, Memory hierarchy, Cache Memory Organization and Design, Performance measurement of two level memory system. Semiconductor Main Memory (RAM, ROM, PROM, EPROM etc.), External Memory (Magnetic Disk, Magnetic Tape, Optical Memory), RAID I/O Modules and Organization, I/O Techniques: Interrupt driven I/O, Programmed I/O (Memory mapped I/O, Isolated I/O), Direct Memory Access (DMA), I/O Channels and Processors Arithmetic and Logic Unit, Data RepresentationInteger & Floating Point Representation (IEEE-754) and Arithmetic Operations, Addition, Subtraction, Multiplication, Booths Multiplication Algorithm, Arithmetic Operation on floating point data.

Learning Objectives To understand the various sub systems, their functionality, and performance measurement metrics of a computer system. To understand the organizational and architectural aspects of a computer system with an example of 80x86.

Reference to Textbook Ch.1 [1.1, 1.2] Ch.2 [2.1,2.2,2.3,2.5]

03

04-06

To understand the top level view of a computer system and information/data flow among various components. How Buses provide a path to data flow among various components of a computer system with an example of standard Bus structures. To understand the memory hierarchy of a computer system. Too gain the knowledge of different types of memory and their characteristics (e.g. cost, size, design, access speed, organization etc.) used in a typical computer

Ch.3 [31.-3.5]

Ch.4 [4.1-4.4] Appendix 4A Ch.5 [5.1-5.3] Ch.6 [6.1-6.4]

07

08

To understand the concept of I/O modules and its requirement to interconnect the external devices with computer system. Commonly used I/O techniques and their comparative performance analysis. To understand how the data is represented inside a computer. How ALU is designed to perform basic Arithmetic and Logic operations on the data.

Ch.7 [7.1-7.6]

Ch.9 [9.1-9.5]

Syllabus for Mid-Semester Test (Closed Book): Topics in Week No. 1 to 8

IS ZC351

(Course Handout)

First Semester 2011-2012

Page 3

Plan of Self Study

Week No. 09-10

Topics Instruction Set characteristics and functions, Intels x86 ISA, Instruction Addressing Modes, Intels x86 Addressing Modes and Instruction Formats

Learning Objectives

11-12

Processor Organization, RISC and CISC Architectures, Instruction Cycle, Instruction Pipelining, Register Optimization, RISC pipelining, Pipeline Conflict/Hazards and Efficiency Issues, Intels x86 Pipelining.

13-14

Instruction-level parallelism and Superscalar Processors and Design Issues, P-4 Super Scalar Pipeline Micro Operations, Design Concepts, Hardwired and MicroProgrammed Control Design Issues, Micro Instruction Sequencing Methods

To understand the concept of an instruction and program. The basic elements of an instruction and various instruction formats with relative performance. The Intel architecture is the reference for the whole discussion. To understand the instruction Ch.12 [12.1-12.5] processing steps To understand Ch.13 [13.1-13.5] how various instruction processing steps can be overlap (called as pipelining) to increase the throughput of a computer. The hardware and software requirements for pipelining and performance limitation factors for it. To gain the knowledge of Ch.14 [14.1-14.3] working principle of modern processors that uses instruction level parallelism. To understand the concept of micro-operations, their execution and sequencing process with the help of control unit design.

Chapter References from Text Book Ch.10 [10.1-10.5] Ch.11 [11.1-11.4]

15-16

Ch. 15 [15.1-15.3] Ch. 16 [16.1-16.3]

Syllabus for Comprehensive Exam (Open Book): All topics given in Plan of Self Study

Evaluation Scheme: EC Evaluation Component & No. Type of Examination EC-1 Assignment/Quiz EC-2 Mid-Semester Test (Closed Book)* EC-3 Comprehensive Exam (Open Book)*

Duration TBA 2 Hours 3 Hours

Weightage 10% 30% 60%

Day, Date, Session,Time TBA Sunday, 04/09/2011 (FN)* 10 AM 12 Noon Sunday, 30/10/2011 (FN)* 9 AM 12 Noon

* Legend: AN: AfterNoon Session; FN: ForeNoon Session; TBA : To be announced Closed Book Test: No reference material of any kind will be permitted inside the exam hall. Open Book Exam: Use of any printed / written reference material (books and notebooks) will be permitted inside the exam hall. Loose sheets of paper will not be permitted. Computers of any kind will not be allowed inside the exam hall. Use of calculators will be allowed in all exams. No exchange of any material will be allowed. Instructor-in-Charge