The ARM Architecture

ARM Architecture
INTRODUCTION The most important part in our project is the microprocessor design. The design passes through many steps until it reaches the final form. The project is an ARM processor that is constructed from the following components: Arithmetic Logic Unit Booth multiplier Barrel shifter Control unit Register file

PROGRAM STATUS REGISTER It contains the processor flags (Z, S, V and C). The modes bits also exist in the program status register in addition to the interrupt and fast interrupt disable bits.

SOME SPECIAL REGISTERS Some registers are used like the instruction register, memory data read and write register and memory address register

PRIORITY ENCODER The encoder is used in the multiple load and store instruction to indicate which register in the register file to be loaded or stored MULTIPLEXERS Many multiplexers are used to control the operation of the processor buses

The ARM Architecture ARITHMETIC LOGIC UNIT (ALU) The ALU has two 32-bits inputs. The first comes from the register file The other comes from the shifter. ALU outputs modify the status register flags. The V-bit output goes to the V flag as well as the Cout goes to the C flag. While the most significant bit actually represents the S flag, the ALU output is NORed to get the Z flag. The entity representation of the ALU is shown in figure below.

The ALU has a 4-bit function bus that allows up to 16 opcode to be implemented. The different opcodes and their corresponding arithmetic and logic operations are shown in table (2-1). The ALU test bench simulation results are shown in figure (4-3).

Figure (4-3): ALU simulation results 4.3) Booth multiplier The multiplier has three 32-bit inputs. All the inputs come from the register file. The multiplier output is only the 32 least significant bits of the product. The entity representation of the multiplier is shown in figure (4-4). The multiplication starts whenever the start input goes active. The output fin goes high when finishing.

The ARM Architecture

Figure (4-4): Multiplier entity 4.3.1) Booth algorithm The multiplier is implemented using the modified booth algorithm. The multiplier is scanned sequentially from right to left. In this case, however, three adjacent bits are examined during each step of the procedure. According to the value of the three bits, the multiplicand is added to or subtracted form the accumulated partial product and the later is then shifted. Figure (4-5) shows a version of this algorithm to multiply two 32-bits fractions using the logic circuit of Figure (4-6).

Figure (4-5): The Booth's algorithm Intermediate results are stored in the accumulator-multiplier register pair A, Q. An extra cell Q(32) is appended to the right most end of Q to

The ARM Architecture facilitate the triple-bit inspection process.

Figure (4-6): Multiplier logic circuit Booth algorithm is an interesting multiplication algorithm for twoscomplement numbers. It treats positive and negative numbers uniformly. Furthermore, runs of 0s or 1s in the multiplier are skipper over without any addition or subtraction being performed, thereby making possible faster multiplication. Figure (4-7) shows the simulation results for the multiplier test bench. It is clear that the multiplication finishes only in 16 clock cycle.

Figure (4-7): Multiplier simulation results

The ARM Architecture 4.4) Barrel shifter The barrel shifter has a 32-bit input to be shifted. This input is coming from the register file or it could be immediate data. The shifter has other control inputs coming from instruction register. Shift field in the instruction controls the operation of the barrel shifter. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right). The amount by which the register should be shifted is contained in an immediate field in the instruction or it could be the lower 6 bits of a register in the register file. Figure (4-8) shows the entity representation of the barrel shifter.

Figure (4-8): Shifter entity The shift_val input bus is 6-bits allowing up to 32 bit shifts. The shift_typ indicates the required shift type for 00, 01, 10, 11 are corresponding to logical shift left, logical shift right, arithmetic shift right and rotate right respectively. The barrel shifter is mainly constructed with multiplexers. Figure (410) shows the logical circuit for the barrel shifter. The test bench simulation of the shifter is also shown in Figure (4-9).

The ARM Architecture

Figure (4-9): Shifter simulation results

The ARM Architecture

Figure (4-10): Shifter logic circuit 4.5) Control unit For any microprocessor, control unit is the heart of the system. It is responsible for the system operation and so the control unit design is the most important part in the hole design. Control unit is usually a pure combinational circuit. In our design, the control unit is implemented by simple state machine. The processor timing is also included in the control unit. Figure (4-11) shows the state machine that implements the control unit. Signals from the control unit are connected to every component in the processor to supervise its operation. The value of those signals for each instruction at every state is explained in Appendix A.

The ARM Architecture

Figure (4-11): Control unit state machine 4.6) ARM7 Functional Diagram The last thing that needs to be explained is how the ARM can be used and how will the chip appear. Figure (4-12) shows the functional block diagram of our ARM processor. The different signals that interface with the processor are input, output or supervisory signals that can be used to control the ARM operation.

The ARM Architecture

Figure (4-12): ARM Functional Diagram