IJRREST: International Journal of Research Review in Engineering Science and Technology (ISSN 2278- 6643) | Volume-1 Issue-2, September

2012

Estimation of Clock Skew Using VHDL

*Vaishali Gupta, *Suvarna.na, *Naveen Jain , **Sarita Bhan *JSS Mahavidyapeetha, Noida, U.P., India **MVN University, Palwal . Haryana, India

______________________________________________________________________________ ABSTRACT
The clock signal has always been a matter of concern for most of the highspeed functions of the synchronous integrated circuits as it decides the speed regularities. To reduce the irregularities of this signal, the clock skew is one of the major constraints to be taken care of. In this paper, an efficient technique for the estimation of this clock skew has been introduced and VHDL has been used to verify its functionality. The clock skew estimation has been used to pave a way for reducing the speed irregularities of the integrated circuit due to clock skew. Key Words: Clock skew, RTL Design, Clock distribution networks, clock scheduling, synchronous circuit.

2. CIRCUIT DESIGN
As our aim is to estimate the clock skew, we need to have a sequential circuit which employs clock in different parts of circuits with certain time delay; hence we used a circuit which included four D Flip Flops with clock distribution emerging in clock skew issue as shown in the Figure 1. In our designed circuit we have an example of sequentially-adjacent flip flops, where a local routing resource has been used to route the clock signal. An appreciable clock skew can be seen in this circuit. It can be noticed in Figure 1 that all flip flops are clocked at the same edge, but the arrival time of the edge is different at each flip flop. Figure 2 indicates an example of the clock skew for the circuit shown in Figure 1. [3]

1. INTRODUCTION
Clock distribution in high-speed digital systems is an exigent problem overwhelming a rising fraction of assets for example design time, power, wiring, and skew, which is the key parameter of interest. First of all, the issues related to clock skew and its estimation in a digital circuit or network comes in our mind. Clock skew is the difference in clock arrival time between different components across a chip. Due to this difference in clock arrival time, delay comes into picture in getting the output of each circuit, which results in speed irregularity of the digital system. [1] In this paper, we introduce a synchronous counter circuit in which four D Flipflops are used, driven with the same clock and in this synchronous circuit we estimate the clock skew using VHDL(Very High Speed Integrated Circuits Hardware Descriptive Language). This paper is organized as follows. Section II describes the circuit design .Section III consists the implementation of the circuit in VHDL. Section IV shows the analysis and simulation results of the circuit. Section V describes the conclusion of our analysis.

Figure 1: Circuit Diagram

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IJRREST: International Journal of Research Review in Engineering Science and Technology (ISSN 2278- 6643) | Volume-1 Issue-2, September 2012

different outputs Q1,Q2,Q3 and Q4 respectively, however all these sequential elements are fed with single clock pulse input CLK which is designated as CLK1,CLK2,CLK3 and CLK4 at the clock inputs of these flip flops. In the synthesis part we can see the RTL schematic for the designed VHDL code shown in Figure 3. By this RTL schematic the designed circuit can also be justified. And the simulation part shows the simulated output waveform for the designed VHDL code shown in figure 4. It is clear from Figure 3 that assumed circuit and the circuit designed by the software are alike whose functional behaviour is verified using the simulation tool. The input-output waveforms of designed circuit as obtained by the simulator tool are shown in Figure 4 which verifies the functional behaviour of the designed circuit.

Figure 2: Clock Arrival Time Fluctuations in the Circuit of Figure 1 We see in Figure 2, there is a short delay between the clock origin, CLK and the clock arriving at four flip flops i.e. CLK1, CLK2, CLK3 and CLK4. This is also clear that the clock skew varies from one node to another node depending upon the way of estimation as the clock with clock input CLK1 lies closer to clock origin, CLK as compared to the clock input CLK4 of fourth flip flop. The waveform design shown in Figure 2 presents a clear idea of clock skew and its variation which is further subjected to change with change in circuit. On the basis of this short delay difference between the respective clock inputs, clock skew can be short delay difference between the respective clock inputs, clock skew can be estimated which forms the base of this paper.

3. CIRCUIT IMPLEMENTATION
The circuit implementation for any design justifies its validity for the observed results. This circuit has been implemented using the hardware descriptive language, VHDL (Very High Speed Integrated Circuit Hardware Description Language). The software used for estimation of clock skew in this designed circuit is XILINX ISE Simulator version 10.1. The designed circuit estimation is done by implementation, synthesis and simulation on XILINX ISE simulator. For implementation part we have designed a circuit as shown in Figure 1 using VHDL code in behavioural style of modelling. The device used for the synthesis purpose is XC2S15 from Spartan series with package CS144 and speed grade 6. In this VHDL code we introduced four D Flip Flops having different inputs D1,D2,D3 and D4 with Figure 3: RTL schematic

Figure 4: Simulated Output Waveform

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IJRREST: International Journal of Research Review in Engineering Science and Technology (ISSN 2278- 6643) | Volume-1 Issue-2, September 2012

4. ANALYSIS AND RESULT

The analyses of the results obtained from the synthesized circuit have emerged as an imperative idea pertaining to the estimation of clock skew. The estimated results of the clock skew are shown in the Table 2 on the basis of the timing paths of the arrival of the clock signals shown in Table 1 as listed below:

5. CONCLUSION
In order to manage with the increasingly significant speed irregularities due to clock skew in high seed synchronous circuits, we propose a technique for the estimation of clock skew using VHDL. For the clock skew estimation, VHDL code is used to design the circuit. Experimental results from XILINX ISE simulator version 10.1 validate the effectiveness of our approach.

6. REFERENCES
[1]Hashimoto, "T. Yamamoto and H. Onodera, "Statistical analysis of Clock Skew Variation in H-tree Structure Masanori, Proceedings of ISQED, IEEE, 2005. [2]K. Ki. Ryoo, J. WH Chong and H. Shin, "Skew optimization by combining tree-based and graph-based techniques for high performance clock routing," IEEE, 1999. [3]Microsemi, Clock Skew and Short Paths Timing, pp.1 to pp.3. [4]R. Saeidi and N. Masoumi, Clock Skew Reduction Using Link Region Technique, IEEE, 2007. [5]www.xilinx.com/technicalnotes

Table 1 Source Setup to CLK(edge) Estimated Clock Skew Nil 0.804 0.804 0.804

D1 D2 D3 D4

1.396 2.200 2.200 2.200 Table 2

In Table 1 we can verify our estimated clock skew which is calculated in Table 2. Table 1 is the report output of the Timing analyser achieved from the designed circuit simulation in ISE Simulator. In Table 1 we can see that the clock arrival time (setup to clock) for D1 differs with clock arrival time for D2, D3 and D4 and this difference in clock arrival time is our estimated clock skew.

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