Académique Documents
Professionnel Documents
Culture Documents
Provides the overall context and framework for the development cycle of FPGAs. This course will arm with the proper planning techniques, strategy, and FPGA tool flow to get up and designing an FPGA design. The flow will take from behavioral specification to tuning specifications for the FPGA, synthesis, verification, and onto implementation and download. Throughout the design cycle, the various tools within the Project Navigator tool are introduced. This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase overall Verilog proficiency and enhance the FPGA optimization. This course covers Verilog 1995 and 2001. Use the ISE software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow. This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O Planner, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints. Provides an understanding to be able to create more efficient designs. This course can help to fit designs in a smaller FPGA or lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, will also be able to create design faster, shorten development time, and lower development costs.
XILINX EXAM
XILINX
180 MINUTES
SECTION A: 25 SECTION B: 10
TARGET AUDIENCE
Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the ISE design tools. Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs. Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs. FPGA designers with intermediate knowledge of HDL and some experience with the Xilinx ISE software tools.
COURSE DURATION
COURSE STRUCTURE
Module Code
Xilinx-01 Xilinx-02 Xilinx-03 Xilinx-04 Prep Xilinx Exam ISE Design Tool Flow Designing with Verilog Essentials of FPGA Design for Performance Exam Preparation Xilinxs IC Design Examination
Module Title
Days
1 4 2 3 1 1
Total Days
12
LEARNING OUTCOME
After completing this comprehensive training, you will have the necessary skills to: Outline a complete project planning process Create a new Project Navigator project in the ISE software Access and modify Xilinx Synthesis Technology (XST) synthesis options Assign pin locations using the I/O Planner Enter global clock constraints using the Xilinx Constraints Editor Simulate a design using the ISim Simulator Write RTL Verilog code for synthesis Write Verilog test fixtures for simulation Create a Finite State Machine (FSM) by using Verilog Target and optimize Xilinx FPGAs by using Verilog Use enhanced Verilog file I/O capability Run a timing simulation by using Xilinx Simprim libraries Create and manage designs within the ISE software design environment Download to the evaluation demo board
Take advantage of the primary features of the 7 series FPGAs Use the Xilinx Project Navigator to implement and simulate an FPGA design Read reports and determine whether your design goals were met Use the Clocking Wizard to create MMCM instantiations Use the I/O Planner to make good pin assignments Use the Xilinx Constraints Editor to enter global timing constraints Describe the architectural features of the 7 series FPGAs Create and integrate cores into your design flow by using the CORE Generator interface Describe the clocking features of the 7 series FPGAs and how they can be used to improve performance Increase performance by duplicating registers and pipelining Increase system reliability by adding an appropriate synchronization circuit Describe different synthesis options and how they can improve performance Describe a flow for obtaining timing closure Pinpoint design bottlenecks by using timing reports Apply advanced timing constraints to meet your performance goals Use advanced implementation options to increase design performance
Lab Descriptions: Lab 1: Projects in the Project Navigator Gain comprehensive hands-on experience with the HDL flow in the ISE software. Create a new project, add source files, synthesize a design, and use the error navigation feature to fix your HDL code. Lab 2: Synthesis Options Modify XST synthesis properties, read synthesis reports to compare the synthesis results with the implemented results, and use the schematic viewer to evaluate the design. Lab 3: I/O Pin Planning Review demo board documentation to determine the finished pinout and use the PlanAhead tool to assign pin location constraints and set other pin attributes. Lab 4: ISim Simulator Use the project navigator to view an HDL testbench, use the ISim Simulator to run simulation view output waveforms, add signals, and change their viewed format.
Lab Descriptions:
The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.