DOWNLINK

4.615 ms (1 TDMA Frame) 577 us MS1 OMCR --> BCC TS0 TDMA Frame 0 TDMA Frame 1 TDMA Frame 2 TDMA Frame 3 TDMA Frame 4 TDMA Frame 5 TDMA Frame 6 TDMA Frame 7 TDMA Frame 8 TDMA Frame 9 TDMA Frame 10 TDMA Frame 11 TDMA Frame 12 TDMA Frame 13 TDMA Frame 14 TDMA Frame 15 TDMA Frame 16 TDMA Frame 17 TDMA Frame 18 TDMA Frame 19 TDMA Frame 20 TDMA Frame 21 TDMA Frame 22 TDMA Frame 23 TDMA Frame 24 TDMA Frame 25 TDMA Frame 26 TDMA Frame 27 TDMA Frame 28 TDMA Frame 29 TDMA Frame 30 235.365 ms 120 ms FCH SCH BCCH BCCH BCCH BCCH PAGCH PAGCH PAGCH PAGCH FCH SCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH FCH SCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH FCH SDC TS1 SDCCH(0) SDCCH(0) SDCCH(0) SDCCH(0) SDCCH(1) SDCCH(1) SDCCH(1) SDCCH(1) SDCCH(2) SDCCH(2) SDCCH(2) SDCCH(2) SDCCH(3) SDCCH(3) SDCCH(3) SDCCH(3) SDCCH(4) SDCCH(4) SDCCH(4) SDCCH(4) SDCCH(5) SDCCH(5) SDCCH(5) SDCCH(5) SDCCH(6) SDCCH(6) SDCCH(6) SDCCH(6) SDCCH(7) SDCCH(7) SDCCH(7) TCH TS2 TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F SACCH TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F IDLE TCH/F TCH/F TCH/F TCH/F TCH/F MS2/ MS3 TCH TS3 TCH TS4 TCH TCH TCH TCH TCH TS5 TCH TCH TCH TCH TCH TS6 TCH TCH TCH TCH TCH TS7 TCH TCH TCH TCH ->>>>

These TSs (0 -> 7) will take the foll. Forms each 4.615 ms

TCH/H TCH/H TCH/H TCH/H TCH/H

TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H SACCH for MS2 TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H SACCH for MS3 TCH/H TCH/H TCH/H TCH/H TCH/H

TDMA Frame 31 TDMA Frame 32 TDMA Frame 33 TDMA Frame 34 TDMA Frame 35 TDMA Frame 36 TDMA Frame 37 TDMA Frame 38 TDMA Frame 39 TDMA Frame 40 TDMA Frame 41 TDMA Frame 42 TDMA Frame 43 TDMA Frame 44 TDMA Frame 45 TDMA Frame 46 TDMA Frame 47 TDMA Frame 48 TDMA Frame 49 TDMA Frame 50 TDMA Frame 51 TDMA Frame 52 TDMA Frame 53 TDMA Frame 54 TDMA Frame 55 TDMA Frame 56 TDMA Frame 57 TDMA Frame 58 TDMA Frame 59 TDMA Frame 60 TDMA Frame 61 TDMA Frame 62 TDMA Frame 63 TDMA Frame 64 TDMA Frame 65 TDMA Frame 66 TDMA Frame 67 TDMA Frame 68 TDMA Frame 69 TDMA Frame 70 TDMA Frame 71

SCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH FCH SCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH IDLE FCH SCH BCCH BCCH BCCH BCCH PAGCH PAGCH PAGCH PAGCH FCH SCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH FCH

SDCCH(7) SACCH(0) SACCH(0) SACCH(0) SACCH(0) SACCH(1) SACCH(1) SACCH(1) SACCH(1) SACCH(2) SACCH(2) SACCH(2) SACCH(2) SACCH(3) SACCH(3) SACCH(3) SACCH(3) IDLE IDLE IDLE SDCCH(0) SDCCH(0) SDCCH(0) SDCCH(0) SDCCH(1) SDCCH(1) SDCCH(1) SDCCH(1) SDCCH(2) SDCCH(2) SDCCH(2) SDCCH(2) SDCCH(3) SDCCH(3) SDCCH(3) SDCCH(3) SDCCH(4) SDCCH(4) SDCCH(4) SDCCH(4) SDCCH(5)

TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F SACCH TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F IDLE TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F SACCH TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F

TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H SACCH for MS2 TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H SACCH for MS3 TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H SACCH for MS2 TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H

TDMA Frame 72 TDMA Frame 73 TDMA Frame 74 TDMA Frame 75 TDMA Frame 76 TDMA Frame 77 TDMA Frame 78 TDMA Frame 79 TDMA Frame 80 TDMA Frame 81 TDMA Frame 82 TDMA Frame 83 TDMA Frame 84 TDMA Frame 85 TDMA Frame 86 TDMA Frame 87 TDMA Frame 88 TDMA Frame 89 TDMA Frame 90 TDMA Frame 91 TDMA Frame 92 TDMA Frame 93 TDMA Frame 94 TDMA Frame 95 TDMA Frame 96 TDMA Frame 97 TDMA Frame 98 TDMA Frame 99 TDMA Frame 100 TDMA Frame 101

SCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH FCH SCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH FCH SCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH PAGCH IDLE

SDCCH(5) SDCCH(5) SDCCH(5) SDCCH(6) SDCCH(6) SDCCH(6) SDCCH(6) SDCCH(7) SDCCH(7) SDCCH(7) SDCCH(7) SACCH(4) SACCH(4) SACCH(4) SACCH(4) SACCH(5) SACCH(5) SACCH(5) SACCH(5) SACCH(6) SACCH(6) SACCH(6) SACCH(6) SACCH(7) SACCH(7) SACCH(7) SACCH(7) IDLE IDLE IDLE

TCH/F TCH/F TCH/F TCH/F TCH/F IDLE

TCH/H TCH/H TCH/H TCH/H TCH/H SACCH for MS3

so, each TS (e.g.SDCCH) will repeat after 4.615 ms - 577 us

26 Frame Traffic Channel MF 51 Frame Control Channel MF 51 Frame Control Channel MF Every TCH & SDCCH has one SACCH associated with it. Four PAGCH TSs = one CCCH block, so 9 CCCH block in DL for paging and access Through parameters, we can set e.g. 2 blocks for AGCH and 7 blocks for PCH in each 51 frame MF

TCH BCC SDC

One "PCH block" corresponds to one "paging subgroup" if repeated after 'n' 51 frame MFs called a ''paging cycle" e.g. n=8 1 paging cycle contains 1 paging block of each paging group

first FCH occupies TS0 then SCH in next frame, then BCCH completed in 102 frames

UPLINK
4.615 ms 577 us MS1 OMCR --> TDMA Frame 0 TDMA Frame 1 TDMA Frame 2 TDMA Frame 3 TDMA Frame 4 TDMA Frame 5 TDMA Frame 6 TDMA Frame 7 TDMA Frame 8 TDMA Frame 9 TDMA Frame 10 TDMA Frame 11 TDMA Frame 12 TDMA Frame 13 TDMA Frame 14 TDMA Frame 15 TDMA Frame 16 TDMA Frame 17 TDMA Frame 18 TDMA Frame 19 TDMA Frame 20 TDMA Frame 21 TDMA Frame 22 TDMA Frame 23 TDMA Frame 24 TDMA Frame 25 TDMA Frame 26 TDMA Frame 27 TDMA Frame 28 TDMA Frame 29 TDMA Frame 30 TDMA Frame 31 TDMA Frame 32 235.365 ms 120 ms BCC TS0 RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH SDC TS1 SDCCH(0) SDCCH(0) SDCCH(0) SDCCH(0) SDCCH(1) SDCCH(1) SDCCH(1) SDCCH(1) SDCCH(2) SDCCH(2) SDCCH(2) SDCCH(2) SDCCH(3) SDCCH(3) SDCCH(3) SDCCH(3) SDCCH(4) SDCCH(4) SDCCH(4) SDCCH(4) SDCCH(5) SDCCH(5) SDCCH(5) SDCCH(5) SDCCH(6) SDCCH(6) SDCCH(6) SDCCH(6) SDCCH(7) SDCCH(7) SDCCH(7) SDCCH(7) SACCH(0) TCH TS2 TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F SACCH TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F IDLE TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F MS2/ MS3 TCH TS3 TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H SACCH for MS2 TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H SACCH for MS3 TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH TS4 TCH TCH TCH TCH TCH TS5 TCH TCH TCH TCH TCH TS6 TCH TCH TCH TCH TCH TS7 TCH TCH TCH TCH (e.g. each RACH TS will be received in 4.615 ms)

TDMA Frame 33 TDMA Frame 34 TDMA Frame 35 TDMA Frame 36 TDMA Frame 37 TDMA Frame 38 TDMA Frame 39 TDMA Frame 40 TDMA Frame 41 TDMA Frame 42 TDMA Frame 43 TDMA Frame 44 TDMA Frame 45 TDMA Frame 46 TDMA Frame 47 TDMA Frame 48 TDMA Frame 49 TDMA Frame 50 TDMA Frame 51 TDMA Frame 52 TDMA Frame 53 TDMA Frame 54 TDMA Frame 55 TDMA Frame 56 TDMA Frame 57 TDMA Frame 58 TDMA Frame 59 TDMA Frame 60 TDMA Frame 61 TDMA Frame 62 TDMA Frame 63 TDMA Frame 64 TDMA Frame 65 TDMA Frame 66 TDMA Frame 67 TDMA Frame 68 TDMA Frame 69 TDMA Frame 70 TDMA Frame 71

RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH

SACCH(0) SACCH(0) SACCH(0) SACCH(1) SACCH(1) SACCH(1) SACCH(1) SACCH(2) SACCH(2) SACCH(2) SACCH(2) SACCH(3) SACCH(3) SACCH(3) SACCH(3) IDLE IDLE IDLE SDCCH(0) SDCCH(0) SDCCH(0) SDCCH(0) SDCCH(1) SDCCH(1) SDCCH(1) SDCCH(1) SDCCH(2) SDCCH(2) SDCCH(2) SDCCH(2) SDCCH(3) SDCCH(3) SDCCH(3) SDCCH(3) SDCCH(4) SDCCH(4) SDCCH(4) SDCCH(4) SDCCH(5)

TCH/F TCH/F TCH/F TCH/F TCH/F SACCH TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F IDLE TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F SACCH TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F TCH/F

TCH/H TCH/H TCH/H TCH/H TCH/H SACCH for MS2 TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H SACCH for MS3 TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H SACCH for MS2 TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H TCH/H

TDMA Frame 72 TDMA Frame 73 TDMA Frame 74 TDMA Frame 75 TDMA Frame 76 TDMA Frame 77 TDMA Frame 78 TDMA Frame 79 TDMA Frame 80 TDMA Frame 81 TDMA Frame 82 TDMA Frame 83 TDMA Frame 84 TDMA Frame 85 TDMA Frame 86 TDMA Frame 87 TDMA Frame 88 TDMA Frame 89 TDMA Frame 90 TDMA Frame 91 TDMA Frame 92 TDMA Frame 93 TDMA Frame 94 TDMA Frame 95 TDMA Frame 96 TDMA Frame 97 TDMA Frame 98 TDMA Frame 99 TDMA Frame 100 TDMA Frame 101

RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH RACH

SDCCH(5) SDCCH(5) SDCCH(5) SDCCH(6) SDCCH(6) SDCCH(6) SDCCH(6) SDCCH(7) SDCCH(7) SDCCH(7) SDCCH(7) SACCH(4) SACCH(4) SACCH(4) SACCH(4) SACCH(5) SACCH(5) SACCH(5) SACCH(5) SACCH(6) SACCH(6) SACCH(6) SACCH(6) SACCH(7) SACCH(7) SACCH(7) SACCH(7) IDLE IDLE IDLE

TCH/F TCH/F TCH/F TCH/F TCH/F IDLE

TCH/H TCH/H TCH/H TCH/H TCH/H SACCH for MS3

26 Frame Traffic Channel MF 51 Frame Control Channel MF 51 Frame Control Channel MF 1 Burst =

TCH BCC SDC 1 TS

only RACH received by BTS in uplink completed in 102 frames

Superframes Hyperframes

1326 TDMA frames (26 x51) 2048 superframes

6.12 sec = 51 (26 Frame) or 26 (51 Frame ) MF 3 hr 28 min 53 sec 760 ms

Important It is not by accident that the control channel multiframe is not a direct multiple of the traffic channel multiframe. From the diagram, it can be seen that any given frame number will only occur simultaneously in both multiframes every 1326 TDMA frames (26 x 51). This number of TDMA frames is termed a superframe and it takes 6.12 s to transmit. This arrangement means that the timing of the traffic channel multiframe is always moving in relation to that of the control channel multiframe and this enables a MS to receive and decode BCCH information from surrounding cells. If the two multiframes were exact multiples of each other, then control channel timeslots would be permanently masked by traffic channel timeslot activity. This changing relationship between the two multiframes is particularly important, for example, to a MS which needs to be able to monitor and report the RSSIs of neighbour cells (it needs to be able to see all the BCCHs of those cells in order to do this). The hyperframe consists of 2048 superframes, this is used in connection with ciphering and frequency hopping. The hyperframe lasts for over three hours, after this time the ciphering and frequency hopping algorithms are restarted. SACCH Multiframe - SACCH TSs in four consecutive 26-Frame TCH MFs or two 51 frame SDCCH MFs As the MS only transmits or receives its own physical channel (normally containing TCH and SACCH) for one-eighth of the time, it uses the remaining time to monitor the BCCHs of adjacent target cells. It completes the process every 480 ms, or four 26-TCH MFs. (104 consecutive assigned TS) in dedicated mode and 470.73 ms in idle mode ( 2 51-frame MFs) The message that it sends to the BSS (on SACCH, uplink) contains the RxLev, RxQual, RxLev_ncell(n) The measurements are made over each SACCH multiframe, which is 104 TDMA frames (480 ms) for a TCH and 102 TDMA frames for an SDCCH (idle & dedicated modes respectively) 1 SACCH message = 4 SACHH TSs = complete measurement report

Transmission Timing To simplify the design of the MS, the GSM specifications specify an offset of three timeslots between the BSS and MS timing, thus avoiding the necessity for the MS to transmit and receive simultaneously. Timing Advance TA The synchronization of a TDMA system is critical because bursts have to be transmitted and received within the real time timeslots allotted to them. The GSM BTS caters for this problem by instructing the MS to advance its timing ((that is, transmit earlier) to compensate for the increased propagation delay. This advance is then superimposed upon the three timeslot nominal offset. This advance is then superimposed upon the three timeslot nominal offset. The maximum timing advance is approximately 233 s. This caters for a maximum cell radius of approximately 35 km. BTS-MS
TS0 TS1 TS2 TS3 TS0 TS4 TS1 TS5 TS2 TS6 TS3 TS7 TS4

MS-BTS - TA

TS5

TS6

TS7