Instituto Superior Tcnico

Sistemas de Processamento Digital de Sinais

2nd Semester 2012/2013

Gonalo Tavares

Development of a BPSK modem using a Costas Loop

Figure 1 represents the block diagram of a general binary phase shift keying (BPSK) modem.

TX bits
PC-USB interface

Scrambler

bn

Differential dn coder and mapper

Pulseshaping filter

xn

Modulator

xn

TX filter (passband)

sT (n )

fc(TX)
RX bits Descrambler
en
sampler

Differential decoder

cn

tn

Desmodulator (Costas Loop)

RX filter (passband)

sR (n )

tn = nTb + t

Bit synchronizer

fc(RX)

DSP (TMS320C6xxx)

Figure 1: A general DSP-BPSK modem. This modem is to be implemented in a high performance digital signal processor using digital signal processing techniques. The information bits arrive at the DSP from a user via an USB or other digital interface. The bits are then scrambled differentially coded and mapped into BPSK symbols (1 bit per symbol). These symbols are baseband filtered to achieve a desired signal spectrum and used to modulated the carrier. Before being transmitted the signal may be subject to additional bandpass filtering. On the receiver side the signal is bandpass filtered and demodulated. The resulting symbol stream is fed to a bit synchronizer which produces a clock signalling the optimum time instants to sample the bits. After sampling the bits are differentially decoded, descrambled and send to the receiving user. Unfortunately and due to the course time limitation, only the blue-shaded blocks will be implemented in this project using a Texas Instruments TMS320C6x DSK. The BPSK modem subset to be implemented is represented in Figure 2.

Bit source & scrambler

bn

Differential coder & mapping

dn

BPSK Modulator

x (t )

Physical channel

1/ f0
t
) cos(2p f0t + f

-1

x (t )

e(t )

) sin(2p f0t + f

Figure 2: BPSK modem subset to be implemented. At this stage of development, the bit source, differential coder and modulator are already developed and the BPSK signal x (t ) is available. The bit source is a simple generator which produces the bit sequence 010101. This sequence is not appropriate for transmission an thus the source bits need to be scrambled in order to appear random. For this purpose the scrambler circuit represented in Figure 3 should be used.

bn
XOR
delay Tb delay Tb

XOR
delay Tb

Scrambler

en
delay N bit

delay Tb

Descrambler

bn
3

 en

bn
Figure 3: Scrambler circuit (feedback structure), channel delay and descrambler.

The taps are summed modulo 2 (XOR operation) accordingly to the polynomial
P (x ) = 1 + x -6 + x -7 . The delay line should be implemented using an unsigned char (8 bit) variable. Problem: Can you show that bn=bn-N where N is the

channel delay in bits? To develop the BPSK Costas Loop receiver follow the next steps: 1) Consider the sinusoidal generator developed in the first part of the project, which uses a 32 point look-up table (LUT) with half cycle values of the sine function. Modify it to implement a numerically controlled oscillator (NCO) controlled by the error signal e(t) with the characteristic
fosc = fol + K 0 e(n ) where fol is the free-running frequency of the oscillator

which should be set equal to the carrier frequency of the BPSK signal, that is fol = f0. To obtain the quadrature output, read the LUT a second time with a 16 sample offset. 2) The 3 filters are lowpass with one pole and one zero, satisfying the difference equation:

y(n ) = ay(n - 1) + g

1-a [ x (n ) - bx (n - 1) ] 1- b

which has the signal flow diagram shown in Figure 4:

1
g

X (z )

1-b 1-a

-b

z -1

Y (z )

a
Figure 4: Low-pass filter signal flow diagram.

3) Determine the filter transfer function. Consider b = 0 and compute the other parameters such that the filters have unity DC gain, the upper and lower filters (Data filters) have cutoff frequency 1 kHz and the loop filter has cutoff frequency 10 Hz. Determine the fixed-point representation formats which are more adequate to the parameters representation and to the filters implementation. 4) Study the working principle of the demodulating loop and set it to work with fs = 16 kHz, f0 = fs/4 and fbit = fs/16. 5) Test the Costas loop with a sinusoidal input signal. First use only the upper arm, so that the loop behaves a a classical digital phase locked loop (DPLL). Then connect the lower arm and test the loop still using the sinusoidal input. Measure the lock and capture range. After this use the BPSK signal to test the operation of the Costas loop. After testing the Costas loop, characterize it by collecting data and figures of the following signals and spectra:

BPSK signal time-waveform and spectrum. Waveforms of the upper and lower arm lowpass filter outputs. Waveform of the error signal e(t). Transient of the loop acquisition process.

This data should be collected for different values of the system parameters, which will be indicated by laboratory instructor.