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Barium Strontium Titanate Thin-Film MultiLayer Capacitors

By Thomas A. Bernacki, Ivoyl P. Koutsaroff and Charles Divita Gennum Corporation
Introduction Miniaturization requirements for hearing-aids and other biomedical applications necessitate the use of advanced packaging and integrated passive technologies. One compound making this possible is Barium Strontium Titanate, (Ba, Sr)TiO3, (BST) [1]. Manufactured on silicon or ceramic wafers, BST capacitors offer high capacitance density, high frequency performance, and the ability to provide exceptional tunability for voltage tunable high frequency applications. Configured into multi-layer capacitor (MLC) arrays, a customized network of capacitors with different values, properties and performance characteristics can be manufactured on the same capacitor chip, offering a higher level of miniaturization, flexibility and performance than conventional discrete capacitors. These customized capacitor networks offer many benefits: A single placement step for all capacitors. Utilizing flip-chip to connect the capacitor chip directly to active ICs, capacitors can be connected in close proximity to critical IC nodes with minimal parasitics. Designers are not restricted to industry standard capacitance values. With profiles as low as 5mils (125microns) , volumetric capacitance densities can be significantly higher than discrete solutions. Ultra-low loss routing between multiple chips and I/Os can be incorporated, with the capacitor chip serving as a carrier in a multi-chip module.

The capacitor is defined by patterning each layer in sequence from the top down, until the entire mesa structure is defined. Following capacitor definition, inter-layer dielectric (ILD) is deposited over the entire wafer surface and cured at high temperatures. Vias are formed in the ILD by standard photolithography

Capacitor Manufacturing The process flow utilized to manufacture BST capacitors is outlined below: The BST multi-layer capacitor thin-film technology is based on a mesa-type process [1]. Alternating layers of Pt and BST are deposited on a silicon or alumina substrate to form a four-layer capacitor stack. BST films are deposited by metalorganic decomposition (MOD) or RF reactive sputtering. PASSIVE COMPONENT INDUSTRY  SEPTEMBER/OCTOBER 2004 11

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serving as routing between multiple active devices (ICs), to and from I/O pads, and functioning as I/O pads. Figure 4 shows a capacitor network of 23 capacitors with a total capacitance of 740nF, 54 I/O pads, and the associated interconnect, in a 3x5mm chip. The capacitors range in size from 1nF to 150nF. Tolerances on the capacitors are excellent, so no trimming or binning is utilized. Capacitor matching (the percent difference between capacitors The BST capacitor of identical designs on the same die) is process in full-scale guaranteed better than 1%. Overall high volume manufactolerance is guaranteed to be better turing yields approxithan 10%. mately 90%. 4-inch Time-domain dielectric breakdown wafers typically contain (TDDB) studies indicate the between 400 and 5000 capacitors have lifetimes of greater dice, depending on the than 10 years under a continuous Figure 1: Cross-Section of Multi-layer Thin-Film BST design [Figure 3]. bias of 3.3V. Over this time, the Capacitor Designs have incapacitors experience no fatigue or cluded as few as one aging. This is because only the capacitor to as many as twenty-three BST Capacitor Performance paraelectric phase of the dielectric on a single die. The capacitor chips material is utilized (no ferroelectric are designed concurrently with active BST capacitors have high capacibehavior is observed in the material). ICs to ensure optimal electrical pertance densities. In a four-layer BST caBST capacitors in the pF range formance and packaging ease. The pacitor on alumina ceramic substrate, have found use in high frequency circapacitor chips include low loss thinthe total capacitance density can be in cuits as well. BST is primarily utilized film interconnect on many products, the range of 144 to 256nF/mm2, dein high frequency circuits to take ad pending on the deposition method vantage of tunability, but used. While not in fill scale manufacby modifying the comturing at the moment, six-layer strucposition of the BST, tuntures have also been demonstrated, ability can be decreased increasing total capacitance density to to provide a high quality 384nF/mm2. factor. For a device with Utilizing standard wafer thinning decreased voltage tuntechniques, the capacitor dice can be ability, Q factors of over thinned to 4mils (100 microns). It has 200 have been achieved been shown that resulting volumetric at 1GHz, and over 160 at 3GHz. For these capacitors, tunabilities of approximately 2:1 (ratio of the highest to lowest capacitance) are observed. When the BST composition is tailored to favour tunability over quality factor, tunabiliFigure 2a: Cross-Section of Actual Multities of over 4:1 have Chip Module Figure 2b: Fully Encapsulated Multi-Chip Module with been achieved, with Q The total package thickness is 60 Mils. One of I/O Pads using the Tip of a Pen as Size Reference. factors over 60 at 1GHz the layers contains BST MLC, 6 Mils in thickThinned on board capacitor dice attached on a ceramic carrier. ness. [3]. Figure 5 shows a density of these capacitors exceeds any MLCC available at present. The largest capacitance value presently available is 0201 (0.6x0.3x0.3mm) with package size of 100nF [2], translating to volumetric density of approximately 1850nF/mm3; BST capacitors have a Wafers are thinned from 22mils volumetric density from 1500 to 2500 (560microns) down to 4mils nF/mm3. Figures 2a and 2b show a (100microns). complete multi-chip module, with the A cross-section of the final stack is thinned capacitor chip attached to sevdepicted in Figure 1. eral other dice. and reactive ion etching. This is followed by the deposition and patterning of a gold or aluminum interconnect layer and deposition and patterning of a silicon nitride passivation layer.

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Figure 3: 4" Al2O3 Ceramic Wafer with 4-Layer BST MLC Capacitors
% Capacitance vs Voltage
120% 100%

Figure 4: BST MLC Capacitor Chip The size is 3x5mm (118 x 197mils).

% Capacitance

80% 60% 40% 20% 0% -10 -5 0 5 10

DC Bias Voltage (V)

Figure 5: Tunability (0-8V) of a BST Capacitor

plot of tunability of a typical highly tunable (>4:1) BST capacitor.

Conclusions

High-density BST multi-layer capacitor technology offers distinct miniaturization advantages for various electronic modules and packages. By utilizing BST capacitors with a wide range (0.5pF to 500nF), functions like decoupling, bypassing, and varying capacitance (voltage tunable) can be realized with a single thin-film passive chip. Such miniaturized multi-functional capacitor chips can improve the performance and reduce the size of Multi-chip modules (MCM) and Systems-in-Package (SiP) [Figure 4].
References [1]

[2] [3]

M. Watt, W09800871, (1998). GRM03 capacitor from Murata Manufacturing Co., Ltd.: http://www.murata.com/catalog/k26e3.pdf I. P. Koutsaroff, T. A. Bernacki, M. Zelner, A. CervinLawry, T. Jimbo and K. Suu, Characterization of

[4]

Jpn. J. Appl. Phys. Vol. 43, No. 911, 6740, (2004). http://www.gennum.com/technology/

Thin-Film Decoupling and High-Frequency (Ba, Sr)Ti03 Capacitors on Al203 Ceramic Substrates,

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