IC Custom Layout Design

IC Custom Layout Design Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. Some of the layout considerations are given below, (1) Contacts: The source diffusion and the drain diffusion should be filled with the maximum number of contacts to reduce the resistance of the connection from the metal to the diffusion, and to maximize the amount of current that can flow through the contacts.

(2) Fingering: Putting together transistors with fixed aspect ratio will not result in a compact layout. Fortunately, the aspect ratio of the transistor can be modified by using the transistor current equation. For example, the transistor with a width of 20um and a length of 0.2um is similar to having four transistors connected in parallel, each with a width of 5um and a length of 0.2um. The MOS is said to have 4 fingers.

(3) Manufacturing limitations: Layout cannot be fabricated exactly as drawn in the layout due to the limitations in the manufacturing process, such as process tolerances and mask misalignment. Some of the manufacturing limitations are captured in the Spice transistor model. Two of the main parameters in the Spice transistor model are DW and DL. DW shows the delta difference of drawn W from effective W. DL shows the delta difference of drawn L from effective L. (4) Speed of the transistor: To increase the speed of the MOS, parasitic capacitance as well as resistance should be reduced. The frequency response of the transistor can be improved if the source capacitance and drain capacitance are reduced. The fingering technique allows the designer to reduce the drain and source area and in turn to reduce the parasitic capacitance.

Folded transistors also reduce the gate resistance. Resistivity of the poly is a few orders higher than the resistivity of the metal. The parasitic capacitances between the poly and the substrate, and between the metal and the poly, are very much larger than the parasitic capacitance between the metal to the substrate. Hence, using poly for interconnect could degrade the frequency response of the transistor if the poly routing is not optimized carefully. (5) Protect the Gate: The gate oxide underneath the poly is incredibly thin. If the charges accumulated on the poly is sufficiently large, the charges accumulated can damage the gate oxide. This is known as process antenna effect. The maximum amount of charges that can be accumulated on the poly is proportional to the area of the poly. Thus, an effective layout practice to prevent process antenna violation is to stay within the antenna ratio design rule of the respective technology. Some general guidelines are,

1)Minimize the use of poly for routing 2)Minimize the use of poly to connect the gates together 3)Do not place contact and via directly on top of the transistors gate. 4)Avoid routing over the gates of critical transistors 5)Avoid routing over active areas of critical transistors. (6) Contacts and Vias: A high percentage of IC manufacturing defects is related to faulty contact and via. Instead of using single contacts or vias, using at least double contacts or double vias whenever possible reduces the possibility of defects. (7) Metal coverage of contacts and vias: Additional metal coverage on the contacts and the vias should be done if they are located at the end of the metal. A larger metal coverage reduce contact or via resistance variation and also reduce the chance of an open contact or open via. (8) Spacing from poly to diffusion: The performance of the circuit can be degraded due to an increase in the capacitive coupling between the poly and the diffusion, and a change in the length and width of the transistor. So the spacing from poly to diffusion should be according to the technology rules. (9) Reduction of disturbances: Analog design performances are sensitive to electrical disturbance. Disturbance in the substrate should be minimized as much as possible. Two common types of substrate disturbance are

- Disturbance from minority carrier Minority carriers are injected into the substrate from the source diffusions and the drain diffusions when the source potential or the drain potential of NMOS is below the substrate potential or the source potential or the drain potential of PMOS is above the N-well potential. The drifting of the minority creates a potential difference or triggers a latch-up. To reduce disturbances from minority carrier, guard ring around noisy transistors can be used. Guard ring considerations are as following, (i) NMOS in the p-substrate with should be surrounded by N-well guard ring. N-well guard ring should be tied to VDD. The N-diffusions from the NMOS could inject stray electrons into the substrate. These stray electrons could be collected efficiently by the N-well guard ring that is biased to VDD to attract the electrons. (ii) PMOS in the N-well should be surrounded with P-diffusion guard ring. P-diffusion guard ring should be tied to ground. P-diffusions from the PMOS inject stray holes into the N-well. These stray holes could be collected efficiently by the P-diffusion guard ring that is biased to ground to attract the holes. Ideally, the guard rings should be placed as closely to the likely noise sources as possible. The guard rings are also placed around the critical transistors to minimize stray electrons and stray holes from affecting the critical transistors. Substrate coupling noise To reduce substrate coupling noise, the guard ring may be used in the following configuration around critical transistors. (i) Surround NMOS in the p-substrate with p-tap guard ring that is connected to ground. (ii) Surround PMOS in the N-well with n-tap guard ring that is connected to VDD.

An important layout practice is to ensure that there is no (or very little) current flowing through any part of the guard ring. There are some disadvantages of the guard rings like, guard rings take up a lot of area and they also add capacitive load to the transistor. So, if the area in the design is of utmost importance, then guard rings should be avoided.

What is Full Custom Layout Design

Dan Clein 6/8/2001 9:13 AM EDT
What is Full Custom Layout Design As we all know, the back-end design of layout implementation known as integrated circuit (IC) layout -is simplistically divided into ASIC-style flow and full-custom flow. This article will try to help users define the various flavors of full-custom layout. The concepts presented here apply in general. However, the examples and references shown refer primarily to CMOS layout design. For a newcomer to VLSI design, full-custom flow means polygon-level layout done entirely through the use of simple polygon pusher software. A lot of people around the world perform this function and common wisdom says the only solution to increasing the quantity and speed of layout is to hire more people. In reality, there are four distinct flavors of full-custom layout design and each offers a range of possibilities for automation: Full-custom layout driven by area limitations or special application needs: This type of layout is made up of repeated complex structures like sense amplifiers, decoders, adders, multipliers -- in general, a datapath with tight control over area, signal noise, bit symmetry. We refer to this type of layout as "datapath layout." Full-custom layout to address high performance or analog circuitry design: This includes phase-locked loops (PLLs), digital-to-analog converters or analog-to- digital converters (DACs/ADCs), electrostatic

discharge (ESD) structures, regulators, radio frequency (RF) speed requirements, or techniques to meet low-power needs. Let's call this type of layout "analog layout." Full-custom layout that requires greater attention to area and performance than the full digital (ASIC) flow, but has less stringent requirements for speed and less need for control over device-level layout than datapath or analog layout: We call this type of layout "custom digital layout." Full-custom layout for cell development: Cells are defined as logical building blocks that are part of a family of components that share common abutment rules, performance characteristics, or functionality. Examples would include the cells within a standard cell library or family of Pad cells. Let's call this type of layout "cell layout."

All four types of full-custom layout are driven by a schematic-based design style versus a language-based design style which uses Verilog or VHDL (the basis for the ASIC design flow). Each of these full-custom layout categories should be used as needed to achieve the overall requirements of the IC under development and, in general, the tradeoffs between the layout styles center around area and performance considerations (see Figure 1). Let's look in greater detail at each style, the thinking behind the technique, the design requirements and flow, the tools used for creation, and the maintenance and migration between process technologies. Datapath What are the special needs of datapath design?

Area Pitch-matched layout -- abutment Symmetry in layout and, therefore, timing

The most intricate example of datapath full-custom layout design is memory design. Memory layout design first depends on the layout of the memory cell. As the memory cell is repeated, cell efficiency is paramount. Therefore, a team of design engineers, layout designers, and processing specialists will invest months to develop the smallest size cell with the performance required for the application.
Surrounding these memory cells, a lot of effort is expended to build all of the interface circuitry. These blocks have to match the pitch of the memory cell and provide the functionality that, in this case, is much more complicated. To facilitate coordination, design and layout are developed in a full concurrent engineering style. The designer tries a new solution and the layout must match it in the pitch-limited spot. For such a design style, a flow that allows architecture exploration and fast back annotation to design is a must.

As seen in Figure 2 (see p. 34), the flow on the left involves only handcrafted intervention. The flow from layout to design and back can iterate as often as five or ten times. And yet, a "good solution" may still not be "clean" when passing through verification. Due to the nature of the processes in this case, we may be forced back to schematic design for small adjustments. In the case of a decoder cell, this flow may take from one to five days for a single full spin. The advantage of the right side of the flow shown in Figure 2 revolves around the use of an online

compactor -- a strategy which becomes even more evident when we are talking about architecture exploration. The compactors used within polygon editors are compacting transistors and their connections inside the cell design, so the layout designer can do a loose pass and, when all the devices and connections are done, then run the compactor tool. It's a very fast and efficient methodology to generate clean design-rules checked (DRC) layout cells. The advanced compactors available today, together with schematic- or netlist-driven layout generators, can provide the best of all possible worlds because the results are correct by construction (CBC), which means DRC and layout-versus-schematic (LVS) are correct. The time needed to use a compactor in this type of flow to explore a decoder architecture is measured in hours instead of days -- meeting DRC requirements, and needing only minutes for any change in schematic to be implemented in layout and then evaluated per the impact of the modification. Obviously the time to verify DRC and LVS, as a final step, is minimal versus the full hand crafted version of the flow. In both cases, parasitic extraction is an obligatory step -- a step beyond the scope of this article. The second issue with layout is maintenance. The compactor is saving the day because, in the case of a design modification, a change in device size is easy to implement when you have an automatic tool to realign design rules. In the case where design rules change in the last moments of a cycle, making the change in the command file and re-running the tool can get new DRC results in minutes. The third issue with this type of layout revolves around migrating a chip from one fabrication process to another to allow second-source manufacturing or process technology shrink. For this problem, the market already has two big contenders, Rubicad (San Jose, CA) and Sagantec (Fremont, CA). The tools are called migration tools and they are tied with a tiler engine. All of these cells abut at the cell-boundary level; a tiler places instances of the repeated cells in an array based on schematic input. Having the information about neighbours in the array, the tiler can then export the constraints data to a compactor that runs outside a polygon editor. This way, for instance, a full ALU can be migrated from process A to B in just a few hours. The advanced migration tools can even adjust device sizes based on a migration netlist or a table of equivalencies between the two processes. This is an example of automation in a flow in which most people still think automation is impossible. Analog layout Analog layout is the place were the layout designer needs to understand the phenomena that happens within the devices, physical connections, implants, and needs to have a good knowledge of semiconductor physics. For example, in a design operating at speeds up to 10 GHz, each small detail that is forgotten will impact performance. This is the place where a layout designer can enhance or destroy a design performance based on his or her capability to apply proper methodologies for each type of circuit. Interlaced devices, common centroid placement and connectivity, differential pairs routing, substrate noise and jitter -- all of them are playing a crucial role in the cell/block performance. Unlike other types of design, analog design deals with

capacitors, resistors, and inductors; automation is often seen as impossible. However, let's see how automation can actually help in this domain. If we carefully analyze the two flows seen in Figure 3 (p. 35), we observe the following:

The schematic, in this case, contains a lot more information than the previous flow. Circuit designers have to make a lot of assumptions when running a simulation. In the case of analog design, where the margins of error and tolerances are very small, the schematic needs to contain a lot of information to assist the layout implementation designer meet those assumptions. Each simulator is using models for devices based on the width and length of the device, number of fingers per device, the multiplication factor, and so forth. So it is important for the layout to follow 100 percent of the design needs. However, verification tools can't check for all of these "finesse" requirements -- they have to be implemented by methodology. The device generators are very advanced for this type of design. Based on extracted data from schematic design, they can generate all of the required transistors, capacitors, and resistors using the specifications explained above. The power lies in creating design and netlist correct devices that will be placed and connected by the layout designer without the worry of size, contacts per source/drain, gate finger, or number of multiples to be used. Placement is tightly controlled. There are several tools on the market such as the NeoLinear (Pittsburgh, PA) product, NeoCell, which provides schematic driven constraints placement. Routing is, in general, hand based. However, using connectivity editing -- which means that the polygon editor shows the "fly lines" of connectivity between devices'the layout designer can identify the connections. In most cases the width of the line is specified in schematic by current, electromigration, capacitance or resistance requirements.

The most important part of the verification process is extraction and back annotation to the schematic. This is an obligatory step because the simulation is based on models. Only after layout extraction can the simulation of the results be considered correct. However, there are a lot of issues related to the proximity of circuits, implants, and insulation guard rings that can't be simulated or extracted. A visual inspection is a must. In terms of database maintenance, once the design is implemented in layout using CBC, any change will be easy to manage using the ECO style regeneration of devices and small routing adjustments. There are no compactors for this task, so migration is out of the question. Due to the fact that analog layout design is very process dependent, it is almost impossible to design having process migration in mind. The design will always have to be adjusted based on the new models. It may happen that the previous architecture is not appropriate, in which case the design is actually a redesign, not a migration. Custom digital There are many circuits in VLSI design that need more attention than the normal digital flow (incorrectly referred to as "ASIC"), but have less constraints than described in the two sections above. (Figure 4) Circuits that need more attention include those such as the control logic in a memory, low-speed interfaces for analog and mixed signal blocks, or the parts of a design that are small enough to be schematic driven and close to the edge of the 500 cells/devices per block. For these types of circuits, the automation is much more advanced than for the other types of full custom layout.

The flow starts using schematic again because it is a full-custom environment. The circuit has specifications including device sizes, connectivity, critical design path, special signals widths, number of vias per connection, and RC-delay requirements. From here, the flow now moves into two other implementation options. If designers want to get a consistent gate quality -- inverters, NORs, NANDs -- then low level standardized gates can be laid out as basic cells. This way the team can benefit from an experienced layout designer to create a very good standard gate library of 20 to 50 gates. This library looks much like a digital one, but because the full custom needs a more controlled environment and we plan to use a shape-based router, the gates are more adapted to the need and the flow. The ports are full polygon size instead of small squares, as in maze or channel-based router requirements. The placer can place cells and devices in rows based on P and N transistor regions and row height. The placement will be based on constraints prepared for the tool, but more generally is based on minimal routing needs. That's why it's better to start with a larger area than needed to let the tool place everything fast, but never forgetting that the density will be sparse. After routing, we can call the compactor to move all the cells and routing to the minimum if this is what is required. In many cases, there are special routing issues such as wire widths larger than minimum, differential pairs, larger-than-normal distance between wires, or shielding requirements. In such cases, we will start with a very small area and will protect the important wires from compaction. Based on prior experience, using an unreleased placer and a shape-based router, we reduced the time to layout of 500+ gates from 1 week to 2 hours. Many vendors are trying to develop a unified environment. Cadence (San Jose, CA) with Virtuoso Custom Placer, Virtuoso Custom Router, and Companion (Sagantec) provide environment enhancements within Virtuoso XL environment. Mentor Graphics (Wilsonville, Oregon) has a similar environment built within its IC Station set of tools. In terms of maintenance for changes in process technology or schematic, this flow benefits from a lot of automation. If the change is schematic -- meaning connections or gate sizes -- a fast replace and reroute locally can fix the issues, using a compactor as the last step. If the change is process-based, Rubicad and Sagantec provide over-the-cell routing compactions or hierarchical migration. Please don't forget to rerun extraction and simulate results because compactors care about minimum design rules and not circuit performance. Cell layout As introduced above, cell full-custom cell layout applies to cells that are part of a family of building blocks, which have a commonality in abutment rules, performance characteristics, functionality, and the tool they are built for. Standard cell and pad libraries are prime examples of a family of cells designed in a full-custom methodology. The architecture of the cells must be considered carefully, taking into account:

The availability and characteristics of interconnect layers -- in general for cell level layout only metals 1 to 2 are used. Abutment rules to all possible combinations of neighbors within the family. Abutment considerations must include considerations for power routing, substrate and cell connections. Compatibility to the intended design flow. For example, routers "like" to have all pins of standard cells on a common pitch for fast and easy connection.

For this kind of layout, the automation can be very advanced. Once the architecture of the cells has been conceived by the layout designer, this architecture can be "programmed" into a class of tools termed "layout synthesis" tools. Combined with a logical definition for each of the cells within this family, the entire cell library can be synthesized and created automatically. Tools created by Cadabra (Numerical Technology, San Jose, CA), Sycon (Santa Clara, CA), Cadence, and Mentor Graphics can fill any user needs. If the library is laid out using a polygon pusher, optimization of the family of cells is also possible. Using tools from Rubicad or Sagantec, the layout can be analyzed as a family to determine the architectural needs for the library. These tools can generate constraints and then 'migrate" the entire library to new parameters. This way you can migrate a library within the same process from channel-based routing to maze routing needs by moving all the pins in the new positions with minimum hand intervention. Wrapping up This small classification of full-custom layout should help the reader make better decisions in choosing the right type of tool for the right type of job. At the same time, vendors can learn the proper terminology and will be able to help users to see the appropriate demos for the tools they need. The name of the companies and specific tools appearing in the article are used only to identify the type of tool. There are many other similar tools in the market; each year at Design Automation Conference (DAC), new ones appear. Maybe using the terms and classification described in this article will make it easier for users and vendors to speak the same language.
Hands on experience in Analog & Mixed Signal (AMS) layout design for different IP's like Level Shifter, Op-Amp, BGR, DAC, Column Drive, Pixels, Imaging Sensors, Standerd cells like NAND ,NOR,MUX,OR,AND,OAI,DFF etc. which Includes Floor planning, Matching, Routing, DRC/LVC and Debugging reliability issues such as HV, Antenna, ESD, Latch Up, IR Drop, EM Violations etc. Experience in working with client team to adapt to the changing DRC/DFM requirements in 28nm, 130nm,180nm,600nm technology nodes with different FABS like TSMC,UMC,X-FAB.