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VLSI LAB MANUAL

PRACTICAL-1
Aim: Introduction to Xilinx-ISE software.

Date:

ISE 8.2i Quick Start Tutorial


The ISE 8.2i Quick Start Tutorial provides Xilinx PLD designers with a quick overview ofthe basic design process using ISE 8.2i Getting Started Starting the ISE Software To start ISE, double-click the desktop icon,or start ISE from the Start menu by selecting:

Create a New Project Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kitdemo board. To create a new project: 1. Select File ->New Project... The New Project Wizard appears. 2. Type tutorial in the Project Name field. 3. Enter or browse to a location (directory path) for the new project. A tutorialSub-directory is created automatically. 4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page. 6. Fill in the properties in the table as shown below: Product Category: All Family: Spartan3 Device: XC3S200 Package: FT256 Speed Grade: -4 Top-Level Module Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Verify that Enable Enhanced Design Summary is selected.
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VLSI LAB MANUAL

Leave the default values in the remaining fields. When the table is complete, your project properties will look like the following:

Figure 2: Project Device Properties 7. Click Next to proceed to the Create New Source window in the New Project Wizard. Atthe end ofthe next section, your new project will be complete.

Create an HDL Source


In this section, you will create the top-level HDL file for your design. Determine thelanguage that you wish to use for the tutorial. Then, continue either to the Creating aVHDL Source section below, or skip to the Creating a Verilog Source section.

Creating a VHDL Source


Create a VHDL source file for the project as follows: 1. Click the New Source button in the New Project Wizard. 2. Select VHDL Module as the source type. 3. Type in the file name counter. 4. Verify that the Add to project checkbox is selected. 5. Click Next. 6. Declare the ports for the counter design by filling in the port information as shownbelow: 7. Click Next, then Finish in the New Source Information dialog box to complete the newsource file template. 8. Click Next, then Next, then Finish.
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The source file containing the entity/architecture pair displays in the Workspace, and thecounter displays in the Source tab, as shown below:

7. Click Next, then Finish in the New Source Information dialog box to complete the newsource file template. 8. Click Next, then Next, then Finish. The source file containing the entity/architecture pair displays in the Workspace, and thecounter displays in the Source tab, as shown below:

VLSI LAB MANUAL

Figure 4: New Project in ISE

Using Language Templates (VHDL)


The next step in creating the new source is to add the behavioral description for thecounter. To do this you will use a simple counter code example from the ISE Language Templates and customize it for the counter design. 1. Place the cursor just below the begin statement within the counter architecture. 2. Open the Language Templates by selecting Edit ->Language Templates Note: You can tile the Language Templates and the counter file by selecting Window >TileVertically to make them both visible. 3. Using the + symbol, browse to the following code example: VHDL ->Synthesis Constructs ->Coding Examples ->Counters ->Binary -> Up/Down Counters - Simple Counter 4. With Simple Counter selected, select Edit Use in File, or select the Use Template in File toolbar button. This step copies the template into the counter source file. 5. Close the Language Templates.

Final Editing of the VHDL Source


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1. Add the following signal declaration to handle the feedback of the counter outputbelow the architecture declaration and above the first begin statement: signalcount_int :std_logic_vector(3 downto0) := "0000"; 2. Customize the source file for the counter design by replacing the port and signal nameplaceholders with the actual ones as follows: 3. Add the following line below the end process; statement: COUNT_OUT <= count_int; 4. Save the file by selecting File ->Save. When you are finished, the counter source file will look like the following: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Entitycounter is Port ( CLOCK :in STD_LOGIC; DIRECTION :in STD_LOGIC; COUNT_OUT :out STD_LOGIC_VECTOR (3 downto0) ); endcounter; architecture Behavioral of counter is signal count_int : std_logic_vector(3 downto0) := "0000"; begin process(CLOCK) begin if CLOCK='1' and CLOCK'eventthen if DIRECTION='1' then count_int<= count_int + 1; else count_int<= count_int - 1; end if; end if; end process; COUNT_OUT <= count_int; EndBehavioral; You have now created the VHDL source for the tutorial project.
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Design Simulation
Verifying Functionality using Behavioral Simulation
Create a test bench waveform containing input stimulus you can use to verify thefunctionality of the counter module. The test bench waveform is a graphical view of a testbench. Create the test bench waveform as follows: 1. Select the counter HDL file in the Sources window. 2. Create a new test bench source by selecting Project New Source. 3. In the New Source Wizard, select Test Bench WaveFormas the source type, and type counter_tbwin the File Name field. 4. Click Next. 5. The Associated Source page shows that you are associating the test bench waveform with the source file counter. Click Next. 6. The Summary page shows that the source will be added to the project, and it displays the source directory, type and name. Click Finish. 7. You need to set the clock frequency, setup time and output delay times in the Initialize Timing dialog box before the test bench waveform editing window opens. The requirements for this design are the following: The counter must operate correctly with an input clock frequency = 25 MHz. The DIRECTION input will be valid 10 ns before the rising edge of CLOCK. The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. The design requirements correspond with the values below. Fill in the fields in the Initialize Timing dialog box with the following information: Clock Time High: 20 ns. Clock Time Low: 20 ns. Input Setup Time: 10 ns. Output Valid Delay: 10 ns. Offset: 0 ns. Global Signals: GSR (FPGA) Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically. Initial Length of Test Bench: 1500 ns. Leave the default values in the remaining fields.

VLSI LAB MANUAL

Figure 7: Initialize Timing

8. Click Finish to complete the timing initialization. 9. The blue shaded areas that precede the rising edge of the CLOCK correspond to theInput Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port todefine the input stimulus for the counter design as follows: Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the counter will count up. Click on the blue cell at approximately the 900 ns to assert DIRECTION high sothat the counter will count down. Note: For more accurate alignment, you can use the Zoom In and Zoom Out toolbar buttons.

Figure 8: Test Bench Waveform

10. Save the waveform.


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11. In the Sources window, select the Behavioral Simulation view to see that the testbench waveform file is automatically added to your project

Figure 9: Behavior Simulation Selection

12. Close the test bench waveform.

Create a Self-Checking Test Bench Waveform


Add the expected output values to finish creating the test bench waveform. Thistransforms the test bench waveform into a self-checking test bench waveform. The keybenefit to a self-checking test bench waveform is that it compares the desired and actualoutput values and flags errors in your design as it goes through the varioustransformations, from behavioral HDL to the device specific representation.To create a self-checking test bench, edit output values manually, or run the GenerateExpected Results process to create them automatically. If you run the Generate ExpectedResults process, visually inspect the output values to see if they are the ones you expectedfor the given set of input values.

To create the self-checking test bench waveform automatically, do the following:


1. Verify that Behavioral Simulation is selected from the drop-down list in the Sourceswindow. 2. Select the counter_tbwfile in the Sources window. 3. In the Processes tab, click the + to expand the Xilinx ISE Simulator process anddouble-click the Generate Expected Simulation Results process. This processsimulates the design in a background process. 4. The Expected Results dialog box opens. Select Yesto annotate the results to the testbench.

VLSI LAB MANUAL

Figure 10: Expected Results Dialog Box

5. Click the + to expand the COUNT_OUT bus and view the transitions thatcorrespond to the Output Delay value (yellow cells) specified in the Initialize Timingdialog box.

Figure 11: Test Bench Waveform with Results

6. Save the test bench waveform and close it. You have now created a self-checking test bench waveform.

Simulating Design Functionality


Verify that the counter design functions as you expect by performing behavior simulationas follows: 1. Verify that Behavioral Simulation and counter_tbware selected in the Sourceswindow. 2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process anddouble-click the Simulate Behavioral Model process.The ISE Simulator opens and runs the simulation to the end of the test bench.

VLSI LAB MANUAL

3. To view your simulation results, select the Simulation tab and zoom in on thetransitions. The simulation waveform results will look like the following:

TEACHER SIGN:

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VLSI LAB MANUAL

PRACTICAL-2
Aim:Design all basic Gates (AND, OR, XOR,X-NOR,NAND,NOT) VHDL Program:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gates is Port ( a : in STD_LOGIC; b : in STD_LOGIC; and_g : out STD_LOGIC; or_g : out STD_LOGIC; nor_g : out STD_LOGIC; nand_g : out STD_LOGIC; not_g : out STD_LOGIC; xor_G : out STD_LOGIC); end gates; architecture Behavioral of gates is begin
and_g<= a and b; nand_g<= a nand b; xor_g<= a xor b; end Behavioral; OR_g<= a or b; nor_g<= a nor b; not_g<= not a;

Date:

RTL Schematic:

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VLSI LAB MANUAL

Technology schematic

Test-Bench Template
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY A_vhd IS END A_vhd; ARCHITECTURE behavior OF A_vhd IS COMPONENT gates PORT( a : IN std_logic; b : IN std_logic; and_g : OUT std_logic; or_g : OUT std_logic; nor_g : OUT std_logic; nand_g : OUT std_logic; not_g : OUT std_logic; xor_G : OUT std_logic END COMPONENT; SIGNAL a :std_logic := '0'; SIGNAL b :std_logic := '0'; SIGNAL and_g :std_logic; SIGNAL or_g :std_logic; SIGNAL nor_g :std_logic; SIGNAL nand_g :std_logic; SIGNAL not_g :std_logic;

);

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VLSI LAB MANUAL SIGNAL xor_G :std_logic; BEGIN uut: gates PORT MAP( a => a, b => b,

and_g =>and_g, nor_g =>nor_g, nand_g =>nand_g, not_g =>not_g,

or_g =>or_g,

xor_G =>xor_G

);

tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish wait for 100 ns; a<='0'; wait for 100 ns; a<='1'; -- Place stimulus here wait; -- will wait forever END PROCESS; END;

b<='1'; b<='0';

Waveform

Synthesis Report:
Final Results RTL Top Level Output File Name : gates.ngr Top Level Output File Name : gates Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs :8
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Cell Usage : # BELS :6 # INV :1 # LUT2 :5 # IO Buffers :8 # IBUF :2 # OBUF :6 Maximum combinational path delay: 10.134ns Timing Detail: Delay: 10.134ns (Levels of Logic = 3) Source: a (PAD) Destination: nor_g (PAD) Data Path: a to nor_g Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 6 0.924 1.850 a_IBUF (a_IBUF) INV:I->O 1 0.653 1.150 not_g1_INV_0 (not_g_OBUF) OBUF:I->O 5.557 not_g_OBUF (not_g) ---------------------------------------Total 10.134ns (7.134ns logic, 3.000ns route) (70.4% logic, 29.6% route) ================================================================ TEACHER SIGN:

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PRACTICAL-3
Aim: Design
Adder circuit in VHDL

Date:

VHDL Program: (1) Full Adder


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityfulladder is Port ( a : in STD_LOGIC; sum : out STD_LOGIC; s1 : out STD_LOGIC; s2 : out STD_LOGIC; s3 : out STD_LOGIC; s4 : out STD_LOGIC ); endfulladder; architectureBehavioral of fulladder is signal s1,s2,s3:std_logic; begin s1 <= a xor b; sum<= s1 xor c; s2 <= a and b; s3 <= b ; endBehavioral;

b : in STD_LOGIC;c : in STD_LOGIC; carry : out STD_LOGIC;

RTL Schematic:

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VLSI LAB MANUAL

Technology schematic

Simulation program and graph:


LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY TEST_vhd IS END TEST_vhd; ARCHITECTURE behavior OF TEST_vhd IS COMPONENT fulladder PORT( a : IN std_logic; b : IN std_logic; c : IN std_logic; sum : OUT std_logic; carry : OUT std_logic; s4 : OUT std_logic ); END COMPONENT; --Inputs SIGNAL a :std_logic := '0'; SIGNAL b :std_logic := '0'; SIGNAL c :std_logic := '0'; --Outputs SIGNAL sum :std_logic; SIGNAL carry :std_logic; SIGNAL s4 :std_logic; BEGIN uut: fulladder PORT MAP( a => a, b => b, c => c, sum => sum, carry => carry, s4 => s4 tb : PROCESS BEGIN -- Wait 100 ns for global reset to finish 16

);

VLSI LAB MANUAL wait for 100 ns; a=>'1'; b=>'0';\ c=>'0'; -- Place stimulus here wait; -- will wait forever END PROCESS; END;

Waveform:

Synthesis Report:
Final Results RTL Top Level Output File Name : fulladder.ngr Top Level Output File Name : fulladder Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs :6 Cell Usage : # BELS :1 # LUT3 :1 # IO Buffers :4 # IBUF :3 # OBUF :1 ====================================================================== Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 9.434ns Timing Detail: -------------All values displayed in nanoseconds (ns) 17

VLSI LAB MANUAL ========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 3 / 1 ------------------------------------------------------------------------Delay: 9.434ns (Levels of Logic = 3) Source: a (PAD) Destination: sum (PAD) Data Path: a to sum Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 1 0.924 1.150 a_IBUF (a_IBUF) LUT3:I0->O 1 0.653 1.150 fulladder_0_xo<1>1 (sum_OBUF) OBUF:I->O 5.557 sum_OBUF (sum) ---------------------------------------Total 9.434ns (7.134ns logic, 2.300ns route) (75.6% logic, 24.4% route) =========================================================================

(2)HALF ADDER VHDL Program:


library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entityhalf_adder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC endhalf_adder; architectureBehavioral of half_adder is component xor_12 Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC ); end component; component and_12 Port ( x : in STD_LOGIC; y : in STD_LOGIC;
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);

VLSI LAB MANUAL

z : out STD_LOGIC ); end component; begin xx1:xor_12 port map(a,b,sum); aa1:and_12 port map(a,b,carry); endBehavioral;

RTL Sythesis

Technology Schematic:

Test Bench templete


LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test4_vhd IS END test4_vhd; ARCHITECTURE behavior OF test4_vhd IS
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COMPONENT half_adder PORT( a : IN std_logic; b : IN std_logic; sum : OUT std_logic; carry : OUT std_logic ); END COMPONENT; SIGNAL a :std_logic := '0'; SIGNAL b :std_logic := '0'; SIGNAL sum :std_logic; SIGNAL carry :std_logic; BEGIN uut: half_adder PORT MAP( a => a, b => b, sum => sum, carry => carry tb : PROCESS BEGIN wait for 100 ns; a <='1'; b <='0'; -- Place stimulus here wait; -- will wait forever END PROCESS; END;

);

Waveform:

Synthesis Report:
Final Results RTL Top Level Output File Name : half_adder.ngr Top Level Output File Name : half_adder Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO
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Design Statistics # IOs :4 Cell Usage : # BELS :2 # LUT2 :2 # IO Buffers :4 # IBUF :2 # OBUF :2 --------------------------Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 9.624ns Timing Detail: Delay: 9.624ns (Levels of Logic = 3) Source: a (PAD) Destination: carry (PAD) Data Path: a to carry Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) IBUF:I->O 2 0.924 1.340 a_IBUF (a_IBUF) LUT2:I0->O 1 0.653 1.150 aa1/z1 (carry_OBUF) OBUF:I->O 5.557 carry_OBUF (carry) Total 9.624ns (7.134ns logic, 2.490ns route) (74.1% logic, 25.9% route)

TEACHERS SIGN

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PRACTICAL-4
Aim: To design 9 bit parity generator in VHDL VHDL program
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity parity_9_bit is Port ( D0 : in STD_LOGIC; D1 : in STD_LOGIC; D2 : in STD_LOGIC; D3 : in STD_LOGIC; D4 : in STD_LOGIC; D5 : in STD_LOGIC; D6 : in STD_LOGIC; D7 : in STD_LOGIC; D8 : in STD_LOGIC; ODD : out STD_LOGIC; EVEN : BUFFER STD_LOGIC); end parity_9_bit; architecture Behavioral of parity_9_bit is COMPONENT xor_21 Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC ); end component; component inv_11 Port ( EVEN : in STD_LOGIC; ODD : out STD_LOGIC end component; signal E0,E1,E2,E3,F0,F1,H0:STD_LOGIC; begin XE0:xor_21 PORT MAP (D0,D1,E0); XE1:xor_21 PORT MAP (D2,D3,E1); XE2:xor_21 PORT MAP (D4,D5,E2); XE3:xor_21 PORT MAP (D6,D7,E3); XF0:xor_21 PORT MAP (E0,E1,F0); XF1:xor_21 PORT MAP (E2,E3,F1); XH0:xor_21 PORT MAP (F0,F1,H0); XEVEN:xor_21 PORT MAP (H0,D8,EVEN); XODD:inv_11 PORT MAP (EVEN,ODD);
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Date:

);

VLSI LAB MANUAL

end Behavioral;

RTL Schematic:

Technology schematic

TEST BENCH
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS COMPONENT bit9_parrity PORT( D0 : IN std_logic; D1 : IN std_logic; D2 : IN std_logic; D3 : IN std_logic; 23

VLSI LAB MANUAL D4 : IN std_logic; D5 : IN std_logic; D6 : IN std_logic; D7 : IN std_logic; D8 : IN std_logic; ODD : OUT std_logic; EVEN : OUT std_logic END COMPONENT; SIGNAL D0 :std_logic := '0'; SIGNAL D1 :std_logic := '0'; SIGNAL D2 :std_logic := '0'; SIGNAL D3 :std_logic := '0'; SIGNAL D4 :std_logic := '0'; SIGNAL D5 :std_logic := '0'; SIGNAL D6 :std_logic := '0'; SIGNAL D7 :std_logic := '0'; SIGNAL D8 :std_logic := '0'; SIGNAL ODD :std_logic; SIGNAL EVEN :std_logic; BEGIN uut: bit9_parrity PORT MAP( D0 => D0, D1 => D1, D2 => D2, D3 => D3, D4 => D4, D5 => D5, D6 => D6, D7 => D7, D8 => D8, ODD => ODD, EVEN => EVEN

);

);

tb : PROCESS BEGIN wait for 100 ns; d0<= '1'; d3<= '1'; d6<= '1';

d1 <= '0'; d4<= '0'; d7<= '1';

d2<= '1'; d5<= '0'; d8<= '0';

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VLSI LAB MANUAL

Waveform:

Synthesis Report:
Final Results RTL Top Level Output File Name : bit9_parrity.ngr Top Level Output File Name : bit9_parrity Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 11 Cell Usage : # BELS :4 # LUT3 :2 # LUT4 :2 # IO Buffers : 11 # IBUF :9 # OBUF :2 TIMING REPORT No clock signals found in this design Asynchronous Control Signals Information: No asynchronous control signals found in this design Timing Summary: Speed Grade: -5 Maximum combinational path delay: 11.427ns Delay: 11.427ns (Levels of Logic = 4) Source: D0 (PAD) Destination: EVEN (PAD) Data Path: D0 to EVEN Cell:in->out fanout Delay Delay Logical Name (Net Name) IBUF:I->O 1 0.924 1.150 D0_IBUF (D0_IBUF) LUT4:I0->O 2 0.653 1.340 xf0/Mxor_z_Result1 (F0) LUT3:I1->O 1 0.653 1.150 xeven/Mxor_z_Result1 (EVEN_OBUF)

TEACHER SIGN:

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PRACTICAL-5
Aim: Design the 4 to 1 mux in VHDL.
VHDL Program:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is Port ( s : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC; i : in STD_LOGIC_VECTOR (3 downto 0) ); end mux; architecture Behavioral of mux is begin process(i,s) begin case s is when "00" => y <=i(0); when "01" => y <=i(1); when "10" => y <=i(2); when "11" => y <=i(3); when others => null; end case; end process; endBehavioral;

Date:

RTL Schematic:

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VLSI LAB MANUAL

Technology schematic

Test Bench Templte


module test1_v; // Inputs reg [1:0] s; reg [3:0] i; // Outputs wire y; // Instantiate the Unit Under Test (UUT) muxuut ( .s(s), .y(y), .i(i) ); 27

VLSI LAB MANUAL initial begin // Initialize Inputs i<="0001"; s<="00"; // Wait 100 ns for global reset to finish #10; s = 0; i = 3; #10; s = 1; i = 2; #10; s = 0; i = 1; #10; s = 1; i = 0; // Add stimulus here End Endmodule

Waveform:

Synthesis Report:
Final Results RTL Top Level Output File Name : mux.ngr Top Level Output File Name : mux Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs :7 Cell Usage : # BELS :3 # LUT3 :2 28

VLSI LAB MANUAL # MUXF5 :1 # IO Buffers :7 # IBUF :6 # OBUF :1 -----------------------------------------------------------TIMING REPORT No clock signals found in this design Asynchronous Control Signals Information: No asynchronous control signals found in this design Timing Summary: Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 6.683ns Timing Detail: All values displayed in nanoseconds (ns) Timing constraint: Default path analysis Total number of paths / destination ports: 7 / 1 ------------------------------------------------------------------------Delay: 6.683ns (Levels of Logic = 4) Source: s<0> (PAD) Destination: y (PAD) Data Path: s<0> to y Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 2 0.718 0.858 s_0_IBUF (s_0_IBUF) LUT3:I0->O 1 0.382 0.000 s<0>1 (N31) MUXF5:I0->O 1 0.379 0.450 Mmux_y_f5 (y_OBUF) OBUF:I->O 3.896 y_OBUF (y) ---------------------------------------Total 6.683ns (5.375ns logic, 1.308ns route) (80.4% logic, 19.6% route)

TEACHER SIGN

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PRACTICAL-6
Aim: To design 3 to 8 decoder in VHDL.
VHDL program:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder3x8 is Port ( i : in STD_LOGIC_VECTOR (2 downto 0); en : in STD_LOGIC; y : out STD_LOGIC_VECTOR (7 downto 0)); end decoder3x8; architecture Behavioral of decoder3x8 is begin process ( i,en) begin If en='1' then case i is when "000" =>y<="00000001"; when "001" =>y<="00000010"; when "010" =>y<="00000100"; when "011" =>y<="00001000"; when "100" =>y<="00010000"; when "101" =>y<="00100000"; when "110" =>y<="01000000"; when "111" =>y<="10000000"; when others =>null; end case; end if; end process; end Behavioral;

Date:

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VLSI LAB MANUAL

RLT Schematic:

Technology schematic:

Test bench temple:


LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS COMPONENT decoder3x8 PORT( i : IN std_logic_vector(2 downto 0); en : IN std_logic; y : OUT std_logic_vector(7 downto 0) ); 31

VLSI LAB MANUAL END COMPONENT; --Inputs SIGNAL en : std_logic := '0'; SIGNAL i : std_logic_vector(2 downto 0) := (others=>'0'); --Outputs SIGNAL y : std_logic_vector(7 downto 0); BEGIN uut: decoder3x8 PORT MAP( i => i, en => en, y => y ); tb : PROCESS BEGIN wait for 100 ns; en<='1'; i<="111"; END PROCESS; END;

Waveform:

Synthesis Report:
Final Results RTL Top Level Output File Name : decoder3x8.ngr Top Level Output File Name : decoder3x8 Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs Cell Usage : # BELS

: 12 :8 32

VLSI LAB MANUAL # LUT3 :8 # FlipFlops/Latches :8 # LD :8 # Clock Buffers :1 # BUFGP :1 # IO Buffers : 11 # IBUF :3 # OBUF :8 Clock Information: Clock Sign | Clock buffer(FF name) | Load | en | BUFGP |8 | Timing Summary: Speed Grade: -6 Minimum input arrival time before clock: 3.879ns Maximum output required time after clock: 6.897ns Timing Detail: Total number of paths / destination ports: 24 / 8 Offset: 3.879ns (Levels of Logic = 2) Source: i<0> (PAD) Destination: y_7 (LATCH) Destination Clock: en falling Data Path: i<0> to y_7 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) IBUF:I->O 8 0.776 1.845 i_0_IBUF (i_0_IBUF) LUT3:I0->O 1 0.549 0.000 Mdecod__mux0001_inst_lut3_01 (_mux0001<7>) Total 3.879ns (2.034ns logic, 1.845ns route) (52.4% logic, 47.6% route) Offset: 6.897ns (Levels of Logic = 1) Source: y_7 (LATCH) Destination: y<7> (PAD) Source Clock: en falling Data Path: y_7 to y<7> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) Total 6.897ns (5.862ns logic, 1.035ns route) (85.0% logic, 15.0% route)

TEACHERS SIGN

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VLSI LAB MANUAL

PRACTICAL-7

Date:

AIM : To design JK flip flop (Positive edge triggered JK Flip Flop with reset input) and D-flipflop. Program: 1). JK-flip flop

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jk is Port (

clk : in STD_LOGIC; j : in STD_LOGIC; k : in STD_LOGIC; reset : in STD_LOGIC; q : out STD_LOGIC; qbar : out STD_LOGIC

);

end jk; architecture Behavioral of jk is signal qtemp,qbartemp : std_logic :='0'; begin Q <= qtemp; Qbar <= qbartemp; process(clk,reset) begin if(reset = '1') then --Reset the output. qtemp <= '0'; qbartemp <= '1'; elsif( rising_edge(clk) ) then if(J='0' and K='0') then --No change in the output NULL; elsif(J='0' and K='1') then --Set the output. qtemp <= '0'; qbartemp <= '1';
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elsif(J='1' and K='0') then --Reset the output. qtemp <= '1'; qbartemp <= '0'; else --Toggle the output. qtemp <= not qtemp; qbartemp <= not qbartemp; end if; end if; end process; end Behavioral; RTL Schematic:

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Technology schematic

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Test bench templte


library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity testbench is end testbench; architecture behavior of testbench is signal clk,j,k,reset,q,qbar : std_logic := '0'; constant clk_period : time := 10 ns; begin --Signal declarations -- Clock period definitions -- Instantiate the Unit Under Test (UUT) -- Clock process definitions

UUT : entity work.jk port map (clk,j,k,q,qbar,reset); clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin j<='1'; k<='0'; wait for clk_period*2; j<='1'; k<='1'; wait for clk_period*2; j<='0'; k<='1'; wait for clk_period*2; j<='0'; k<='0'; wait for clk_period*2; j<='1'; k<='0'; wait for clk_period*2; reset <='1'; j<='1'; k<='1'; wait for clk_period*2;
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j<='0'; k<='1'; wait for clk_period*2; reset <='0'; j<='1'; k<='1'; wait; end process; end;

Waveform

Synthesis report
* Final Report Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs :6 Cell Usage : # BELS # LUT2 # LUT3 # FlipFlops/Latches # FDCE # FDPE # Clock Buffers # BUFGP # IO Buffers # IBUF * : jk.ngr : jk : NGC : Speed : NO

:3 :1 :2 :2 :1 :1 :1 :1 :5 :3
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# OBUF :2 ============================================================ Device utilization summary: --------------------------Selected Device : 2s15cs144-5 Number of Slices: 2 out of 192 1% Number of Slice Flip Flops: 2 out of 384 0% Number of 4 input LUTs: 3 out of 384 0% Number of IOs: 6 Number of bonded IOBs: 6 out of 90 6% Number of GCLKs: 1 out of 4 25% Clock Information: Clock Signal | Clock buffer(FF name) | Load | clk | BUFGP |2 | Data Path: qtemp to qtemp Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDCE:C->Q 2 1.292 1.340 qtemp (qtemp) LUT3:I2->O 1 0.653 0.000 _mux00041 (_mux0004) FDCE:D 0.753 qtemp ---------------------------------------Total 4.038ns (2.698ns logic, 1.340ns route) (66.8% logic, 33.2% route) Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 8 / 4 Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 2 / 2 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDPE:C->Q 2 1.292 1.340 qbartemp (qbartemp) OBUF:I->O 5.557 qbar_OBUF (qbar) ---------------------------------------Total 8.189ns (6.849ns logic, 1.340ns route) (83.6% logic, 16.4% route)

TEACHERS SIGN

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PRACTICAL-8
Aim :To design BCD counter Program library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity BCD is Port ( y : out STD_LOGIC_VECTOR (3 downto 0); clk : in STD_LOGIC; rst : in STD_LOGIC); end BCD; architecture Behavioral of BCD is signal temp: std_logic_vector(3 downto 0); begin process ( clk,rst ) begin if (rst= '1') then temp <= "0000"; elsif(clk='1' and clk'event) then temp<=temp+"0001"; y <= temp; if (temp="1001") then temp <= "0000"; end if; end if; end process; end Behavioral;
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Date:

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RTL Schematic

Technology Schematic

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Test Bench LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT BCD PORT( clk : IN std_logic; rst : IN std_logic; y : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs SIGNAL clk : std_logic := '0'; SIGNAL rst : std_logic := '1'; --Outputs SIGNAL y : std_logic_vector(3 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: BCD PORT MAP( y => y, clk => clk, rst => rst ); tb : PROCESS BEGIN
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wait for 1 ns; rst<='0'; CLK <= not CLK after 20 ns; -- Wait 100 ns for global reset to finish -- Place stimulus here -wait; -- will wait forever END PROCESS; END;

Waveform

Synthesis report:
* Final Report * ========================================================================= Final Results RTL Top Level Output File Name : BCD.ngr Top Level Output File Name : BCD Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs Cell Usage : # BELS # INV # LUT3 # LUT4 # FlipFlops/Latches # FDC # FDE # Clock Buffers

:6

:5 :2 :1 :2 :8 :4 :4 :1
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# BUFGP # IO Buffers # IBUF # OBUF

:1 :5 :1 :4

Device utilization summary: --------------------------Selected Device : 2s15cs144-5 Number of Slices: 4 out of 192 2% Number of Slice Flip Flops: 8 out of 384 2% Number of 4 input LUTs: 5 out of 384 1% Number of IOs: 6 Number of bonded IOBs: 6 out of 90 6% Number of GCLKs: 1 out of 4 25% Clock Information: ----------------------------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP |8 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: --------------------------------------------------------------------------+------------------------+-------+ Control Signal | Buffer(FF name) | Load | -----------------------------------+------------------------+-------+ rst | IBUF |4 | -----------------------------------+------------------------+-------+ Delay: Source: temp_0 (FF) Destination: temp_0 (FF) Source Clock: clk rising Destination Clock: clk rising

5.588ns (Levels of Logic = 1)

Data Path: temp_0 to temp_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------FDC:C->Q 5 1.292 1.740 temp_0 (temp_0) INV:I->O 1 0.653 1.150 Mcount_temp_lut<0>1_INV_0 (Mcount_temp_lut<0>) FDC:D 0.753 temp_0 ---------------------------------------Total 5.588ns (2.698ns logic, 2.890ns route) (48.3% logic, 51.7% route)

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PRACTICAL 9
Aim: Implement Design and Verify Constraints.
Implementing the Design

Date:

1. Select the counter source file in the Sources window. 2. Open the Design Summary by double-clicking the View Design Summary process in the Processes tab. 3. Double-click the Implement Design process in the Processes tab. 4. Notice that after Implementation is complete, the Implementation processes have a green check mark next to them indicating that they completed successfully without Errors or Warnings.

Figure 18: Post Implementation Design Summary

5. Locate the Performance Summary table near the bottom of the Design Summary. 6. Click the All Constraints Met link in the Timing Constraints field to view the Timing Constraints report. Verify that the design meets the specified timing requirements. 7. Close the Design Summary.

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Figure 19: All Constraints Met Report

Verify Design using Timing Simulation


Use the same self-checking test bench waveform you created in the previous section to verify the counter design after it has been completely implemented. Timing simulation verifies that the design operates within the constraints specified after routing and logic delays are accounted for. Run timing simulation as follows: 1. Select the Post-Route Simulation view from the drop-down list in the Source window. 2. Select counter_tbw in the Sources window. 3. Run timing simulation by double-clicking the Simulate Post-Place & Route Model process found in the Xilinx ISE Simulator process group.
4. Verify that the counter is counting up and down as directed by the stimulus on the DIRECTION port. 5. Verify that there are no ERRORs reported in the Simulator transcript window. 6. Zoom in to view the actual delay from the rising edge of CLOCK to a valid COUNT_OUT output change. 7. Close the simulation view.

Figure 23: Post-Place & Route Simulation

You have completed timing simulation of your design using the ISE Simulator.
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This is the last step in the design verification process. This section provides simple instructions for downloading the counter design to the Spartan-3 Starter Kit demo board. 1. Connect the 5V DC power cable to the power input on the demo board (J4). 2. Connect the download cable between the PC and demo board (J7). 3. Select Synthesis/Implementation from the drop-down list in the Sources window. 4. Select counter in the Sources window. 5. In the Processes window, click the + sign to expand the Generate Programming File processes. 6. Double-click the Configure Device (iMPACT) process. 7. The Xilinx WebTalk Dialog box may open during this process. Click Decline. 8. Select Disable the collection of device usage statistics for this project only and click OK. iMPACT opens and the Configure Devices dialog box is displayed. 9. In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG). 10. Verify that Automatically connect to a cable and identify Boundary-Scan chain is selected. 11. Click Finish. 12. If you get a message saying that there are two devices found, click OK to continue. The devices connected to the JTAG chain on the board will be detected and displayed in the iMPACT window. 13. The Assign New Configuration File dialog box appears. To assign a configuration file to the xc3s200 device in the JTAG chain, select the counter.bit file and click Open. 14. If you get a Warning message, click OK. 15. Select Bypass to skip any remaining devices. 16. Right-click on the xc3s200 device image, and select Program... The Programming Properties dialog box opens. 17. Click OK to program the device

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Figure 25: Assign New Configuration File

When programming is complete, the Program Succeeded message is displayed. On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running. 18. Close iMPACT without saving.

TEACHERS SIGN

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PRACTICAL 10
Aim: Introduction to MICROWIND software.
To use the MICROWIND program use the following procedure: Go to the directory in which the software has been copied (The default directory is MICROWIND) Double-click on the MicroWind icon

Date:

The MICROWIND display window is shown in Figure 1. It includes four main windows: the main menu, the layout display window, the icon menu and the layer palette. The cursor appears in the middle of the layout window and is controlled by using the mouse. The layout window features a grid that represents the current scale of the drawing, scaled in lambda () units and in micron. The lambda unit is fixed to half of the minimum available lithography of the technology. The default technology is a 0.8 m technology, consequently lambda is 0.4 m.

Fig. 1. The MICROWIND window as it appears at the initialization stage..


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The MOS device The MOS symbols are reported below. The n-channel MOS is built using polysilicon as the gate material and N+ diffusion to build the source and drain. The p-channel MOS is built using polysilicon as the gate material and P+ diffusion to build the source and drain.

nMOS

pMOS

Manual Design By using the following procedure, you can create a manual design of the n-channel MOS. The default icon is the drawing icon shown above. It permits box editing. The display window is empty. The palette is located in the lower right corner of the screen. A red color indicates the current layer. Initially the selected layer in the palette is polysilicon. The two first steps are illustrated in Figure 2. Fix the first corner of the box with the mouse. While keeping the mouse button pressed, move the mouse to the opposite corner of the box. Release the button. This creates a box in polysilicon layer as shown in Figure 2. The box width should not be inferior to 2 , which is the minimum width of the polysilicon box.

Fig. 2. Creating a polysilicon box.


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Change the current layer into N+ diffusion by a click on the palette of the Diffusion N+ button. Make sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the bottom of the drawing as in Figure 3. N-diffusion boxes are represented in green. The intersection between diffusion and polysilicon creates the channel of the nMOS device.

Fig. 3. Creating the N-channel MOS transistor Process Simulation Click on this icon to access process simulation. The cross-section is given by a click of the mouse at the first point and the release of the mouse at the second point. In the example below (Figure 4), three nodes appear in the cross-section of the n-channel MOS device: the gate (red), the left diffusion called source (green) and the right diffusion called drain (green), over a substrate (gray). The gate is isolated by a thin oxide called the gate oxide. Various steps of oxidation have lead to a thick oxide on the top of the gate.

Fig. 4. The cross-section of the nMOS devices.


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The physical properties of the source and of the drain are exactly the same. Theoretically, the source is the origin of channel impurities. In the case of this nMOS device, the channel impurities are the electrons. Therefore, the source is the diffusion area with the lowest voltage. The polysilicon gate floats over the channel, and splits the diffusion into 2 zones, the source and the drain. The gate controls the current flow from the drain to the source, both ways. A high voltage on the gate attracts electrons below the gate, creates an electron channel and enables current to flow. A low voltage disables the channel. Mos Characteristics Click on the MOS characteristics icon. The screen shown in Figure 5 appears. It represents the Id/Vd simulation of the nMOS device.

Fig. 5. N-Channel MOS characteristics. The MOS size (width and length of the channel situated at the intersection of the polysilicon gate and the diffusion) has a strong influence on the value of the current. In Figure 5, the MOS width is 12.8m and the length is 1.2m. Click on OK to return to the editor. A high gate voltage (Vg =5.0) corresponds to the highest Id/Vd curve. For Vg=0, no current flows. The maximum current is obtained for Vg=5.0V, Vd=5.0V, with Vs=0.0.
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The MOS parameters correspond to SPICE Level 3. You can alter the value of the parameters, or even access to Level 1. You may also skip to PMOS. You may as well add some measurements to fit the simulation. Finally, you can simulate devices with other sizes in the proposed list. Add Properties for Simulation Properties must be added to the layout to activate the MOS device. The most convenient way to operate the MOS is to apply a clock to the gate, another to the source and to observe the drain. The summary of available properties is reported below.

VDD property VSS property Clock property Node visible Pulse property

Apply a clock to the drain. Click on the Clock icon, click on the left diffusion. The Clock menu appears (See below). Change the name into drain and click on OK. A default clock with 3 ns period is generated. The Clock property is sent to the node and appears at the right hand side of the desired location with the name drain .

Fig. 6. The clock menu. Apply a clock to the gate. Click on the Clock icon and then, click on the polysilicon gate. The clock menu appears again. Change the name into gate and click on OK to apply a clock with 6 ns period.
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Watch the output: Click on the Visible icon and then, click on the right diffusion. The window below appears. Click OK. The Visible property is then sent to the node. The associated text s1 is in italic. The wave form of this node will appear at the next simulation.

Fig. 7. The visible node menu. Save before Simulation Click on File in the main menu. Move the cursor to Save as ... and click on it. A new window appears, into which you enter the design name. Type, for example, myMos. Use the keyboard for this and press . Then click on OK. After a confirmation question, the design is saved under that filename.

IMPORTANT : Always save BEFORE any simulation ! Analog Simulation Click on Simulate on the main menu. The timing diagrams of the inverter appear, as shown in Figure 8.

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Fig. 8. Analog simulation of the MOS device. When the gate is at zero, no channel exists so the node s1 is disconnected from the drain. When the gate is on, the source copies the drain. It can be observed that the nMOS device drives well at zero but at the high voltage. The final value is 4.2V, that is VDD minus the threshold voltage. Click on More in order to perform more simulations. Click on Stop to return to the editor. The MOS Model 1 For the evaluation of the current Ids between the drain and the source as a function of Vd,Vg and Vs, you may use the old but nevertheless simple MODEL 1 described below. The model 1 is accurate for channel length of more than 10m. CUT-OFF MODE. Vgs<0 Ids = 0 LINEAR MODE. Vds<Vgs-Vt, W Vds2 Ids = KP L ((Vgs-Vt)Vds- 2 )) SATURATED MODE. Vds>Vgs-Vt,

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Ids = KP/2

W (Vgs-Vt)2 L

In those formulas, W is the MOS channel width, L is the MOS channel length. VTO is the threshold voltage. The parameter KP is evaluated by the following formula: n is the mobility of electrons, p the mobility of holes, and TOX the gate oxide thickness.

KP(n) = n 0 S / TOX KP(p) = p 0 S / TOX where (0.8m technology)

n = 510 V.cm-2 r (SiO2)= 3.9 TOX = 150 nm

p = 270 V.cm-2 0 = 8.85 e -14 Farad/cm

When dealing with sub-micron technology, the model 1 is 200-300% higher than the measurements, as shown above for the prediction of a 20x0.8m n-channel MOS with KP computed according to 0.8m oxide thickness.

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The MOS Model 3 For the evaluation of the current Ids as a function of Vd,Vg and Vs between Drain and Source, we commonly use the following equations, close from the SPICE model 3 formulations. The formulations are derived from the model 1 and take into account a set of physical limitations in a semi-empirical way. CUT-OFF MODE. Vgs<0 Ids = 0 NORMAL MODE. Vgs>Von Ids = Keff with von = 1.2 vth vth = VTO + GAMMA( PHI vb vde = min ( vds, vdsat) vdsat = vc + vsat vsat = vgs-vth vc = VMAX

W Vde (1+KAPPA vds) Vde ((Vgs-vth))) LEFF 2

PHI )

vc2 vsat2

LEFF 0.06

LEFF = L - 2 LD Keff =

KP (1+ THETA(vgs- vth))

SUB-THRESHOLD MODE. Vgs<Von vds is replaced by von in the above equations. Ids = Ids(von,vds) e

q(vgs- von) nkT

In those formulas, W corresponds to the MOS channel width, L to the MOS channel length and VTO to the threshold voltage. The KP parameter is evaluated by the following formula in which : n is the mobility of electrons, p the mobility of holes, and TOX the gate oxide thickness.
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KP(n) = n 0 S / TOX KP(p) = p 0 S / TOX where (0.8 technology)

n = 510 V.cm-2 r (SiO2)= 3.9 TOX = 150 nm n=2 k = 1.381e-23 T = 300 K q = 1.6e-19 Temperature effects :

p = 270 V.cm-2 0 = 8.85 e -14 Farad/cm

n = n0 (T-300) e(-1.5) p = p0 (T-300) e(-1.5) vt = vt0-0.002(T-300) Tutorial on SPICE Level 3 Parameters Click on the MOS characteristics icon. The screen displays the Id/Vd simulation of the nMOS device. You can change the MOS parameter values directly on the screen and see the effect on the MOS simulation. Notice that KP includes the values of TOX (thin-oxide thickness) and of U0 (the carrier mobility) as described in the previous chapter. Fitting the model with measurements Click on Add Measurement. The program scans the current directory and displays the list of measurement files with and appendix called ".MES". Choose Es207_n20x20.MES. It corresponds to the measurements performed on a real MOS device with size W=20 m, L=20 m, fabricated by ATMEL ES2 in their 0.8 m technology (ES208.RUL). You should always start with measurements for a device with a very large width and length. The second order effects are reduced in such devices. The measured data is added to the drawing, as shown in the Figure 9.

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Fig. 9. The measured data file is added to the simulation (Es207_20x20.MES file). The principles for fitting the simulation with the measurements are described below. Click on Id vs. Vg. The curve shown in Figure 10 is used to fit VTO and Decrease VTO down to 0.7 in order to shift the curves to the right, and increase GAMMA up to 0.65 to adjust the set of curves. The measurement step for vbulk is 1.0V while the simulation step is 0.5 V in the figure.

Fig. 10. The Id/Vg to find VTO and fit GAMMA (Es207_20x20.MES file).
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Click on Id vs. Vd. Increase THETA to bend the curve in order to find a compromise. Although not satisfactory, the result is quite correct.

Fig. 10. Fitting the model with the measured data file (Es207_20x20.MES file). Now load a new measurement such as Es207_N20x0,8.mes. Click on Id vs. Vg Increase LD in order to fit the slope in the Id/Vg curve.

Fig. 11. Small channel MOS measurement (Es207_20x0,8.MES file).


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Click on Id vs. Vd. Adjust VMAX to fit the transition point between the linear and the saturated region according to the measurement. Next, adjust KAPPA to adapt the positive slope in the saturated region.

Fig. 11. Small channel MOS measurement (Es207_20x0,8.MES file). Click on Id(log)/Vg. Verify that the slope is correct in sub-threshold mode. If not you can adjust the slope using NSS. Notice that the measurement limit is in the order of the nA. This is why no reliable data is available below 10-9 A (Figure 12).

Fig. 12. Small channel MOS measurement in the sub-threshold region (Es207_20x0,8.MES file).
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The PMOS Transistor The p-channel transistor simulation features the same functions as the n-channel device. Click on pMOS in the menu. The software switches to the p-channel MOS simulation, as shown in Figure 13. Note that the pMOS gives only half of the maximum current given by the nMOS with the same device size.

Fig. 13. Simulation of the p-channel MOS.

Teachers sign

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