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Submitted in partial fulfillment for the award of the degree of



by PRASENJIT PODDER JOHN EBENEZER JOSEPHRAJ .D under the guidance of Mr. R. JEBAKUMAR, M.E., (Lecturer, School of Computer Science and Engineering) (10305265) (10305081)


(under section 3 of UGC Act,1956) SRM Nagar, Kattankulathur 603 203 Kancheepuram Dist MAY 2009

Certified that this project report DEVICE CONTROL BY SMS is the bonafide work of PRASENJIT PODDER (10305265) and JOHN EBENEZER JOSEPHRAJ .D (10305081) who carried out the project work under my supervision.






Date :


Our project controls the devices by SMS commands using cell phones. A GSM modem is placed near the devices to access the data. GSM modem is a device which operates as cell phone with only SMS technology. The GSM modem comes along with RS232 port, which is used by microcontroller to read the data present in the SIM card such as SMS. Then the process is to control corresponding equipment connected to microcontroller. The device to be controlled such as switch, light, fan etc is connected to the microcontroller through relay, which when energized or deenergized (Turns ON or OFF) respectively, the devices connected to it. Each device will be allotted to a number following by a particular word such as DEV. In order to turn ON/OFF the corresponding number should be text messaged to the GSM modem.












Muthamizhchelvan for providing us with an excellent infrastructure for developing this project.

We are greatly indebted to our Head of Department, Prof. C. Malathy, M.S., M.E., for her motivation, guidance throughout the course of this project work. She has been responsible for providing us with a lot of splendid opportunities, which has shaped our career. Her advice, ideas and constant support has engaged us on and helped us get through in difficult times.

We hereby acknowledge all those who are related to this work either directly or indirectly. We express my deep sense gratitude to our project guide Mr. R. Jebakumar, M.E for his valuable guidance, stimulating discussions throughout the period of this project.

We express my deep sense of gratitude to Mr. T. Sabhanayagam, M.Sc.,M.C.A.,M.S. Department of Computer Science, SRM University, Chennai, for his encouragement and support.

We are also thankful to the almighty and we will be failing in my duty if we do not express our indebtedness to our Department Staffs, Parents, and Friends for their support and encouragement.

Last but not the least we are thankful to all those, who are directly and indirectly related to this project.

LIST OF SYMBOLS AND ABBREVIATIONS LIST OF FIGURES 1. INTRODUCTION 2. LITERATURE REVIEW 3. SYSTEM ANALYSIS 3.1 Existing System 3.2 Proposed System 4. WORKING ENVIRONMENT 4.1 Hardware Specification 4.2 Software Specification 5. SYSTEM ANALYSIS 5.1 Block Diagram 5.2 Dataflow Diagram 5.3 Circuit Diagram 5.4 Power Supply Unit 5 6 7 10 14 14 15 16 16 16

17 18 19 19

5.5 Module Diagram 6. MODULE DESCRIPTION 6.1 Receiving Messages 6.2 Controlling The Units 6.3 Sending The Report 7. SYSTEM IMPLEMENTATION 7.1 LCD Coding 7.2 GSM Coding 8. SYSTEM TESTING 8.1 Unit Testing 8.2 Integration Testing 8.3 Verification And Validation Testing 8.4 User Acceptances Testing 8.5 Functional Testing

20 21 21 27 44 50 50 52 59 59 60 60 61 61

8.6 Performance Testing 8.7 Structure Testing 8.8 System Testing 9. CONCLUSION 10. FUTURE ENHANCEMENT 11. BIBLIOGRAPHY

61 61 62 63 63 64


1. SMS 2. MMS 3. WAP 4. WI-FI 5. GSM Communication 6. QoS 7. PC 8. CPU 9. SIM 10. RTOS 11. SWAP 12. GUI 13. ACK 14. TCP 15. PSU : : : : : : : : : : Quality of Service Personal Computer Central Processing Unit Subscriber Identity Module Real-Time Operating System Shared Wireless Access Protocol Graphical User Interface Acknowledgement Transmission Control Protocol Power Supply Unit : : : : : Short Messaging Service Multimedia Messaging Service Wireless Access Protocol Wireless Local Area Network Global System for Mobile

Figure No. Page Figure Title

Fig 1 Fig 2 Fig 3 Fig 4 Fig 5 Fig 6 Fig 7 Fig 8 Fig 9 Fig 10 Fig 11 Fig 12 Fig 13 Fig 14 Fig 15 Fig 16 Fig 17 Fig 18 Fig 19 Fig 20 Fig 21

Diagram of system components Operation block of switching module Flowchart of remote triggering based embedded server Transmitter Section Receiver Section Dataflow Diagram Circuit Diagram Power Supply Unit Module Diagram GSM Network Block Diagram of a Basic Power Supply Circuit Diagram of the Power Supply Pin out of the 7805 regulator IC Pin Diagram of Microcontroller Oscillator Connection External Clock Drive Configuration Block Diagram Times in Capture Mode Relay Driver Circuit LCD Display Basic 2051 Configuration

11 12 13 17 17 18 19 19 20 21 23 25 26 28 31 32 33 39 41 47 49

During the past decade, the world has seen the paradigm shift into mobile computing and communications. Much of the business and educational work is now heavily relying on the fast access to information and easy communication channels, irrespective of terrain and climate conditions. Ubiquitous wireless coverage has proven itself as of attractive option for B2B and B2C services as well as domestic applications. Remote Home Automation is the proof-of-concept for controlling electronic devices based on wireless messaging.

Smart home systems are expected to become key research area for ubiquitous and embedded system computing in coming years. In this project, a new scheme in smart home systems technology using embedded server for providing intelligent control of home appliances is proposed. A wireless based embedded server act as protocol glue that incorporates wireless option such as Short Message Service (SMS) router with wireless local area network (WI-FI) for intelligent automation and higher speed of home appliances connectivity. With remote triggering capabilities, it sits at the core of the home network, acts as residential gateway and enables bi-directional communication and data transfer channel among networked appliances in the home and across the Internet.

Smart home has been the talk of decade, predicted to be the next gigantic leap in the field of remote monitoring, has become an important research topic in recent years. In the past decade, research on smart homes has been moving towards applying the principles of ubiquitous computing. Smart home environment defined as one that is able to acquire and apply knowledge about home dwellers and their environment in order to meet the goals of comfort and efficiency.

The smart home adjusts its function to the inhabitants needs according to the information it collects from inhabitants, the computational system, and the context. With the availability of switched broadband services, a new opportunity exists for utilities between smart home systems technology and information service providers. However, the key issue is the interface between external information networks and the

home environment. One potential solution is through a remote triggering based embedded server, defined as an electronic subsystem which provides user interface, routing services and some management functionality to distribute and regulate the use of information services in the home.

There has been much talk about generic remote triggering based embedded server but all of todays solutions are proprietary. One of the core difficulties in putting the module in place is the uncertainty as to the services and facilities which consumers will come to demand in the medium to long term. Because large based systems which a service provider must install are considerable risks if new, or if refined services required by customers, thus a practical module must be inexpensive, easily maintainable from both software and hardware perspectives.

Devices in smart home environment can be done with variety of communications modes such as wireless LAN technology, dial-up modems, fiber technology and cellular network. The cellular network is getting widespread attention for transporting data, using GSM (global system for mobile communication) digital standard. GSM which provides always on connectivity and has low cost compared to other mobile communication option and also comprises high security so the information cannot be penetrated by any intruders. The most successful option utilizing GSM will be Short Message Services (SMS). In this paper, the system design, architecture and connectivity implementation will be presented.

A new networking market, the home networking, is rapidly emerging as the focus of both PC and consumer electronics vendors. For years vendors have been trying to develop home automation networks that tie together and control all home appliances (US middle class home has 30-50 devices that contain microprocessors). However, as we all know, the home automation market has not taken off as expected. This is due to the lack of a killer application that drives the market. Moreover, there are many technical challenges that face home networking, e.g. develop technology that works for each embedded system device regardless of its operating system while considering the fact that this solution has to be inexpensive, and easy to install and maintain. The main technological challenges have remained and even increased, i.e., the quest for high speed communication, but what has dramatically changed is the

existence of the killer application: the desire to access data, voice and video from the Internet from each location in the home while sharing a single Internet connection to the home.

In order to deliver quality multimedia communication that includes voice, video, data and control, the network has to provide quality of service (QoS) support. The ability to provide QoS for multiple users in to the customer premise gives service providers the ability to offer more than just Internet access. With QoS, service providers can expand their service offerings to include differentiated data services, voice and video. For example, a service provider can deploy integrated access devices that support both voice and data applications at the customer premise. To provide such support QoS has to be integrated into the backbone, last mile and home networking technologies. We survey some of the existing support for QoS in the backbone and last mile technologies and point out recommendations for such support in home networking technology.

A few years back, interconnecting home appliances was just a thought but now it has become a reality. Using the existing system, it is possible to monitor and control home appliances remotely.


A prototype of remote triggering based embedded server comprises of embedded CPU, switching module with Wi-Fi connectivity and SMS option. The aim is to design and implement a complete home appliance control over wireless and SMS technology. SMS is considered as first tier approach in this design. Being widely used, SMS with 160 characters are sufficient for device applications and provide ease of implementation into existing system or by interfacing with applications. A central theme in the implementation of this module is that the system architecture should be lightweight and platform independent. This is particularly important in smart home application where cost is king. Although the penetration of desktop PC technology into the home market is increasing on a daily basis, it is expected that most homes will not rely on home PC for control and monitoring in smart home environment. Instead a set-top-box style solution with low cost embedded CPU will satisfy this need for most end users.

Furthermore, two distinctly different approaches emerging in the field of smart home system: one approach is to incorporate TCP/IP networking even into the simplest consumer devices. Most available embedded processors used in consumer devices are not powerful enough to implement IP protocol. The second approach, which is more realistic, is to integrate existing established technologies, such as SMS and TCP/IP infrastructure. With this approach only one device- the remote triggering based embedded server need be smart enough to implement the IP protocol, and only one IP number need be assigned per home. Therefore, other technologies such as X10 and CEBus can be integrated with the module to provide full control functionalities of home appliances. The prototype consists of Wireless Access Point, Switching Module, Embedded CPU and SMS module. A Pocket PC will acts as Remote Terminal with capability on sending SMS and also with wireless connectivity. It will access the interface program stored in embedded CPU. The GSM module logs on to the GSM network to send or receive the data needed for monitoring

or controlling. Using RS-232 connection, the commands will be triggered by the switching module to control the home appliances. The whole system components are shown in Fig 1.

Fig. 1

a. Embedded CPU

The embedded CPU will acts as storage and remote application server for the module. In this design, the GSM dial-up and communication protocol are stored in embedded CPU. Wireless access point is attached with the embedded CPU. The software, written using Microsoft Embedded Visual Basic will reside in embedded CPU. The CPU supports 4 inputs and 4 outputs Ethernet connectivity and system memory up to 512MB. For this prototype implementation, the EB-3820[4] model has been used with Windows XP environment.

b. SMS Module Wireless Access Point is connected to the module via Embedded CPU. The SMS module consists of GSM modem. The SMS module acts like an interface between the embedded CPU and the GSM network. The module makes the system log on the GSM network and ready to make any communication or transferring of data. The module consists of Subscriber Identity Module card (SIM) to make the network identify the user and provide the user the GSM services. The module takes the AT

command from the Remote Terminal (Pocket PC) and send them to Switching Module by the GSM network. There are several types of SMS modules available in market, out of these types the focus of this paper will be on Enfora GSM1218A. The Enfora GSM1218A is intended for use in 900/1800 bands respectively. The module is used to make a connection to the GSM network and send/receive SMS.

c. Switching Module

Switching module consists of single chip and several relays that have functional protocol stack installed on complete Real-Time Operating System (RTOS), integrates all features needed for modern Ethernet and Internet applications. SC12 from Beck- IPC is used to implement the server. Network interface of SC12 including 10Base-T with RJ-45 connector. Switching Module is connected to the host server through RS-232 connection. The function of the switching module is listening to the incoming data, analyze the data and perform appropriate operation. The switching module controlled by a microcontroller to enable data processing mechanism. The operation block of switching module is illustrated in Fig. 2.

Fig. 2 The task of microcontroller centered on performing fetching mechanism to the incoming data from I/O interfaces and generates proper output switching signal. The switching signal will determine active path in switching unit for triggering control. There are 15 switching paths waiting for remote activation signal in switching unit. Relay set is the final block of switching module that represents desired responds of incoming signal. Each relay consumes 4 ms of delay time to perform triggering action

once activation signal received. However, it is allowable for remote triggering and monitoring purpose in smart home environment.


The proposed remote triggering based embedded servers for smart home environment uses embedded process incoming data from RS-232 by running C program and sends data via switching module to control any connected home appliances. Prior connecting to the switching module, the remote application server need to be activated and configured with wireless access point. Once the network cable plugged into the RJ-45 socket, the pre-defined network configurations automatically launch the network service in the remote application server in embedded CPU. These configurations include IP address, subnet mask, and gateway and DNS server. By connecting using Wi-Fi, the module provides a transparent interface of the local system to global network Using wireless connection or SMS, home user can trigger the desired function to the remote application server using mobile device. In this prototype implementation, Pocket PC with GSM feature is used to send SMS commands to the module. Once triggering signal received, the switching module will trigger the appropriate relay connected to home appliances. Fig.3 shows a flowchart of the remote triggering based embedded servers mechanism.



During the past decade, the world has seen the paradigm shift into mobile computing and communications. Much of the business and educational work is now heavily relying on the fast access to information and easy communication channels, irrespective of terrain and climate conditions.

Infrared technology which is a viable approach for line of sight point-to-point communication but because of its obstacle penetration inability it can not be used throughout the home.

Another wireless technology is Bluetooth. Using it we can communicate with any device from certain distance without stopping in any obstacles. This technology is much faster than infrared. Bluetooth supports both point-to-point and point-to-multipoint connection up to 10 meters range. Bluetooth implements authentication and encryption algorithms for security. The main security features are a challenge-response routine (for authentication), stream cipher (for encryption), and session key generation.

HomeRF is a working group (core members: Compaq Computer Corporation, Ericsson Enterprise Networks, HP, IBM, Microsoft, Motorola, Philips, Consumer Communications, Proxim and Symbionics) that has worked on a standard called Shared Wireless Access Protocol (SWAP). The goal is to enable interoperability between low cost consumer devices for both voice and data traffic in home and small office environment. SWAP supports two topology types: an Ad Hoc network and a Managed network. The Ad Hoc network supports only data traffic and the Managed network supports both data traffic and time critical communication, such as interactive voice.

Technologies that require new wires such as fibre optics and coaxial cable. These networks can provide very high speed communication but require the

installation of new communication infrastructure which may be cost prohibitive.


A few years back, interconnecting home appliances was just a thought but now it has become a reality. Using the existing system, it is possible to monitor and control home appliances remotely.

All these features can be accessed via hand-held devices that are used for attending and making calls.

Various challenges and requirements are faced when interacting with home appliances via mobile device. Firstly, device and technology heterogeneity require implementation of gateway function. Secondly, communication infrastructure between users and home appliances must support mobility of both, the user and the terminal as well as various forms of communication. At the same time, solutions must be user-friendly. Finally, new services should be easily deployable and devices accessible with minimal amount of extra effort.

Essentially, the same standardized mechanisms and framework should be utilized for different services. Provides secure, flexible and comfortable services inside and outside the home.


Required Hardware

GSM Modem Microcontroller

(AT89C51) Power Supply Unit LCD Display Relay driver Relays Max232

Microcontroller Programmer

Parallel Programmer

4.2 SOFTWARE SPECIFICATION: Keil vision Software

Embedded Tool


Embedded C

Programming Software

Easy Downloader


Transmitter Section:

Fig. 4 Receiver Section:

Fig. 5


Fig. 6


Fig. 7


Fig. 8




Fig. 9



Through the mobile phone text messages can be forwarded to the GSM modem which has been placed near the kit.

GSM Modem:

A GSM modem is a device which is used for mobile communication. A GSM modem is connected to each Telecontrol unit. The central server calls up each of the Telecontrol units in sample homes to pick up the data stored therein. aMap's technology architecture enables instant data collection from the sample homes as often as desired. It also enables conducting of instant opinion polls about the programs being telecast. The collected data is instantaneously incorporated into the aMap reports.

At present the central server calls up all the sample homes between 2:00 AM and 4:00 AM IST (Indian Standard Time) to collect the data. In case the data from some of the homes/ units can not be collected in the first attempt, the server dials that home again after 5 minutes, and makes the third attempt after 1.30 hours. After 3 trials, the server gives up. If non-collection of data is caused by the problems with cellular connection, the data can be collected later at any time over next seven days.

Fig. 10 The system generates a list of sample homes from which the data could not be collected. These failures are investigated on the same day. The possible causes of failure in data collection are 1. The Telecontrol power failure 2. The Telecontrol unit disconnection/disfunctionality

3. The sample home being locked 4. The problems with cellular connection etc. The Telecontrol system can respond to every possible use of a television screen, including viewing videos, playing TV games and using Tele text. Moreover, the design of the Telecontrol unit and its interactive system can be adapted to the psychological requirements of the panel household members, a key reason for its very high degree of acceptance and the widespread willingness to enter information. The central server calls up each of the data stored in Telecontrol using AT commands (Attentional Commands). * The AT commands, using for the system are given below, * AT+CMGR=ALL; is used to Read all sms in the sim card. * AT+CMGS= (Mobile No.); is used for sending sms. For completion of the process we have to give ctrl+z. eg: AT+CMGS=9840478140 * ATD (Mobile no.); is used for calling a specified no. eg: ATD 9840478140 Power Supply Unit:

A power supply (sometimes known as a power supply unit or PSU) is a device or system that supplies electrical or other types of energy to an output load or group of loads.

Fig.11 (A)

Fig.11 (B)

The first section is the TRANSFORMER. The transformer steps up or steps down the input line voltage and isolates the power supply from the power line. The RECTIFIER section converts the alternating current input signal to a pulsating direct current. However, as you proceed in this chapter you will learn that pulsating dc is not desirable. For this reason a FILTER section is used to convert pulsating dc to a purer, more desirable form of dc voltage. The final section, the REGULATOR, does just what the name implies. It maintains the output of the power supply at a constant level in spite of large changes in load current or input line voltages. Now that we know what each section does, let's trace an ac signal through the power supply. At this point you need to see how this signal is altered within each section of the power supply. Later on in the chapter you will see how these changes take place. In view B of figure 11, an input signal of 115 volts ac is applied to the primary of the transformer. The transformer is a step-up transformer with a turn ratio of 1:3. You can calculate the output for this transformer by multiplying the input voltage by the ratio of turns in the primary to the ratio of turns in the secondary; therefore, 115 volts ac 3 = 345 volts ac (peak-to- peak) at the output. Because each diode in the rectifier section conducts for 180 degrees of the 360-degree input, the output of the rectifier will be one-half, or approximately 173 volts of pulsating dc. The filter section, a network of resistors, capacitors, or inductors, controls the rise and fall time of the varying signal; consequently, the signal remains at a more constant dc level. You will see the filter process more clearly in the discussion of the actual filter circuits. The output of the filter is a signal of 110 volts dc, with ac ripple riding on the dc. The reason for the lower voltage (average voltage) will be explained later in this chapter. The regulator maintains its output at a constant 110-volt dc level, which is used by the electronic equipment (more commonly called the load). Simple 5V power supply for digital circuits Summary of circuit features

Brief description of operation: Gives out well regulated +5V output, output current capability of 100 mA

Circuit protection: Built-in overheating protection shuts down output when regulator IC gets too hot

Circuit complexity: Very simple and easy to build Circuit performance: Very stable +5V output voltage, reliable operation Availability of components: Easy to get, uses only very common basic components

Design testing: Based on datasheet example circuit, I have used this circuit successfully as part of many electronics projects

Applications: Part of electronics devices, small laboratory power supply Power supply voltage: Unregulated DC 8-18V power supply Power supply current: Needed output current + 5 mA Component costs: Few dollars for the electronics components + the input transformer cost CIRCUIT DESCRIPTION: This circuit is a small +5V power supply, which is useful when experimenting

with digital electronics. Small inexpensive wall transformers with variable output voltage are available from any electronics shop and supermarket. Those transformers are easily available, but usually their voltage regulation is very poor, which makes then not very usable for digital circuit experimenter unless a better regulation can be achieved in some way. The following circuit is the answer to the problem. This circuit can give +5V output at about 150 mA current, but it can be increased to 1 A when good cooling is added to 7805 regulator chip. The circuit has over overload and therminal protection.

Fig.12 Circuit diagram of the power supply.

The capacitors must have enough high voltage rating to safely handle the input voltage feed to circuit. The circuit is very easy to build for example into a piece of Vero board.


Pin out of the 7805 regulator IC.

1. Unregulated voltage in 2. Ground 3. Regulated voltage out COMPONENT LIST:

7805 regulator IC 100 uF electrolytic capacitor, at least 25V voltage rating 10 uF electrolytic capacitor, at least 6V voltage rating 100 nF ceramic or polyester capacitor MODIFICATION IDEAS MORE OUTPUT CURRENT If you need more than 150 mA of output current, you can update the output current up to 1A doing the following modifications:

Change the transformer from where you take the power to the circuit to a model which can give as much current as you need from output

Put a heat sink to the 7805 regulator (so big that it does not overheat because of the extra losses in the regulator)

OTHER OUTPUT VOLTAGES If you need other voltages than +5V, you can modify the circuit by replacing the 7805 chips with another regulator with different output voltage from regulator 78xx chip family. The last numbers in the chip code tells the output voltage. Remember that the input voltage must be at least 3V greater than regulator output voltage to otherwise the regulator does not work well. 6.2 CONTROLLING THE UNITS: MICROCONTROLLER:

FEATURES: Compatible with MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory o Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 128 x 8-bit Internal RAM 32 Programmable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down Modes

DESCRIPTION: The AT89C51 is a low-power, high-performance CMOS 8-bit Microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications.


Fig. 14

PIN DESCRIPTION: VCC - Supply voltage. GND - Ground.

PORT 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this

mode P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.

PORT 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups Port 1 also receives the low-order address bytes during Flash programming and verification. PORT 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16bit addresses (MOVX @ DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

PORT 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification.

RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.


External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.


Fig.15 IDLE MODE In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and

the entire special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. EXTERNAL CLOCK DRIVE CONFIGURATION:

Fig. 16


Fig.17 The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, five vector two-level interrupt architecture, a full duplex serial port, and on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to

zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset

POWER-DOWN MODE: In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

PROGRAM MEMORY LOCK BITS: On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.

PROGRAMMING THE FLASH The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming

interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low voltage programming mode provides a convenient way to program the AT89C51 inside the users system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.

The AT89C51 code memory array is programmed byte-by byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.

PROGRAMMING ALGORITHM: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps. Input the desired memory location on the address lines. Input the appropriate data byte on the data lines. Activate the correct combination of control signals. Raise EA/VPP to 12V for the high-voltage programming mode. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. DATA POLLING: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed,

true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.

READY/BUSY: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.

PROGRAMS VERIFY: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.

CHIP ERASE: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10ms. The code array is written with all 1s. The chip erase operation must be executed before the code memory can be re-programmed.

READING THE SIGNATURE BYTES: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming

PROGRAMMING INTERFACE Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is self timed and once initiated, will automatically time itself to completion. All

major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.

SPECIAL FUNCTION REGISTERS A map of the on-chip memory area called the Special Function Register (SFR). Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.

TIMER 2 REGISTERS Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) is the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

INTERRUPT REGISTERS The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.

DATA MEMORY The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). MOV @R0, #data Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

TIMER 0 AND 1 Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.

TIMER 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.

CAPTURE MODE In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2

performs the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.

AUTO-RELOAD (UP OR DOWN COUNTER) Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. TIME IN CAPTURE MODE:

Fig. 18

Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this mode, the T2EX pin controls the direction of the count. Logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH

and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. Logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.

PROGRAMMABLE CLOCK OUT A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4MHz at a 16 MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 s a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.

UART The UART in the AT89C52 operates the same way as the UART in the AT89C51.

INTERRUPTS The AT89C52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port

interrupt. These interrupts are all shown in Figure 6. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table shows that bit position IE.6 is unimplemented. In the AT89C51, bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.


A relay is an electrical switch that opens and closes under the control of another electrical circuit. In the original form, the switch is operated by an electromagnet to open or close one or many sets of contacts. It was invented by Joseph Henry in 1835. Because a relay is able to control an output circuit of higher power than the input circuit, it can be considered, in a broad sense, to be a form of an electrical amplifier

Fig. 19 Relays are components which allow a low-power circuit to switch a relatively high current on and off, or to control signals that must be electrically isolated from the controlling circuit itself.

To make a relay operate, you have to pass a suitable pull-in and holding current (DC) through its energizing coil. And generally relay coils are designed to operate from a particular supply voltage - often 12V or 5V, in the case of many of the small relays used for electronics work. In each case the coil has a resistance which will draw the right pull-in and holding currents when it is connected to that supply voltage. So the basic idea is to choose a relay with a coil designed to operate from the supply voltage youre using for your control circuit (and with contacts capable of switching the currents you want to control), and then provide a suitable relay driver circuit so that your low-power circuitry can control the current through the relay coil. Typically this will be somewhere between 25mA and 70mA.

Often your relay driver can be very simple, using little more than an NPN or PNP transistor to control the coil current. All your low-power circuitry has to do is provide enough base current to turn the transistor on and off

In A, NPN transistor Q1 (say a BC337 or BC338) is being used to control a relay (RLY1) with a 12V coil, operating from a +12V supply. Series base resistor R1 is used to set the base current for Q1, so that the transistor is driven into saturation (fully turned on) when the relay is to be energized. That way, the transistor will have minimal voltage drop, and hence dissipate very little power as well as delivering most of the 12V to the relay coil. RLY1 needs 50mA of coil current to pull in and hold reliably, and has a resistance of 240W so it draws this current from 12V. Our BC337/338 transistor will need enough base current to make sure it remains saturated at this collector Current level. To work this out, we simply make sure that the base current is greater than this collector current divided by the transistor is minimum DC current gain hFE. So as the BC337/338 has a minimum hFE of 100 (at 100mA), we had need to provide it with at least 50mA/100 = 0.5mA of base current. In practice, youd give it roughly double this value, say 1mA of base current, just to make sure it does saturate. So if your control signal Vin was switching between 0V and +12V, youd give R1 a value of say 11kW, to provide the 1mA of base current needed to turn on both Q1 and the relay.

If our relay has a coil resistance of say 180W, so that it draws say 67mA at 12V, wed need to reduce R1 to say 8.2kW, to increase the base current to about 1.4mA. Conversely if the relay coil is 360W and draws only 33mA, we could increase R1 to 15kW, giving about 0.76mA of base current. Each time we go for about twice the relay coil current divided by Q1s hFE

As you can see a power diode D1 (1N4001 or similar) is connected across the relay coil, to protect the transistor from damage due to the back-EMF pulse generated in the relay coils inductance when Q1 turns off.

The basic NPN circuit in diagram A is fine if you want the relay to energize when your control voltage Vin is high (+12V), and be off when Vin is low (0V). But what if you want the opposite? That is where youd opt for a circuit like that shown in diagram B, using a PNP transistor like the BC327 or BC328. This is essentially the same circuit as in A, just swung around to suit the PNP transistor is polarity. This time transistor Q2 will turn on and energize the relay when Vin is low (0V), and will turn off when Vin is high (+12V).

Otherwise everything works just as before, and the value of base resistor R2 is worked out in the same way as for R1. In fact because the minimum hFE of the BC327/328 PNP transistors is also 100 at 100mA, you could use exactly the same values of R2 to suit each relay resistance/current. The simple transistor driver circuits of A and B are very low in cost, and are generally fine for driving most relays. However there may be occasions, such as when your control circuit is based on CMOS logic, where the base current needed by these circuits is a bit too high.

For these situations the circuit shown in C might be of interest, because it needs rather less input current. As you can see it uses a readily available and very low cost 555 IC as the relay driver, plus only one extra component: bypass capacitor C1. Although we normally think of the 555 as a timer/oscillator, its actually very well suited for driving a small relay. Output pin 3 can both source and sink 200mA (enough to handle most small relays comfortably), and the internal flip flop which controls its output stage is triggered swiftly between its two states by internal comparators connected to the two sensing inputs on pins 2 and 6. When these pins are

taken to a voltage above 2/3 the supply voltage, the output switches low (0V); then they are taken below 1/3 the supply voltage, the output swings high. And the 555 can happily work at 5V, as you can see, so its very suitable for driving a 5V relay coil from this supply voltage.

Because the sensing inputs of the 555 are voltage sensing and need only a micro amp or so of current, the value of input resistor R3 can be much larger than for the transistor driver circuits. Typically youd use a value of say 100kW, or even 220kW for a circuit operating from 12V. Although the push-pull output stage of the 555 automatically shunts the relay coil when pin 3 is high, damping the back-EMF, it is probably still a good idea to fit diode D3 as well- especially when using this circuit from a 12V supply. That is because the negative-going back-EMF pulse could cause damage to the transistors inside the 555. Capacitor C1 is fitted to make sure that the 555 doesnt turn on the relay in response to noise spikes on the supply line. By the way if you need the very low input current of this circuit, but want to make the relay operate when Vin is low rather than high, simply connect the relay coil and D3 from pin 3 of the 555 to ground just like the arrangement shown in diagram B.

Finally in all of these circuits, it is a good idea to fit the supply line of the relay/driver stage with a reasonably high value of bypass capacitor (say 100uF), to absorb the current transients when the relay turns on and off. This will ensure more reliable operation, and help prevent interference with the operation of your control circuitry.


LCD A liquid crystal display (commonly abbreviated LCD) is a thin, flat display device made up of any number of color or monochrome pixels arrayed in front of a light source or reflector. It is often utilized in battery-powered electronic devices because it uses very small amounts of electric power.

Overview Each pixel of an LCD typically consists of a layer of molecules aligned between two transparent electrodes, and two polarizing filters, the axes of transmission of which are (in most of the cases) perpendicular to each other. With no liquid crystal between the polarizing filters, light passing through the first filter would be blocked by the second (crossed) polarizer. The surfaces of the electrodes that are in contact with the liquid crystal material are treated so as to align the liquid crystal molecules in a particular direction. This treatment typically consists of a thin polymer layer that is unidirectionally rubbed using, for example, a cloth. The direction of the liquid crystal alignment is then defined by the direction of rubbing. Before applying an electric field, the orientation of the liquid crystal molecules is determined by the alignment at the surfaces. In a twisted nematic device (still the most common liquid crystal device), the surface alignment directions at the two electrodes are perpendicular to each other, and so the molecules arrange themselves in a helical structure, or twist. Because the liquid crystal material is birefringent, light passing through one polarizing filter is rotated by the liquid crystal helix as it passes through the liquid crystal layer, allowing it to pass through the second polarized filter. Half of the incident light is absorbed by the first polarizing filter, but otherwise the entire assembly is transparent. When a voltage is applied across the electrodes, a torque acts to align the liquid crystal molecules parallel to the electric field, distorting the helical structure (this is resisted by elastic forces since the molecules are constrained at the surfaces). This reduces the rotation of the polarization of the incident light, and the device appears gray. If the applied voltage is large enough, the liquid crystal molecules in the center of the layer are almost completely untwisted and the polarization of the incident light is not rotated as it passes through the liquid crystal layer. This light will then be mainly polarized perpendicular to the second filter, and thus be blocked and the pixel will appear black. By controlling the voltage applied across the liquid crystal layer in each pixel, light can be allowed to pass through in varying amounts thus constituting different levels of gray.

The optical effect of a twisted nematic device in the voltage-on state is far less dependent on variations in the device thickness than that in the voltage-off state. Because of this, these devices are usually operated between crossed polarizers such that they appear bright with no voltage (the eye is much more sensitive to variations in the dark state than the bright state). These devices can also be operated between parallel polarizers, in which case the bright and dark states are reversed. The voltageoff dark state in this configuration appears blotchy, however, because of small thickness variations across the device. Both the liquid crystal material and the alignment layer material contain ionic compounds. If an electric field of one particular polarity is applied for a long period of time, this ionic material is attracted to the surfaces and degrades the device performance. This is avoided either by applying an alternating current or by reversing the polarity of the electric field as the device is addressed (the response of the liquid crystal layer is identical, regardless of the polarity of the applied field). When a large number of pixels is required in a display, it is not feasible to drive each directly since then each pixel would require independent electrodes. Instead, the display is multiplexed. In a multiplexed display, electrodes on one side of the display are grouped and wired together (typically in columns), and each group gets its own voltage source. On the other side, the electrodes are also grouped (typically in rows), with each group getting a voltage sink. The groups are designed so each pixel has a unique, unshared combination of source and sink. The electronics or the software driving the electronics then turns on sinks in sequence, and drives sources for the pixels of each sink. Specifications Important factors to consider when evaluating an LCD monitor:

Resolution: The horizontal and vertical size expressed in pixels (e.g., 1024x768). Unlike CRT monitors, LCD monitors have a native-supported resolution for best display effect.

Dot pitch: The distance between the centers of two adjacent pixels. The smaller the dot pitches size, the fewer granularities are present, resulting in a

sharper image. Dot pitch may be the same both vertically and horizontally, or different (less common).

Viewable size: The size of an LCD panel measured on the diagonal (more specifically known as active display area).

Response time: The minimum time necessary to change a pixel's color or brightness.

Matrix type: Active or Passive. Viewing angle: (coll., more specifically known as viewing direction). Color support: How many types of colors are supported (coll., more specifically known as color gamut).

Brightness: The amount of light emitted from the display (coll., more specifically known as luminance).

Contrast ratio: The ratio of the intensity of the brightest bright to the darkest dark.

Aspect ratio: The ratio of the width to the height (for example, 4:3, 16:9 or 16:10).

Input ports (e.g., DVI, VGA, LVDS, or even S-Video and HDMI).

Using the LCD Module with an 8051 Microcontroller The LCD Module can easily be used with an 8051 microcontroller such as the AT89C2051 included with the microcontroller beginner kit. The LCD Module comes with a 16 pin connector. This can be plugged into the breadboard as shown below.

Fig. 20

The pins on the 16 pin connector of the LCD Module are defined below. The table also shows how to connect each pin to the 2051 microcontroller. To connect the LCD Module to a standard 40 pin 8051, use the pin names listed below to find the correct pin number on the 8051 microcontroller. The example programs below do not need to be modified to work with a 40 pin 8051. 2051 Function Pin Number & Name Data Line 6 18, P1.6 Data Line 1 13, P1.1 Power 5VDC Not Connected Display Adjust Data Line 7 19, P1.7 Data Line 2 14, P1.2 Ground 2051 Function Pin Number & Name LCD RS Data Line 5 LCD Read/Write Data Line 0 7, P3.3 17, P1.5 6, P3.2

LCD Connector 1 2 3

LCD Connector 16 15 14


12, P1.0

5 6 7 8

12 11 10 9

Data Line 4 LCD Enable Data Line 3 Not Connected

16, P1.4 8, P3.4 15, P1.3

The basic 2051 configuration is shown below. Build this circuit and then you will be ready to add the LCD Module.

Fig. 21 After you have built a basic 2051 configuration as shown above, you can connect the LCD Module as shown in the table above. In addition, you need to add the following connections. Connect LCD Pin 3 to Vcc (5 Volts). Connect LCD Pin 8 to Ground. Connect a 510 ohm resistor between LCD Pin 5 and ground. Connect a 2.2k ohm resistor from LCD Pin 2 and Vcc. Connect a 2.2k ohm resistor from LCD Pin 13 to Vcc.



7.1 LCD Coding:

#include<reg51.h> void lcd_command(unsigned char); void lcd_display(unsigned char); void init(); void checkb(); void front_lcd();

sbit rs=P3^5; sbit rw=P3^6; sbit en=P3^7; sbit busy=P1^7; void lcd_command(unsigned char value) { unsigned int r; rs=0; rw=0; P1=value; en=1; for(r=0;r<1000;r++); en=0; checkb(); } void front_lcd() { lcd_command(0X01); lcd_command(0X80); } void init() {

lcd_command(0x38); lcd_command(0x38); lcd_command(0x0c); lcd_command(0X01); lcd_command(0X0e); lcd_command(0X80); } void checkb() { rs=0; rw=1; busy=1; en=0; //for(r=0;r<1000;r++); en=1; while(busy==1); } void lcd_display(unsigned char p) { rs=1; rw=0; P1=p; en=1; //for(r=0;r<1000;r++); en=0; checkb(); } 7.2 GSM Coding:

#include<reg51.h> #include<stdio.h> #include<string.h> sbit en=P3^7; sbit rw=P3^6; //LCD

sbit rs=P3^5; //sfr datas=0x90; sbit busy=P1^7; sbit sw=P2^0; //sbit sen = P3^2; sbit mot1 = P2^2; sbit mot2 = P2^3; sbit mot3 = P2^4; sbit mot4 = P2^5; void lcd_init(); void lcddtw(unsigned char); void lcdcmw(unsigned char); unsigned int h; unsigned char sa,sar,count=0; unsigned char temp; unsigned char a,b,c,d,e; unsigned char sak; unsigned long you; unsigned char str[20]; unsigned char lat[16]; unsigned char lon[16]; //code unsigned char pdf[]="AT+CMGF=1"; code unsigned char dele[]="AT+CMGD=1"; code unsigned char wel[]="WELCOME"; code unsigned char rea[]="READY"; code unsigned char sat[]="STATUS";

code unsigned char send[]="AT+CMGS=\"9840478140\""; code unsigned char mot1[]="STUD1 DEV1 ON"; code unsigned char mot1[]="STUD1 DEV1 OFF";

code unsigned char mot2[]="STUD1 DEV2 ON"; code unsigned char mot2[]="STUD1 DEV2 OFF";

code unsigned char mot3[]="STUD1 DEV3 ON"; code unsigned char mot3[]="STUD1 DEV3 OFF";

code unsigned char mot4[]="STUD1 DEV4 ON"; code unsigned char mot4[]="STUD1 DEV4 OFF";

code unsigned char read[]="AT+CMGR=1"; void checkb(); void lcdcmw(unsigned char value) { rs=0; rw=0; P1=value; en=1; en=0; checkb(); }

void lcd_init() { lcdcmw(0x38); lcdcmw(0x38); lcdcmw(0X0e); lcdcmw(0X06); lcdcmw(0X01); lcdcmw(0X0e); lcdcmw(0X80); } void checkb() { rs=0; rw=1; busy=1; en=0;

en=1; while(busy==1); } void lcddtw(unsigned char p) { rs=1; rw=0; P1=p; en=1; en=0; checkb(); } void se1() { TMOD=0x20; SCON=0x50; TH1=0xfd; TI=RI=0; TR1=1; } void tx(unsigned char t) { SBUF=t; while(TI==0); TI=0; } void main() { //unsigned char at[]="AT"; unsigned char sak; unsigned long i,j; mot1 = 0 ; mot2 = 0 ; mot3 = 0 ;

mot4 = 0 ; //sen = 0 ; se1(); lcd_init(); for(sak=0;wel[sak]!='\0';sak++) { lcddtw(wel[sak]); } for(h=0;h<40000;h++); while(1) { lcdcmw(0x01); lcdcmw(0x80); for(sak=0;rea[sak]!='\0';sak++) { lcddtw(rea[sak]); } lcdcmw(0x01); lcddtw('I'); for (j=0;j<50000;j++); for(sa=0;read[sa]!='\0';sa++) { tx(read[sa]); } for(h=0;h<10000;h++); tx(0x0d); do { j=j+1; while(RI==0); temp=SBUF; str[j]=temp; RI=0; }

while(1); lcdcmw(0x01); lcdcmw(0x80); for(i=0;str[i]!='\0';i++) { lcddtw(str[i]); } for(h=0;h<50000;h++); if(strcmp(str,mot11)==0) { lcdcmw(0x01); lcdcmw(0x80); for(h=0;mot11[h]!='\0';h++) lcddtw(mot11[h]); mot1=1; for(h=0;h<40000;h++); } else if(strcmp(str,mot10)==0) { lcdcmw(0x01); lcdcmw(0x80);

for(h=0;mot10[h]!='\0';h++) lcddtw(mot10[h]); mot1=0; for(h=0;h<40000;h++); } else if(strcmp(str,mot21)==0) { lcdcmw(0x01); lcdcmw(0x80); for(h=0;mot21[h]!='\0';h++) lcddtw(mot21[h]); mot2=1;

for(h=0;h<40000;h++); } else if(strcmp(str,mot20)==0) { lcdcmw(0x01); lcdcmw(0x80); for(h=0;mot20[h]!='\0';h++) lcddtw(mot20[h]); mot2=0; for(h=0;h<40000;h++); } else if(strcmp(str,gps_d)==0) { send_data(); } } }

TESTING: Testing plays a vital role to reach the present in any system. It is the major quality control measure used to determine the status and usefulness of the system. Its basic function is to find the errors in the software by examining all the possible loopholes. The goal testing is to find the coding errors, uncovered requirements, invalid acceptance, storage of data, etc. Testing is vital to the success of the system. System testing makes a logical assumption that if all parts of the system are correct, the goal will be successfully achieved. The candidate system is subject to a variety of test, online responses, volume, stress, recovery, security and usability tests. A serious of tests are performed for the proposed system is ready for user acceptance testing The testing methodologies are 12. Unit Testing 13. Integration Testing 14. Verification And Validation Testing 15. User Acceptances Testing 16. Functional Testing 17. Performance Testing 18. Structure Testing 19. System Testing

8.1 UNIT TESTING: For successful implementation, each and module of a new system is tested separately to rectify within its boundaries. Detailed design description is used as a guide in this process. The database was checked with the sample data to ensure the normal form. Under this the following test were done

Interface Testing: To assure that information properly flows in and out of program unit.

Data Structure Testing: To ensure that data is properly stored in underlying tables.

Independent Path Testing: All independent paths through module were executed at least once to assure that they are behaving as per expectations.

8.2 INTEGRATION TESTING: Integration testing is the systematic testing for constructing tests to uncover errors associated within the interface. The objective is to take unit tested modules and build a program structure. All modules are combined and tested as a whole. Here correction is difficult because the isolation of causes is complicated by the vast expanses of the entire program. There are two types of integration in non-incremental integration; all modules are combined in advance. Correction is difficult because isolation of causes is complicated by the vast expanse of the entire program. In incremental integration, the program is constructed and tested in small segments, where error are easier to isolate and correct; interfaces are more likely to be tested completely; and a systematic test may be applied.

8.3 VERIFICATION AND VALIDATION TESTING: The system has been verified and validated using Test data Live data

Verified With Test Data: In this case of testing, the data was developed artificially and applied to the system. The result of the system was checked to ensure that, it satisfies the specification of the system. Each module in this system has been tested independently and finally tested as a package.

Verified With Data: In this case the real data are applied to the system and the result is checked with the original result that was manually calculated. Verification is a rigorous mathematic demonstration that source code conforms to its specification. Validation is the process of evaluating software at the end of software development process to determine the compliance with requirements.

8.4 USER ACCEPTANCE TESTING: It is a key factor for the success of any system. The system under consideration is tested for user acceptance by constantly in touch with the prospective system users at the time of developing and making changes wherever required.

8.5 FUNCTIONAL TESTING: Functional testing specifies typical operating condition, typical input values and expected results. Functional test also test behavior just inside, on and beyond the functional boundaries. Examples of functional boundary testing include a real valued square root routine, with small positive numbers zero and negative numbers.

8.6 PERFORMANCE TESTING: Performance tests are designed to verify response time under varying load percentage of execution time spent in various segments of program.

8.7 STRUCTURE TESTING: Structure test are connected with examining the internal processing logic of the software system. The particular routine are called logical paths are traversed. Through the routines are objects of interest. The goal of structure testing is to travel a specified number of paths through the routines to establish the thoroughness of testing.


When a system is developed, it is hoped that it performs properly. In practice, however some errors always occur. The main purpose of testing an information system is to find the error and correct them. A successful test is one, which finds an error

Objectives of System Testing To ensure during operating the system will perform as per specification, To make sure that the system meets user requirements during the operation. To verify that the controls incorporated in the function as intended. To see that when correct inputs are fed to the system, the outputs are correct. To make sure during operation, incorrect input, process and output will be detected.

The scope of the system test should include both manual operations and computerized ones. Operation system is a comprehensive evaluation of the programs, manual procedures, computer operations and controls

System testing is the process of checking if the developed system is working according to the original objectives and recruitments. All testing needs to be conducted in accordance to the test conditions specified earlier. This will ensure that the test coverage meets the requirements and that testing is done in systematic manner. One can compare the new system by taking the earlier processed data will appropriate level on the current system. While doing so the present system will identify the errors and omissions and testing these is especially crucial.

This project is based on concept of GSM mobile network to control the devices (Home Appliances) by sms commands. This signal is processed by a micro-

controller to send a signal such as sms to the GSM modem by the owners when they are out of place.

The household appliances can be controlled just through sending an sms from anywhere by the user. This instantly provides the status of the devices which has been controlled.


In future process we will add more controls to the application and we will enhance the time taken for this process.

11. Bibliography

o Jinnah University for Women, 5/C North Nazimabad, Karachi o Muhammad Saqib Ilyas o N.E.D. University of Engineering and Technology, Karachi REMOTE TRIGGERING BASED EMBEDDED SERVER FOR SMART HOME ENVIRONMENT o Thinagaran Perumal, Abd Rahman Ramli, Chui Yew Leong, o Intelligent Systems and Robotics Laboratory o Institute of Advanced Technology University Putra, Malaysia LCD o Liquid Crystal Displays: Addressing Schemes and Electro-Optical Effects by Ernst Lueder, Ernst Lauder o Electronic Display Measurements: Concepts, Techniques and Instrumentation by Peter A. Keller GSM o Introduction to GSM o Physical Channels, Logical Channels, Network, and Operation Author: Lawrence Harte EMBEDDED o Embedded software The Work Colin Walls