DATA SHEET DATA SHEET

MOS INTEGRATED CIRCUIT

PD78C10A, 78C11A, 78C12A

8-BIT SINGLE-CHIP MICROCOMPUTER (WITH A/D CONVERTER)

DESCRIPTION
The PD78C11A is a CMOS 8-bit microprocessor which can integrate 16-bit ALU, ROM, RAM, an A/D converter, a multi-function timer/event counter, and a general-purpose serial interface into a single chip, then expand the memory (ROM/RAM) up to 60K bytes externally. The PD78C10A is a ROM-less product of the PD78C11A, and can directly address the external memory up to 64k bytes. The PD78C12A is a product which has more built-in ROM capacity than the PD78C11A, and its memory (ROM/RAM) can be externally extended up to 56K bytes. The

PD78C10A, PD78C11A, and PD78C12A operated at low power consumption, because they have a CMOS construction. Also, they can hold data with low power consumption by using standby function. On-chip PROM products, PD78CP14 and PD78CP18 which are ideal for evaluation or preproduction use during system development, early start-up and short-run multiple-device production of application sets, are available.

FEATURES
Abundant 159 types of instructions : 87AD series instruction set, multiplication/division instructions, 16-bit operation instructions Instruction cycle : 0.8 s (at 15 MHz operation) On-chip ROM : 4096W 8 (PD78C11A), 8192W 8 (PD78C12A) Non (PD78C10A) On-chip RAM : 256W 8 High-precision 8-bit A/D converter : 8 analog inputs General-purpose serial interface : Asynchronous, synchronous, I/O interface mode Multi-function 16-bit timer/event counter Two 8-bit timers I/O lines : 32 (PD78C10A), 44 (PD78C11A, 78C12A) Interrupt function (external - 3, internal - 8) : Non-maskable interrupt 1, maskable interrupt 10 Standby function : HALT mode, hardware/software STOP mode Zero-cross detection function : (2 inputs) On-chip pull-up resistor (port A, B, C: PD78C11A, 78C12A only) by mask option Caution The PD78C10A does not hava a mask option.

The information in this document is subject to change without notice.

Document No. IC-2678C (O. D. No. IC-7769E) Date Published February 1995 P Printed in Japan

The mark 5 shows major revised points.

1990

PD78C10A,78C11A,78C12A

ORDERING INFORMATION
Ordering Code Package 64-pin 64-pin 64-pin 68-pin 64-pin 64-pin 64-pin 64-pin 68-pin 64-pin 64-pin 64-pin 64-pin 68-pin plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic shrink DIP (750 mil) QFP (14 20 mm) QUIP QFJ ( 950 mil) shirink DIP (750 mil) QFP (14 20 mm) QUIP QUIP straight QFJ ( 950 mil) shrink DIP (750 mil) QFP (14 20 mm) QUIP QUIP straight QFJ ( 950 mil) On-Chip ROM None None None None Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM Mask ROM

PD78C10ACW PD78C10AGF-3BE PD78C10AGQ-36 PD78C10AL PD78C11ACW- PD78C11AGF--3BE PD78C11AGQ--36 PD78C11AGQ--37 PD78C11AL- PD78C12ACW- PD78C12AGF--3BE PD78C12AGQ--36 PD78C12AGQ--37 PD78C12AL-

PD78C10A,78C11A,78C12A

PIN CONFIGURATION (TOP VIEW)

For PD78C10ACW, PD78C10AGQ-36, PD78C11ACW-, PD78C11AGQ--36/37, PD78C12ACW-, PD78C12AGQ--36/37.
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0/T X D PC1/R X D PC2/SCK PC3/INT2 PC4/TO PC5/CI PC6/CO0 PC7/CO1 NMI INT1 MODE1 RESET MODE0 X2 X1 V SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 V DD STOP PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD AV DD V AREF AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AV SS

For PD78C10AGF-3BE, PD78C11AGF--3BE, PD78C12AGF--3BE

V AREF AV DD AN7 AN6 34 AN5 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 PD2 PD1 PD0 ALE PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 WR 39 RD 38

PD3 PD4 PD5 PD6 PD7 STOP V DD PA0 PA1 PA2 PA3 PA4 PA5

51 52 53 54 55 56 57 58 59 60 61 62 63 64

50

49

48

47

46

45

44

43

42

41

40

37

36

35

AN4 AN3 AN2 AN1 AN0 AV SS V SS X1 X2 MODE0 RESET MODE1 INT1

10

11

12

13

14

15

16

17

18

20 19

PC0/T X D

PC1/R X D

PC2/SCK

PC3/INT2

PC6/CO0

PC7/CO1

PC4/TO

PC5/CI

NM1

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PD78C10A,78C11A,78C12A

For PD78C10AL, PD78C11AL-, PD78C12AL-

STOP

PD7

PD6

PD5

PD4

PD3

PD2

PA6

PA5

PA4

PA3

PA2

PA1

PA0

V DD

IC

9 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0/T X D PC1/R X D PC2/SCK PC3/INT2 IC PC4/TO PC5/CI PC6/CO0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45

IC

PD1 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD AV DD IC V AREF AN7

44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

NMI

MODE1

RESET

MODE0

X2

PC7/C01

INT1

X1

V SS

AV SS

AN0

AN1

AN2

AN3

AN4

AN5

AN6

BLOCK DIAGRAM

OSC X2

PORT F

X1

16 LATCH INC/DEC PC SP EA V B D H 8 EA' V' B' D' H' BUFFER A' C' E' L' ALT G.R A C E L MAIN G.R 8 PROGRAM*1 MEMORY

8 12/ 13

PF7-0/ AB15-8

16 8

PORT D

PC0/TXD PC1/RXD PC2/SCK

SERIAL I/O

PD7-0/ AD7-0

NMI INT1 INT. CONTROL 4

PORT C

DATA MEMORY (256-BYTE)

PC7-0*2

PC3/INT2/TI TIMER PC4/TO 8 8 PC5/CI PC6/CO0 PC7/CO1 TIMER/ EVENT COUNTER

8/16

8 INTERNAL DATA BUS

8 PORT B

PB7-0*2

16 8 LATCH

16 LATCH

6 PSW 8 INST.REG

AN7-0 VAREF AVDD AVSS

8 A/D CONVERTER 8

16

16 8 ALU (8/16) INST. DECODER

PORT A

PA7-0*2

PD78C10A,78C11A,78C12A

16

READ/WRITE CONTROL

SYSTEM CONTROL

STAND BY CONTROL

1. It depends on a product type. The PD78C11A has 4K bytes, and the PD78C12A has 8K bytes. The PD78C10A does not incorporate a program memory. 2. An on-chip pull-up resistor is available by mask option (PD78C11A, 78C12A only).
RD WR ALE MODE1 MODE0 RESET STOP VDD VSS

PD78C10A,78C11A,78C12A

CONTENTS 1. PIN FUNCTIONS .....................................................................................................................................

1.1 1.2 1.3 1.4 LIST OF PIN FUNCTION ................................................................................................................................ PIN INPUT/OUTPUT CIRCUITS .................................................................................................................... PIN MASK OPTIONS ...................................................................................................................................... RECOMMENDED CONNECTION OF UNUSED PINS ..................................................................................

7
7 9 14 14

2. 3. 4.

DIFFERENCES BETWEEN PD78C10A AND PD78C11A, 78C12A ................................................... 15 RESET OPERATIONS ............................................................................................................................. 17 INSTRUCTION SET ................................................................................................................................. 20
4.1 4.2 4.3 IDENTIFIER/DESCRIPTION OF OPERAND ................................................................................................... SYMBOL DESCRIPTION OF OPERATION CODE ......................................................................................... INSTRUCTION EXECUTION TIME ................................................................................................................ 20 21 22

5. 6. 7. 8. 9.

LIST OF MODE REGISTERS .................................................................................................................. 34 ELECTRICAL SPECIFICATIONS ............................................................................................................. 35 CHARACTERISTIC CURVES (REFERENCE VALUES) ......................................................................... 47 DIFFERENCES IN 87AD SERIES PRODUCTS ...................................................................................... 50 PACKAGE INFORMATION ..................................................................................................................... 54

10. RECOMMENDED SOLDERING CONDITIONS...................................................................................... 60 APPENDIX DEVELOPMENT TOOLS ............................................................................................................ 62

PD78C10A,78C11A,78C12A

1. PIN FUNCTIONS
1.1 LIST OF PIN FUNCTION (1/2)

Pin Name PA7 to PA0 (Port A) PB7 to PB0 (Port B) PC0/TXD PC1/RxD

I/O Input/Output Input/Output Input-output/ Output Input-output/ Input Input-output/ Input-output

Function 8-bit input-output port, which can specify input/output bit-wise. 8-bit input-output port, which can specify input/output bit-wise. Transmit Data Output pin for serial data. Receive Data Input pin for serial data. Serial Clock Input-output pin for serial clock. It becomes output clock for the internal clock use, and input for the external. Interrupt Request/Timer Input Maskable interrut input pin of the edge trigger (falling edge), or an external clock input pin for a timer. Also, it can be used as a zero-cross detection pin for AC input. Timer Output Square wave defining one cycle of internal clock or timer counter time as half cycle is output. Counter Input External pulse input pin to timer/event counter. Counter Output 0, 1 Programmable rectangle wave output by timer/event counter. Port D 8-bit input-output port, which can specify input-output in byte units ( PD78C11A). Port F 8-bit input-output port, which can specify input-output bit-wise. Address/Data Bus When external memory is used, it becomes multiplexed address/data bus. Address Bus When external memory is used, it becomes address bus.

PC2/SCK

PC3/INT2/TI

Input-output/ Input/Input

Port C 8-bit input-output port, which can specify input/ output bit-wise.

PC4/TO

Input-output/ Output

PC5/CI

Input-output/ Input Input-output/ Output Input-output/ Input-output Input-output/ Output

PC6/CO0 PC7/CO1

PD7 to PD0/ AD7 to AD0 PF7 to PF0/ AB15 to AB8

WR (Write Strobe)

Output

Strobe signal which is output for write operation of external memory. It becomes high in any cycle other than the data write machine cycle of external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes output high-impedance. Strobe signal which is output for read operation of external memory. It becomes high in any cycle other than the read machine cycle of external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes output high-impedance. Strobe signal to latch externally the lower address information which is output to PD7 to PD0 pins to access external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes output high-impedance.

RD (Read Strobe) ALE (Address Latch Enable)

Output

Output

PD78C10A,78C11A,78C12A

1.1

LIST OF PIN FUNCTION (2/2)

Pin Name

I/O

Function

PD78C11A and 78C12A sets MODE0 pin to 0 (low level), and MODE1 pin to 1 (high level*) PD78C10A allows you to set MODE0, MODE1 pins to select 4K, 16K, or 64K bytes for the size of the memory which is installed externally.
MODE0 MODE1 (Mode) Input-output MODE0 0 1 1 MODE1 0 0 1 External Memory 4K bytes 16K bytes 64K bytes

Also, when each of MODE0 and MODE1 pins is set to 1*, it is synchronized to ALE to output a control signal. NMI (Non-Maskable Interrupt) INT1 (Interrupt Request) AN7 to AN0 (Analog Input) VAREF (Reference Voltage) AVDD (Analog VDD) AVSS (Analog VSS) X1, X2 (Crystal) RESET (Reset) STOP (Stop) VDD VSS Input

Input

Non-maskable interrupt input pin of the edge trigger (falling edge)

Input

A maskable interrupt input pin of the edge trigger (rising edge). Also, it can be used as a zero-cross detection pin for AC input. 8 pins of analog input to A/D converter. AN7 to AN4 can be used as edge detection (falling edge) input. A common pin serving both as a standard voltage input pin for A/D converter and as a control pin for A/D converter operation.

Input

Input

Power supply pin for A/D converter.

GND pin for A/D converter. Crystal connection pins for system clock oscillation. X1 should be input when a clock is supplied from outside. Input the clock of the reverse phase of X1 to X2. Low-level active system reset input. Control signal input pin in hardware STOP mode. The oscillation stops when a clock is supplied from outside. Positive power supply pin. GND pin.

* Pull-up. Pull-up resister R is 4 [k] R 0.4 tCYC [k] (tCYC is ns unit). Remarks The PD78C11A and PD78C12A are pull-up resistor incorporation specifiable by mask option at ports A, B and C.

PD78C10A,78C11A,78C12A

1.2 PIN INPUT/OUTPUT CIRCUITS Tables 1-1 and 1-2, and figures (1) to (15) show input- output circuits of each pin in a partially simplified form. Table 1-1 Pin Type No. (PD78C10A)
Pin Name PA7 to PA0 PB7 to PB0 PC1 to PC0 PC2/SCK PC3/INT2 PC7 to PC4 PD7 to PD0 PF7 to PF0 NMI INT1 Pin Name RESET RD WR ALE STOP MODE0 MODE1 AN3 to AN0 AN7 to AN4 VAREF Type No. 2 4 4 4 2 11 11 7 12 13

Type No. 5 5 5 8 10 5 5 5 5 2

Table 1-2 Pin Type No. (PD78C11A and 78C12A)

Pin Name PA7 to PA0 PB7 to PB0 PC1 to PC0 PC2/SCK PC3/INT2 PC7 to PC4 PD7 to PD0 PF7 to PF0 NMI INT1 Type No. 5-A 5-A 5-A 8-A 10-A 5-A 5 5 2 9 Pin Name RESET RD WR ALE STOP MODE0 MODE1 AN3 to AN0 AN7 to AN4 VAREF Type No. 2 4 4 4 2 11 11 7 12 13

PD78C10A,78C11A,78C12A

(1) Type 1

V DD

P- ch

IN N- ch

(2) Type 2

IN

(3) Type 4
V DD

output data P-ch

OUT

output disable

N-ch

(4) Type 4-A

V DD

output data P-ch

OUT

output disable

N-ch

10

PD78C10A,78C11A,78C12A

(5) Type 5

output data Type4 output disable IN/OUT

Type1

(6) Type 5-A

output data Type4-A output disable IN/OUT

Type1

(7) Type 7

AV DD P-ch IN N-ch AV DD Sampling C AV SS AVSS Reference Voltage (From Voltage Tap of Series Resistance String) +

(8) Type 8

output data output disable Type5 IN/OUT

Type2

MCC

11

PD78C10A,78C11A,78C12A

(9) Type 8-A

output data output disable Type5-A IN/OUT

Type2

MCC

(10) Type 9
self bias enable

IN

Type1

data

(11) Type 10

output data output disable Type5 IN/OUT

self bias enable

Type9

MCC

12

PD78C10A,78C11A,78C12A

(12) Type 10-A

output data output disable Type5-A IN/OUT

self bias enable

Type9

MCC

(13) Type 11
IN/OUT

output data

N-ch

Type1

(14) Type 12

IN

Type7

Type2

Edge Detector

(15) Type 13

IN

Type1

STOP Mode

AV SS

13

PD78C10A,78C11A,78C12A

1.3 PIN MASK OPTIONS PD78C11A and 78C12A has the following mask options, which can be selected bit-wise according to the application.

Pin Name PA7 to PA0 PB7 to PB0 PC7 to PC0

Mask Options Pull-up resistor incorporated Pull-up resistor not incorporated

Cautions

1. Zero-cross function can not be operated normally if pull-up resistor is incorporated in PC3. 2. PD78C10A has no mask option.

1.4

RECOMMENDED CONNECTION OF UNUSED PINS

Pin PA7 to PA0 PB7 to PB0 PC7 to PC0 PD7 to PD0 PF7 to PF0 RD WR ALE STOP INT1, NMI AVDD AVAREF AVSS AN7 to AN0

Recommended Connection

Connect to VSS or VDD via resistor

Leave open

Connect to VDD Connect to VSS or VDD Connect to VDD Connect to VSS Connect to AVSS or AVDD

14

PD78C10A,78C11A,78C12A

2. DIFFERENCES BETWEEN PD78C10A AND PD78C11A, 78C12A

The difference between the PD78C10A and PD78C11A, 78C12A is whether or not there is an on-chip mask programmable ROM. The memory map differs accordingly as described below. (1) PD78C10A Since the PD78C10A does not have an on-chip ROM, all memory, except the on-chip RAM area (addresses FF00H to FFFFH) can be installed outside. The size of this external memory can be selected from among 4K bytes (0000H to 0FFFH), 16K bytes (0000H to 3FFFH), and 64K bytes (0000H to FEFFH) by MODE0 and MODE1 pin setting as shown in the following table and Fig. 2-1.

Control Pin Operation Mode MODE1 4K bytes access 16K bytes access 64K bytes access 0 0 1 MODE0 0 1 1 External Memory 4K bytes (address 0000H to 0FFFH) 16K bytes (address 0000H to 3FFFH) 64K bytes (address 0000H to FEFFH) On-Chip RAM Address FF00H to FFFFH Address FF00H to FFFFH Address FF00H to FFFFH

External memory is accessed by using PD7 to PD0 (multiplexed address/data bus), PF7 to PF0 (address bus), and the RD, WR, and ALE signals. When 4K-byte or 16K-byte external memory is accessed PF7 to PF0 not used as address lines can be used as general purpose input/output ports. The size of external memory can be specified by MODE0 and MODE1 pin setting. Preset each bit of MEMORY MAPPING reisters MM2, MM1, and MM0 to "0". (2) PD78C11A and 78C12A The PD78C11A has an on-chip mask programmable ROM at addresses 0000H to 0FFFH and RAM at addresses FF00H to FFFFH. Externally, memory can be extended up to 60K bytes (addresses 1000H to FEFFH) in steps. The PD78C12A has an on-chip mask programmable ROM at address 0000H to 1FFFH and RAM at address FF00H to FFFFH. Externally, memory can be extended up to 56K bytes (address 2000H to FEFFH) in steps. The size of the external extension memory can be selected from among no external memory, 256 bytes, 4K bytes, 16K bytes, and 56K/60K bytes* by MEMORY MAPPING register setting. External memory can be accessed by using PD7 to PD0 (multiplexed address/data bus), PF7 to PF0 (address bus), and the RD, WR, and ALE signals. Programs and data can be stored in external memory. PF7 to PF0 become address lines corresponding to the size of external memory. The remaining pins can be used as general purpose input/output ports.

PF7 Port Port Port AB15

PF6 Port Port Port AB14

PF5 Port Port AB13 AB13

PF4 Port Port AB12 AB12

PF3 Port AB11 AB11 AB11

PF2 Port AB10 AB10 AB10

PF1 Port AB9 AB9 AB9

PF0 Port AB8 AB8 AB8

External Memory Maximam 256 bytes Maximum 4K bytes Maximum 16K bytes Maximum 56K/60K bytes*

PD78C11A: 60K bytes, PD78C12A: 56K bytes

15

      N M E D ; : 3 2 1 L K J C B A P O G F = 5 4 , +  "
Fig. 2-1 PD78C10A Memory Map
4K Bytes Access 16K Bytes Access 64K Bytes Access 0000H External Memory 0FFFH External Memory External Memory Not Used 3FFFH Not Used FF00H FFFFH On-Chip RAM On-Chip RAM On-Chip RAM MODE0 = 0 MODE1 = 0 MODE0 = 1 MODE1 = 0 MODE0 = 1 MODE1 = 1

PD78C10A,78C11A,78C12A

16

PD78C10A,78C11A,78C12A

3. RESET OPERATIONS
When RESET Input becomes low, the system reset is activated to create the following status. INTERRUPT ENABLE F/F is reset and interrupt is disabled. All the interrupt mask registers are set (1) and interrupt is masked. An interrupt request flag is reset (0) and hold interrupt is eliminated. Each bit of PSW is reset (0). 0000H is loaded into the program counter (PC). The MODE A, MODE B, MODE C, and MODE F registers are set to FFH and the bits (MM0, 1, and 2) of the MODE CONTROL C and MEMORY MAPPING registers are respectively reset (0), then all the ports (A, B, C, D, and F) become input port (output high-impedance). All the test flags but SB flag are reset (0). A timer mode register is set to FFH, and TIMER F/F is reset. The mode register (ETMM, EOM) of a timer/event counter is reset (0). The serial mode high register(SMH) of serial interface is reset (0), while the serial mode low register (SML) is set to 48H. The A/D channel mode register of the A/D converter is reset (0). WR, RD, ALE signals become high-impedance. The ZC1, ZC2 bits of the zero-cross mode register (ZCM) are set (1). The internal timing generator is initialized. Data memory and the following register contents are undefined: Stack pointer (SP) Expansion accumulator (EA, EA), accumulator (A, A) General register (B, C, D, E, H, L, B, C, D, E, H, L) Output latch of each port TIMER REG0, 1 (TM0, TM1) TIMER/EVENT COUNTER REG0, 1 (ETM0, ETM1) RAE bit of MEMORY MAPPING register SB flag of test flag When RESET input becomes high, the reset status is released. Then, execution of the program is started from 0000H. The contents of various kinds of registers must be initialized or re-initialized in the program, if necessary. Table 3-1 shows the state of each hardware after reset. Table 3-2 shows the state of each pin after reset.

17

PD78C10A,78C11A,78C12A

Table 3-1 State of Each Hardware after Reset

Hardware Power-on reset Reset input during normal operation Writing by CPU Write address data Address data other than the aboove Previous contents held. State after Reset Previous contents held. Undefined

Internal data memory

Operation other than writing by CPU

Reset input in standby mode Expansion accumulator (EA, EA') Accumulator (A, A') Undefined General register (B, C, D, E, H, L, B', C', D', E', H', L') Working register vector register (V, V') Program counter (PC) Stack pointer (SP) Mode register (MA, MB, MC, MF) Port MCC register MM register (bits MM0 to MM2) Output latch of each port INTERRUPT ENABLE F/F Interrupt Request flag Mask register Test flag (except SB flag) Power-on reset Standby flag (SB) Standby mode Reset input during normal operation Timer mode register (TMM) Timer Timer F/F Timer register (TM0, TM1) Timer/event counter mode register (ETMM) 00H Timer/event counter output mode register (EOM) Timer/event counter Timer/event counter register (ETM0, ETM1) Timer/event counter capture register (ECPT) Timer/event counter (ECNT) Serial mode high register (SMH) Serial interface Serial mode low register (SML) A/D channel mode register (ANM) MM register (MM3; RAE bit) Zero cross mode register (ZC1, ZC2 bits) 48H 00H Undefined 1 00H Undefined 0000H Undefined FFH 00H 0 Undefined 0 0 FFH 0 1 Previous contents held. Contents immediately before RESET input held FFH 0 Undefined

18

PD78C10A,78C11A,78C12A

Table 3-2 State of Each Pin after Reset

Pin WR RD High-impedance ALE All ports (PA, PB, PC, PD, PF) State after Reset

19

PD78C10A,78C11A,78C12A

4. INSTRUCTION SET
4.1 IDENTIFIER/DESCRIPTION OF OPERAND
Identifier r r1 r2 sr sr1 sr2 sr3 sr4 rp rp1 rp2 rp3 rpa rpa1 rpa2 rpa3 wa word byte bit f irf V, A, B, C, D, E, H, L EAH, EAL, B, C, D, E, H, L A, B, C PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, SML, EOM, ETMM, TMM, MM, MCC, MA, MB, MC, MF, TXB, TM0, TM1, ZCM PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB, CR0, CR1, CR2, CR3 PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM ETM0, ETM1 ECNT, ECPT SP, B, D, H V, B, D, H, EA SP, B, D, H, EA B, D, H B, D, H, D+, H+, D, H B, D, H B, D, H, D+, H+, D, H, D+byte, H+A, H+B, H+EA, H+byte D, H, D++, H++, D+byte, H+A, H+B, H+EA, H+byte 8 bit immediate data 16 bit immediate data 8 bit immediate data 3 bit immediate data CY, HC, Z NMI*, FT0, FT1, F1, F2, FE0, FE1, FEIN, FAD, FSR, FST, ER, OV, AN4, AN5, AN6, AN7, SB Description

NMI can also be described as FNMI.

Remarks 1. sr to sr4 (special register)

PA PB PC PD PF MA MB MC MCC MF MM TM0 TM1 TMM : PORT A : PORT B : PORT C : PORT D : PORT F : MODE A : MODE B : MODE C : MODE CONTROL C : MODE F : MEMORY MAPPING : TIMER REG0 : TIMER REG1 : TIMER MODE COUNTER REG0 ETM1 : TIMER/EVENT COUNTER REG1 ECNT : TIMER/EVENT COUNTER UPCOUNTER ECPT : TIMER/EVENT COUNTER CAPTURE ANM CR0 to CR3 TXB RXB SMH SML MKH MKL ZCM : TX BUFFER : RX BUFFER : SERIAL MODE High : SERIAL MODE Low : MASK High : MASK Low : ZERO CROSS MODE EOM ETMM : TIMER/EVENT COUNTER MODE : TIMER/EVENT COUNTER OUTPUT MODE : A/D CHANNEL MODE : A/D CONVERSION RESULT 0 to 3

2. rp to rp3 (register pair)

SP B D H V EA : STACK POINTER : BC : DE : HL : VA : EXTENDED ACCUMULATOR

4. f (flag)
CY HC Z : CARRY : HALF CARRY : ZERO

5. irf (interrupt flag)

NMI FT0 FT1 F1 F2 FE0 FE1 FEIN FAD FSR FST ER OV AN4 to AN7 SB : STANDBY : NMI INPUT : INTFT0 : INTFT1 : INTF1 : INTF2 : INTFE0 : INTFE1 : INTFEIN : INTFAD : INTFSR : INTFST : ERROR : OVERFLOW : ANALOG INPUT 4 to 7

3. rpa to rpa3 (rp addressing)

B D H D+ H+ D H D++ H++ D + byte H+A H+B H + EA H + byte : : : : : : : : : : : : : : (BC) (DE) (HL) (DE)+ (HL)+ (DE) (HL) (DE)++ (HL)++ (DE + byte) (HL + A) (HL + B) (HL + EA) (HL + byte)

ETM0 : TIMER/EVENT

20

PD78C10A,78C11A,78C12A

4.2
r

SYMBOL DESCRIPTION OF OPERATION CODE

r1 R2 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 reg V A B C D E H L T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 reg EAH EAL B C D E H L rpa A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 addressing (BC) (DE) (HL) rpa (DE)+ (HL)+ (DE)(HL)(DE + byte) (HL + A) (HL + B) (HL + EA) (HL + byte)

r2 r

rpa1

rpa2

sr S5 S4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 S3 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 S2 S1 S0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Special-reg PA PB PC PD PF MKH MKL ANM SMH SML EOM ETMM TMM MM MCC MA MB MC MF TXB RXB TM0 TM1 CR0 CR1 CR2 CR3 ZCM

sr1

sr2

rpa3 C3 C2 C1 C0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 1 0 1 1 0 1 0 1 addressing (DE) (HL) (DE)++ (HL)++ (DE + byte) (HL + A) (HL + B) (HL + EA) (HL + byte)

sr

irf I4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 rp1 I3 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 I2 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 I1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 f Q1 0 0 1 1 0 Q0 0 1 0 1 0 reg-pair VA BC DE HL EA F2 0 0 0 1 F1 0 1 1 0 F0 0 0 1 0 flag CY HC Z I0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 INTF NMI FT0 FT1 F1 F2 FE0 FE1 FEIN FAD FSR FST ER OV AN4 AN5 AN6 AN7 SB

sr3 U0 0 1 special-reg ETM0 ETM1

sr4 V0 0 1 special-reg ECNT ECPT

rp P2 0 0 0 0 1 P1 0 0 1 1 0 P0 0 1 0 1 0 reg-pair SP BC DE HL EA rp

Q2 0 0 0 0 1

rp2

rp3

21

PD78C10A,78C11A,78C12A

4.3 INSTRUCTION EXECUTION TIME 1 state shown here is composed of 3 clock cycles. When a clock cycle of 15 MHz is used, the execution time should be 200 ns (= 3 1/15 s). In this case, the 4-state instruction which is the minimum execution time should be execution time of 0.8 s.

22

Note 1

Mnemonic

Operand B1 r1, A A, r1 0 0 0 1 1 T2 T1 T0 0 0 0 0 1 T2 T1 T0 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 1 R2 R1 R0 0 1 1 0 0 1 0 0 0 1 1 1 0 0 0 1 0 1 0 0 1 0 A1 A0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 A3 0 1 1 1 A2 A1 A0 A3 0 1 0 1 A2 A1 A0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 1 rp3, EA 1 0 1 1 0 1 P1 P0 1 0 1 0 0 1 P1 P0

Operation Code B2 B3 B4

State 4 4 r1 A A r1 sr A A sr1 r (word) (word) r r byte sr2 byte

Operation

Skip Condition

* MOV *

sr, A A, sr1 r, word word, r

1 1 S5 S4 S3 S2 S1 S0 1 1 S5 S4 S3 S2 S1 S0 0 1 1 0 1 R2 R1 R0 0 1 1 1 1 R2 R1 R0 Data S3 0 0 0 0 S2 S1 S0 Offset Data Offset Offset Data*1 Data*1 Data Data Low Adrs Low Adrs High Adrs High Adrs

10 10 17 17 7 14 13 10 10 10 7/13*3 7/13*3 4 4 4 13 (C + 1) 4 4

8-bit data transfer instructions

* MVI

r, byte sr2, byte

MVIW MVIX STAW LDAW STAX LDAX EXX EXA EXH BLOCK

* * * * * *

wa, byte rpa1, byte wa wa rpa2 rpa2

(V. wa) byte (rpa1) byte (V. wa) A A (V. wa) (rpa2) A A (rpa2)

PD78C10A,78C11A,78C12A

B B', C C', D D' E E', H H', L L' V, A V', A', EA EA' H, L H', L' (DE) + (HL) +, C C 1 End if borrow rp3L EAL, rp3H EAH EAL rp3L, EAH rp3H

Note 2

DMOV EA, rp3

Note 23

1. Instruction Group 2. 16-bit data transfer instructions

Note 1

16-bit data transfer instructions

Note 2

24

Mnemonic

Operand B1 sr3, EA 0 1 0 0 1 0 0 0

Operation Code B2 1 1 0 1 0 0 1 U0 1 1 0 0 0 0 0 V0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 C3 C2 C1 C0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 0 Q2 Q1 Q0 1 0 1 0 0 Q2 Q1 Q0 0 P2 P1 P0 0 1 0 0 0 1 0 0 1 0 0 0 Low Byte 1 0 1 0 1 0 0 0 1 1 0 0 0 R2 R1 R0 0 1 0 0 1 1 0 1 0 1 0 1 High Byte 1 0 0 0 C3 C2 C1 C0 Data*2 Data*2 Low Adrs High Adrs Low Adrs High Adrs B3 B4

State 14 14 20 20 20 20 *3 14/20 20 20 20 20 *3 14/20 13 10 10 17 8 8 8 8 sr3 EA EA sr4

Operation

Skip Condition

DMOV EA, sr4 SBCD SDED SHLD SSPD STEAX LBCD LDED LHLD LSPD LDEAX PUSH POP LXI TABLE A, r ADD r, A A, r ADC r, A * word word word word rpa3 word word word word rpa3 rp1 rp1 rp2, word

(word) C, (word + 1) B (word) E, (word + 1) D (word) L, (word + 1) H (word) SPL, (word + 1) SPH (rpa3) EAL, (rpa3 + 1) EAH C (word), B (word + 1) E (word), D (word + 1) L (word), H (word + 1) SPL (word), SPH (word + 1) EAL (rpa3), EAH (rpa3 + 1) (SP 1) rp1H, (SP 2) rp1L SP SP 2 rp1L (SP), rp1H (SP + 1) SP SP + 2 rp2 word C (PC + 3 + A) B (PC + 3 + A + 1) AA+r rr+A A A + r + CY r r + A + CY

PD78C10A,78C11A,78C12A

0 1 1 0 0 0 0 0

Note

1. Instruction Group 2. 8-bit operation instructions (register)

Note

Mnemonic

Operand B1 A, r 0 1 1 0 0 0 0 0

Operation Code B2 1 0 1 0 0 R2 R1 R0 0 0 1 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 0 1 1 1 0 0 0 1 R2 R1 R0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 R2 R1 R0 0 0 0 1 1 0 1 0 1 R2 R1 R0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 1 0 0 1 1 0 B3 B4

State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 AA+r rr+A A A r rrA

Operation

Skip Condition No Carry No Carry

ADDNC r, A A, r SUB r, A A, r SBB r, A 8-bit operation instructions (register) A, r SUBNB r, A A, r ANA r, A A, r ORA r, A A, r XRA r, A A, r GTA r, A A, r LTA r, A A, r NEA r, A

A A r CY r r A CY AAr rrA AAr rrA AAr rrA AAr rrA No Borrow No Borrow

PD78C10A,78C11A,78C12A

Ar1 rA1 Ar rA Ar rA

No Borrow No Borrow Borrow Borrow No Zero No Zero

Note 25

Instruction Group

8-bit operation instructions (register) Note

8-bit operation instructions (memory)

26

Mnemonic

Operand B1 A, r 0 1 1 0 0 0 0 0

Operation Code B2 1 1 1 1 1 R2 R1 R0 0 1 1 1 1 1 0 0 1 1 0 1 0 1 1 1 0 0 0 0 1 1 0 0 0 A2 A1 A0 1 1 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 0 0 0 1 A2 A1 A0 1 0 0 1 1 0 0 1 0 A2 A1 A0 1 0 1 0 1 A2 A1 A0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 0 1 B3 B4

State 8 8 8 8 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 Ar rA Ar Ar

Operation

Skip Condition Zero Zero No Zero Zero

EQA r, A ONA OFFA ADDX ADCX ADDNCX SUBX SBBX SUBNBX ANAX ORAX XRAX GTAX LTAX NEAX EQAX ONAX OFFAX A, r A, r rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa

A A + (rpa) A A + (rpa) + CY A A + (rpa) A A (rpa) A A (rpa) CY A A (rpa) A A (rpa) A A (rpa) A A (rpa) A (rpa) 1 A (rpa) A (rpa) A (rpa) A (rpa) A (rpa) No Borrow Borrow No Zero Zero No Zero Zero No Borrow No Carry

PD78C10A,78C11A,78C12A

Note

Instruction Group

Note

Mnemonic * ADI

Operand B1 A, byte r, byte sr2, byte 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 0 0

Operation Code B2 Data 0 1 0 0 0 R2 R1 R0 S3 1 0 0 0 S2 S1 S0 Data 0 1 0 1 0 R2 R1 R0 S3 1 0 1 0 S2 S1 S0 Data 0 0 1 0 0 R2 R1 R0 S3 0 1 0 0 S2 S1 S0 Data 0 1 1 0 0 R2 R1 R0 S3 1 1 0 0 S2 S1 S0 Data 0 1 1 1 0 R2 R1 R0 S3 1 1 1 0 S2 S1 S0 Data 0 0 1 1 0 R2 R1 R0 S3 0 1 1 0 S2 S1 S0 Data 0 0 0 0 1 R2 R1 R0 Data Data Data Data Data Data Data B3 B4

State 7 11 20 7 11 20 7 11 20 7 11 20 7 11 20 7 11 20 7 11

Operation A A + byte r r + byte sr2 sr2 + byte A A + byte + CY r r + byte + CY sr2 sr2 + byte + CY A A + byte r r + byte sr2 sr2 + byte A A byte r r byte sr2 sr2 byte A A byte CY r r byte CY

Skip Condition

* ACI

A, byte r, byte sr2, byte

Immediate data operation instructions

* ADINC

A, byte r, byte sr2, byte

No Carry No Carry No Carry

* SUI

A, byte r, byte sr2, byte

* SBI

A, byte r, byte sr2, byte

PD78C10A,78C11A,78C12A

sr2 sr2 byte CY A A byte r r byte sr2 sr2 byte A A byte r r byte No Borrow No Borrow No Borrow

* SUINB

A, byte r, byte sr2, byte

* ANI

A, byte r, byte

Note 27

Instruction Group

Note

Immediate data operation instructions

28

Mnemonic ANI * ORI

Operand B1 sr2, byte A, byte r, byte sr2, byte 0 1 1 0 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 1 0 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0

Operation Code B2 S3 0 0 0 1 S2 S1 S0 Data 0 0 0 1 1 R2 R1 R0 S3 0 0 1 1 S2 S1 S0 Data 0 0 0 1 0 R2 R1 R0 S3 0 0 1 0 S2 S1 S0 Data 0 0 1 0 1 R2 R1 R0 S3 0 1 0 1 S2 S1 S0 Data 0 0 1 1 1 R2 R1 R0 S3 0 1 1 1 S2 S1 S0 Data 0 1 1 0 1 R2 R1 R0 S3 1 1 0 1 S2 S1 S0 Data 0 1 1 1 1 R2 R1 R0 S3 1 1 1 1 S2 S1 S0 Data Data Data Data Data Data B3 Data B4

State 20 7 11 20 7 11 20 7 11 14 7 11 14 7 11 14 7 11 14

Operation sr2 sr2 byte A A byte r r byte sr2 sr2 byte A A byte r r byte sr2 sr2 byte A byte 1 r byte 1 sr2 byte 1 A byte r byte sr2 byte A byte r byte sr2 byte A byte r byte sr2 byte

Skip Condition

* XRI

A, byte r, byte sr2, byte

* GTI

A, byte r, byte sr2, byte

No Borrow No Borrow No Borrow Borrow Borrow Borrow No Zero

* LTI

A, byte r, byte sr2, byte

* NEI

A, byte r, byte sr2, byte

PD78C10A,78C11A,78C12A

No Zero No Zero Zero Zero Zero

* EQI

A, byte r, byte sr2, byte

Note

Instruction Group

Note

Mnemonic *

Operand B1 A, byte r, byte sr2, byte 0 1 0 0 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0

Operation Code B2 Data 0 1 0 0 1 R2 R1 R0 S3 1 0 0 1 S2 S1 S0 Data 0 1 0 1 1 R2 R1 R0 S3 1 0 1 1 S2 S1 S0 1 1 0 0 0 0 0 0 1 1 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 offset Data Data B3 B4

State 7 11 14 7 11 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 A byte r byte sr2 byte A byte r byte sr2 byte

Operation

Skip Condition No Zero No Zero No Zero Zero Zero Zero

Immediate data operation instructions

ONI

* OFFI

A, byte r, byte sr2, byte

ADDW ADCW ADDNCW Working register operation instructions SUBW SBBW SUBNBW ANAW ORAW XRAW GTAW LTAW NEAW EQAW ONAW

wa wa wa wa wa wa wa wa wa wa wa wa wa wa

A A +(V. wa) A A + (V. wa) + CY A A + (V. wa) A A (V. wa) A A (V. wa) CY A A (V. wa) A A (V. wa) A A (V. wa) No Borrow No Carry

PD78C10A,78C11A,78C12A

A A (V. wa) A (V. wa) 1 A (V. wa) A (V. wa) A (V. wa) A (V. wa) No Borrow Borrow No Zero Zero No Zero

Note 29

Instruction Group

Note

Working register operation instructions

16-bit operation instructions

30

Mnemonic OFFAW ANIW ORIW GTIW LTIW NEIW EQIW ONIW OFFIW EADD DADD DADC DADDNC ESUB DSUB DSBB DSUBNB DAN DOR DXR * * * * * * * wa

Operand B1 0 1 1 1 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 0

Operation Code B2 1 1 0 1 1 0 0 0 Offset B3 Offset Data B4

State 14 19 19 13 13 13 13 13 13 A (V. wa)

Operation

Skip Condition Zero

wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte EA, r2 EA, rp3 EA, rp3 EA, rp3 EA, r2 EA, rp3 EA, rp3 EA, rp3 EA, rp3 EA, rp3 EA, rp3

(V. wa) (V. wa) byte (V. wa) (V. wa) byte (V. wa) byte 1 (V. wa) byte (V. wa) byte (V. wa) byte (V. wa) byte (V. wa) byte EA EA + r2 EA EA + rp3 EA EA + rp3 +CY EA EA + rp3 EA EA r2 No Carry No Borrow Borrow No Zero Zero No Zero Zero

0 1 0 0 0 0 R1 R0 1 1 0 0 0 1 P1 P0 1 1 0 1 1 0 1 0

11 11 11 11 11 11 11 11 11 11 11

0 0 0 0 0 1 0 0

0 1 1 0 0 0 R1 R0 1 1 1 0 0 1 P1 P0 1 1 1 1 1 0 1 1 1 0 0 0 1 1 P1 P0 1 0 0 1 1 0 0 1 0 1 P1 P0

PD78C10A,78C11A,78C12A

EA EA rp3 EA EA rp3 CY EA EA rp3 EA EA rp3 EA EA rp3 EA EA rp3 No Borrow

Note

Instruction Group

Note 1

Mnemonic DGT DLT DNE DEQ DON DOFF MUL DIV INR

Operand B1 EA, rp3 EA, rp3 EA, rp3 EA, rp3 EA, rp3 EA, rp3 r2 r2 r2 0 1 0 0 0 0 R1 R0 0 0 1 0 0 0 0 0 0 0 P1 P0 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0 0 R1 R0 0 0 1 1 0 0 0 0 0 0 P1 P0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 1 0 1 0 0

Operation Code B2 1 0 1 0 1 1 P1 P0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 0 1 0 0 1 0 1 1 R1 R0 0 0 1 1 B3 B4

State 11 11 11 11 11 11 32 59 4 EA rp3 1 EA rp3 EA rp3 EA rp3 EA rp3 EA rp3 EA A r2

Operation

Skip Condition No Borrow Borrow No Zero Zero No Zero Zero

Note 2

16-bit operation instructions

EA EA r2, r2 Remainder r2 r2 + 1 (V. wa) (V. wa) + 1 rp rp + 1 EA EA + 1 r2 r2 1 (V. wa) (V. wa) 1 rp rp 1 EA EA 1 Decimal Adjust Accumulator CY 1 CY 0 AA+1 Borrow Borrow Carry Carry

Increment/decrement instructions

INRW

wa rp

Offset

16 7 7 4

INX EA DCR DCRW * r2 wa rp DCX EA DAA 7 4 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0 1 1 1 0 1 0 8 8 8

Offset

16 7

PD78C10A,78C11A,78C12A

Note 3

STC CLC NEGA

Note 31

1. Instruction Group 2. Multiplication/division instructions 3. Other operation instructions

Note

Rotation/shift instructions

Jump instructions

Call Instructions

32

Mnemonic RLD RRD RLL RLR SLL SLR SLLC SLRC DRLL DRLR DSLL DSLR JMP JB JR JRE JEA CALL CALB CALF * * * * r2 r2 r2 r2 r2 r2 EA EA EA EA

Operand B1 0 1 0 0 1 0 0 0

Operation Code B2 0 0 1 1 1 0 0 0 1 0 0 1 0 1 R1 R0 0 0 R1 R0 0 0 1 0 0 1 R1 R0 0 0 R1 R0 0 0 0 0 0 1 R1 R0 0 0 R1 R0 1 0 1 1 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 0 1 Low Adrs High Adrs B3 B4

State 17 17 8 8 8 8 8 8 8 8 8 8 10 4 10

Operation Rotate Left Digit Rotate Right Digit r2m + 1 r2m, r20 CY, CY r27 r2m 1 r2m, r27 CY, CY r20 r2m + 1 r2m, r20 0, CY r27 r2m 1 r2m, r27 0, CY r20 r2m + 1 r2m, r20 0, CY r27 r2m 1 r2m, r27 0, CY r20 EAn + 1 EAn, EA0 CY, CY EA15 EAn 1 EAn, EA15 CY, CY EA0 EAn + 1 EAn, EA0 0, CY EA15 EAn 1 EAn, EA15 0, CY EA0 PC word PCH B, PCL C

Skip Condition

Carry Carry

word

PD78C10A,78C11A,78C12A

word word

1 1

jdisp 1 jdisp 0 0 1 0 1 0 0 0 Low Adrs 0 0 1 0 1 0 0 1 fa High Adrs

PC PC + 1 + jdisp 1 PC PC + 2 + jdisp PC EA (SP 1) (PC + 3)H, (SP 2) (PC + 3)L PC word, SP SP 2 (SP 1) (PC + 2)H, (SP 2) (PC + 2)L PCH B, PCL C, SP SP 2 (SP 1) (PC + 2)H, (SP 2) (PC + 2)L PC15 11 00001, PC10 0 fa, SP SP 2

0 1 0 0 1 1 1 0 1 0 0 1 0 0 0

10 8 16 17 13

word

0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0

word

0 1 1 1 1

Note

Instruction Group

Note 1

Mnemonic CALT SOFTI RET RETS RETI BIT *

Operand B1 word 1 0 0 ta

Operation Code B2 B3 B4

State 16 16 10 10 13

Operation (SP 1) (PC + 1)H, (SP 2) (PC + 1)L PCL (128 + 2ta), PCH (129 + 2ta), SP SP 2 (SP 1) PSW, (SP 2) (PC + 1)H, (SP 3) (PC + 1)L, PC 0060H, SP SP 3 PCL (SP), PCH (SP + 1) SP SP + 2 PCL (SP), PCH (SP + 1), SP SP +2 PC PC + n PCL (SP), PCH (SP + 1) PSW (SP + 2), SP SP + 3 Skip if (V. wa) bit = 1 Skip if f = 1 Skip if f = 0 Skip if irf = 1, then reset irf Skip if irf = 0 Reset irf, if irf = 1 No Operation Enable Interrupt Disable Interrupt Set Halt Mode

Skip Condition

Note 2

0 1 1 1 0 0 1 0 1 0 1 1 1 0 0 0 1 0 0 1 0 1 1 0 0 0 1 0 bit, wa f f irf irf 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 B2 B1 B0 0 1 0 0 1 0 0 0 Offset 0 0 0 0 1 F2 F1 F0 0 0 0 1 0 1 0 I4 I3 I2 I1 I0 0 1 1 I4 I3 I2 I1 I0

Return instructions

Unconditional skip

10 8 8 8 8 4 4 4 12 12

(V. wa)bit =1 f=1 f=0 irf = 1 irf = 0

Skip instructions CPU control instructions

SK SKN SKIT SKNIT NOP EI DI HLT STOP

PD78C10A,78C11A,78C12A

Set Stop Mode

* 1. Data is B2 if rpa2 = D + byte, H + byte. 2. Data is B3 if rpa3 = D + byte, H + byte. 3. In the State item, a figure is in the right side of slash if rpa2 and rpa3 are D + byte, H + A, H + B, H + EA, H + byte. Remarks The idle state when each instruction is skipped is different from the execution state as shown below. 1-byte instruction : 4 states 3-byte instruction (with *) : 10 states 2-byte instruction (with *) : 2-byte instruction : Note 33 1. 2. Instruction Group Call instructions 7 states 8 states 3-byte instruction 4-byte instruction : : 11 states 14 states

PD78C10A,78C11A,78C12A

5. LIST OF MODE REGISTERS

Read/ Write W W W W W W R/W W R/W W Serial mode register SMH MKL Interrupt mask register MKH ANM A/D channel mode register Zero-cross mode register R/W Specifies the operating mode of A/D converter. R/W Specifies the enable/disable of the interrupt request. R/W Specifies the operating mode of serial interface.

Name of Mode Registers MA MB MCC MC MM MF TMM ETMM EOM SML MODE A register MODE B register MODE CONTROL C register MODE C register MEMORY MAPPING register MODE F register Timer mode register Timer/event counter mode register Timer/event counter output mode register

Function Specifies bit-wise the input/output of the port A. Specifies bit-wise the input/output of the port B. Specifies bit-wise the port/control mode of the port C. Specifies bit-wise the input/output of the port C which is in port mode. Specifies the port/extension mode of port D and port F. Specifies bit-wise the input/output of the port F which is in port mode. Specifies operating mode of timer. Specifies the operating mode of timer/event counter. Control the output level of CO0 and CO1.

ZCM

Specifies the operation of zero-cross detector circuit.

34

PD78C10A,78C11A,78C12A

6. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 C)

PARAMETER

SYMBOL VDD

TEST CONDITIONS

RATING 0.5 to +7.0 AVSS to VDD +0.5 0.5 to +0.5 0.5 to VDD +0.5 0.5 to VDD +0.5

UNIT V V V V V mA mA mA mA V C C

Power supply voltage

AVDD AVSS

Input voltage Output voltage

VI VO All output pins

4.0 100 2.0 50 0.5 to AVDD +0.3 40 to +85

Output current low

IOL Total of all output pins All output pins

Output current high

IOH Total of all output pins

A/D converter reference input voltage Operating ambient temperature Storage temperature

VAREF TA

Tstg

65 to +150

Caution

Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product.

35

PD78C10A,78C11A,78C12A
(TA = 40 to +85 C, VDD = AVDD = +5.0 V 10 %, VSS = AVSS = 0 V, VDD 0.8 V AVDD VDD, 3.4 V VAREF AVDD)

OSCILLATOR CHARACTERISTICS

RESONATOR

RECOMMENDED CIRCUIT

PARAMETER

TEST CONDITIONS

MIN.

MAX.

UNIT

X1

X2

A/D converter not used Oscillator frequency (fXX)

15

MHz

Ceramic*1 or crystal resonator*2

C1

C2

A/D converter used

5.8

15

MHz

A/D converter not used

X1 X2

15

MHz

X1 input frequency (fX) A/D converter used X1 rise time, fall time (tr, tf) 5.8 15 MHz

External clock

20

ns

HCMOS Inverter

X1 input high, low level width (tH, tL)

20

250

ns

Cautions 1. Place oscillator circuit as close as possible to X1, X2 pins. 2. Ensure that no other signal lines pass through the shadow area.

1. The ceramic oscillators and external capacitance given in the following table are recommended.
RECOMMENDED CONSTANTS MAKER PRODUCT NAME C1[pF] CSA7.37MT CST7.37MTW Murata Mfg. Co., Ltd CSA12.0MT CST12.0MTW CSA15.00MX001 FCR8.0MC TDK Corp. FCR12.0OMC FCR15.0MC FCR10.0MC On-chip On-chip 30 On-chip 30 On-chip 15 C2[pF] 30 On-chip 30 On-chip 15

2. When a crystal oscillator is used, the following external capacitance is recommended. C1 = C2 = 10 pF

36

PD78C10A,78C11A,78C12A

CAPACITANCE (TA = 25 C, VDD = VSS = 0 V)

PARAMETER Input capacitance Output capacitance Input-output capacitance SYMBOL CI fC = 1 MHz CO Unmeasured pins returned to 0 V CIO 20 pF 20 pF TEST CONDITIONS MIN. TYP. MAX. 10 UNIT pF

37

PD78C10A,78C11A,78C12A
DC CHARACTERISTICS (TA = 40 to +85 C, VDD = AVDD = +5.0 V 10 %, VSS = AVSS = 0 V)
PARAMETER SYMBOL VIL1 Input voltage low VIL2 RESET, STOP, NMI, SCK, INT1, TI, AN4 to AN7 All except RESET, STOP, NMI, SCK, INT1, TI, AN4 to AN7, X1, X2 RESET, STOP, NMI, SCK, INT1, TI, AN4 to AN7, X1, X2 IOL = 2.0 mA IOH = 1.0 mA Output voltage high VOH IOH = 100 A Input current Input leakage current Output leakage current AVDD power supply current VDD power supply current Data retention voltage Data retention current II ILI INT1*1, TI(PC3)*2 ; 0 V VI VDD All except INT1, TI (PC3), 0 V VI VDD 0 V VO VDD Operating mode fXX = 15 MHz STOP mode Operating mode fXX = 15 MHz HALT mode fXX = 15 MHz Hardware/software STOP mode Hardware/software*3 IDDDR STOP mode RL Ports A, B and C VDDDR = 2.5 V VDDDR = 5 V 10% 3.5 V VDD 5.5 V, VI = 0 V 17 2.5 1 10 27 15 50 75 0.5 10 13 7 VDD 0.5 200 10 10 1.3 20 25 13 V VDD 1.0 0 0.2 VDD V TEST CONDITIONS All except RESET, STOP, NMI, SCK, INT1, TI, AN4 to AN7 MIN. 0 TYP. MAX. 0.8 UNIT V

V1IH Input voltage high VIH2 Output voltage low VOL

2.2

VDD

0.8 VDD

VDD 0.45

V V V

A A A
mA

ILO AIDD1 AIDD2 IDD1 IDD2 VDDDR

A
mA mA V

A A
k

Pull-up resistor*4

Caution *

For a detailed description of the hardware STOP mode, refer to the 87AD Series mPD78C18 User's Manual.

1. If self-bias should be generated by ZCM register. 2. If the control mode is set by MCC register, and self-bias should be generated by ZCM register. 3. If self-bias is not generated. 4. PD78C11A and 78C12A only.

38

PD78C10A,78C11A,78C12A
AC CHARACTERISTICS (TA = 40 to +85 C, VDD = AVDD = +5.0 V 10 %, VSS = AVSS = 0 V) Read/write Operation:

PARAMETER X1 input cycle time Address setup time (to ALE ) Address hold time (from ALE ) RD delay time from address Address float time from RD Data input time from address Data input time from ALE Data input time from RD RD delay time from ALE Data hold time (from RD ) ALE delay time from RD

SYMBOL tCYC tAL tLA tAR tAFR tAD tLDR CL = 100 pF

TEST CONDITIONS

MIN. 66 30

MAX. 250

UNIT ns ns ns ns

fXX = 15 MHz, CL = 100 pF

35 100 20 250 135

ns ns ns ns ns ns ns ns

fXX = 15 MHz, CL = 100 pF tRD tLR tRDH tRL CL = 100 pF fXX = 15 MHz, CL = 100 pF In Data Read fXX = 15 MHz, CL = 100 pF RD low level width tRR In OP Code Fetch fXX = 15 MHz, CL = 100 pF ALE high level width M1 setup time (to ALE ) M1 hold time (from ALE ) IO/M setup time (to ALE ) IO/M hold time (from ALE ) WR delay time from address Data output time from ALE Data output time from WR WR delay time from ALE Data setup time (to WR ) Data hold time (from WR ) ALE delay time from WR WR low level width tLL tML tLM fXX = 15 MHz tIL tLI tAW fXX = 15 MHz, CL = 100 pF tLDW tWD tLW tDW tWDH tWL tWW fXX = 15 MHz, CL = 100 pF CL = 100 pF 15 165 60 80 215 180 100 ns ns ns ns ns ns ns 30 35 100 ns ns ns fXX = 15 MHz, CL = 100 pF 415 90 30 35 ns ns ns ns 15 0 80 215 120

39

PD78C10A,78C11A,78C12A

Serial Operation :
PARAMETER SYMBOL TEST CONDITIONS *1 SCK input SCK cycle time tCYK SCK output *1 SCK input SCK low level width tKKL SCK output *1 SCK input SCK high level width tKKH SCK output RXD setup time (to SCK ) RXD hold time (from SCK ) TXD delay time from SCK tRXK tKRX tKTX *1 *1 *1 *2 160 700 80 80 210 ns ns ns ns ns *2 160 700 335 ns ns ns *2 400 1.6 335 ns MIN. 800 MAX. UNIT ns

s
ns

1. If clock rate is 1 in asynchronous mode, synchronous mode, or I/O interface mode.

2. If clock rate is 16 or 64 in asynchronous mode. Remarks The numeric values in the table are those when fXX = 15 MHz, CL = 100 pF. Zero-Cross Characteristics :
PARAMETER Zero-cross detection input Zero-cross accuracy Zero-cross detection input frequency SYMBOL VZX AZX fZX AC combination 60 Hz sine wave 0.05 TEST CONDITIONS MIN. 1 MAX. 1.8 135 1 UNIT VACP-P mV kHz

Other Operation :
PARAMETER TI high, low level width SYMBOL tTIH, tTIL tCI1H, tCI1L CI high, low level width tCI2H,tCI2L NMI high, low level width INT1 high, low level width INT2 high, low level width AN4 to AN7, low level width RESET high, low level width tNIH, tNIL tI1H, tI1L tI2H, tI2L tANH, tANL tRSH, tRSL Pulse width test mode 48 10 36 36 36 10 tCYC Event count mode TEST CONDITIONS MIN. 6 6 MAX. UNIT tCYC tCYC

s
tCYC tCYC tCYC

40

PD78C10A,78C11A,78C12A
A/D CONVERTER CHARACTERISTICS (TA = 40 to +85 C, VDD = +5.0 V 10 %, VSS = AVSS = 0 V, VDD 0.5 V AVDD VDD, 3.4 V VAREF AVDD)

PARAMETER Resolution

SYMBOL

TEST CONDITIONS

MIN. 8

TYP.

MAX.

UNIT Bits

3.4 V VAREF AVDD, 66 ns tCYC 170 ns Absolute accuracy* 4.0 V VAREF AVDD, 66 ns tCYC 170 ns TA = 10 to +70 C, 4.0 V VAREF AVDD, 66 ns tCYC 170 ns 66 ns tCYC 110 ns Conversion time tCONV 110 ns tCYC 170 ns 66 ns tCYC 110 ns Sampling time tSAMP 110 ns tCYC 170 ns AN0 to AN7 (including unused pins) 576 432 96 72 0.3 50 3.4 Operating mode STOP mode Operating mode fXX = 15 MHz STOP mode 1.5 0.7 0.5 10

0.8% 0.6% 0.4%

FSR FSR FSR tCYC tCYC tCYC tCYC

Analog input voltage Analog input impedance Reference voltage

VIAN RAN VAREF IAREF1

VAREF +0.3

V M

AVDD 3.0 1.5 1.3 20

V mA mA mA

VAREF current IAREF2 AVDD power supply current AIDD1 AIDD2

Quantization error ( 1/2 LSB) is not included.

AC Timing Test Point

VDD 1.0 V 0.45 V

2.2 V 0.8 V

Test Points

2.2 V 0.8 V

41

PD78C10A,78C11A,78C12A

tCYC-Dependent AC Characteristics Expression

PARAMETER tAL tLA tAR tAD tLDR tRD tLR tRL 2T 100 T 30 3T 100 7T 220 5T 200 4T 150 T 50 2T 50 4T 50 (In data read) tRR 7T 50 (In OP code fetch) tLL tML tLM tIL tLI tAW tLDW tLW tDW tWDH tWL tWW 2T 40 2T 100 T 30 2T 100 T 30 3T 100 T + 110 T 50 4T 100 2T 70 2T 50 4T 50 12T (SCK input)*1/6T (SCK input)*2 tCYK 24T (SCK output) 5T + 5 (SCK input)*1/2.5T + 5 (SCK input)*2 tKKL 12T 100 (SCK output) 5T + 5 (SCK input)*1/2.5T + 5 (SCK input)*2 tKKH 12T 100 (SCK output) MIN. ns MIN. ns MIN. ns MIN. MIN. MIN. MIN. MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. ns ns ns ns ns ns ns ns ns ns ns ns MIN. ns EXPRESSION MIN./MAX. MIN. MIN. MIN. MAX. MAX. MAX. MIN. MIN. UNIT ns ns ns ns ns ns ns ns

1. If clock rate is 1, in asynchronous mode, synchronous mode, or I/O interface mode.

2. If clock rate is 16 64, in asynchronous mode. Cautions 1. T = tCYC = 1/fXX 2. Other items which are not listed in this table are not dependent on oscillator frequency (fXX).

42

PD78C10A,78C11A,78C12A

Timing Waveform Read operation

tCYC X1

PF7 - 0 tAD PD7 - 0 Address (Lower) tLL ALE tAL RD tLR tAR tML MODE1 (M1)*1 MODE0 (IO/M)*2 tLM tLA tAFR tLDR

Address (Upper)

Read Data tRDH tRL

tRD tRR

tIL

tLI

1. When MODE1 pin is pulled up, M1 signal is output to MODE1 pin in the 1st OP code fetch cycle. 2. When MODE0 pin is pulled up, IO/M signal is output to MODE0 pin in sr to sr2 register read cycle.

Write operation

X1

PF7 - 0 tLDW PD7 - 0 Address (Lower) tLL ALE tAL WR tLW tAW tIL MODE0 (IO/M)*3 tLI tLA tWD

Address (Upper)

Write Data tDW tWDH

tWW

tWL

3. When MODE0 pin is pulled up, IO/M signal is output to MODE0 pin in sr to sr2 register write cycle.

43

PD78C10A,78C11A,78C12A

Serial Operation
tCYK tKKL SCK tKTX TXD tKKH

R XD tRXK tKRX

Timer Input Timing

tTIH

tTIL

TI

Timer/Event Counter Input Timing

Event Counter Mode tCI1H tCI1L

CI

Pulse Width Test Mode tCI2H tCI2L

CI

44

PD78C10A,78C11A,78C12A

Interrupt Input Timing

tNIH tNIL

NMI

tI1L

tI1H

INT1

tI2H

tI2L

INT2

Reset Input Timing

tRSH tRSL

RESET

0.8 VDD 0.2 VDD

External Clock Timing

t H

0.8 VDD X1 0.8 V tr tCYC tf t H

45

PD78C10A,78C11A,78C12A

DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = 40 to +85 C)
PARAMETER Data retention power supply voltage Data retention power supply current VDD rise/fall time STOP setup time (to VDD) STOP hold time (from VDD) SYMBOL VDDDR VDDDR = 2.5 V IDDDR VDDDR = 5 V 10% tRVD, tFVD tSSTVD 200 12T +0.5 10 50 TEST CONDITIONS MIN. 2.5 1 TYP. MAX. 5.5 15 UNIT V

A A s s s

tHVDST

12T +0.5

Data Retention Timing

90 % VDD 10 % tFVD tSSTVD STOP VDDDR tRVD tHVDST VIH2 VIL2

46

PD78C10A,78C11A,78C12A

7. CHARACTERISTIC CURVES (REFERENCE VALUES)

IDD1, IDD2 vs VDD
20 (TA = 25 C, fXX = 15 MHz)

IDD1 (TYP.)

VDD Power Supply Current IDD1, IDD2 [mA]

15

10

IDD2 (TYP.) 5

4.5

5.0 Power Supply Voltage VDD [V]

5.5

IDD1, IDD2 vs fXX

(TA = 25 C, VDD = 5 V) 30

VDD Power Supply Current IDD1, IDD2 [mA]

20 IDD1 (TYP.)

10 IDD2 (TYP.)

10

15

Oscillator Frequency fXX [MHz]

47

PD78C10A,78C11A,78C12A

IOL vs VOL
(TA = 25 C, VDD = 5 V) 2.5 TYP.

2.0

Output Current Low IOL [mA]

1.5

1.0

0.5

0.1

0.2

0.3

0.4

0.5

Output Voltage Low VOL [V]

IOH vs VOH
(TA = 25 C, VDD = 5 V) 1.5

TYP.

Output Current High IOH [mA]

1.0

0.5

0.1

0.2

0.3

0.4

0.5

Power Supply Voltage Output Voltage High VDD VOH [V]

48

PD78C10A,78C11A,78C12A

IDDDR vs VDDDR
(TA = 25 C) 10

Data Retention Power Supply Current IDDDR [ A]

TYP.

Data Retention Power Supply Voltage VDDDR [V]

49

PD78C10A,78C11A,78C12A

8. DIFFERENCES IN 87AD SERIES PRODUCTS (1/2)

Product Name Item Number of instructions

PD7810, 7811*1
158 kinds ROM less (PD7810) 4K 8 bits (PD7811)

PD7810H, 7811H

PD78C10, 78C11*1
159 kinds (STOP instruction added) ROM less (PD78C10) 4K 8 bits (PD78C11)

On-chip ROM

ROM less (PD7810H) 4K 8 bits (PD7811H) 256 8 bits 27

On-chip RAM Nnmber of special registers Operating frequency Power supply voltage Operating temperature range 10 to 12 MHz 5 V 5 % 4 to 10 MHz 5 V 10 %

28 (ZCM register added) 4 to 15 MHz 5 V 10 % 10 to +70 C 4 to 15 MHz*2 5 V 10 % 40 to +85 C Three kinds: HALT mode, software STOP mode, and hardware STOP mode. All data of on-chip RAM are held by low power supply voltage (2.5V) in software/ hardware STOP mode. 12 Stop Low level Self-bias control possible (by ZCM register specification) By analog delay Operation stop possible (VAREF pin operation) 0.4% (TA = 10 to +70 C, VAREF = 4.0V to AVDD) (TA = 40 to +85 C, VAREF = 4.0V to AVDD) 0.8% (TA = 40 to +85 C VAREF = 3.4V to AVDD)

10 to +70 C 40 to +85 C

Standby function

Thirty-two bytes of the on-chip RAM 256 bytes of data are held by low power supply voltage (3.2 V)

Number of HALT instruction state HALT mode CPU operation ALE

11 M3 T2 cycle repeated High level Self-bias control impossible

Zero crossing detector self-bias control NMI, RESET noise elimination method A/D converter operation control

By clock sampling

Operation stop impossible

A/D converter absolute accuracy (Unit: FSR)

0.4% (TA = 10 to +50 C) 0.6% (TA = 40 to +85 C)

0.4% (TA = 10 to +70 C)*3

0.6%

VAREF voltage range Analog input voltage range AICC/AIDD1 AIDD2 IAREF/IAREF1 IAREF2

AVCC to 0.5V to AVCC 0V to VAREF 6 mA Typ. 0.5 mA Typ. 2.0 mA Typ.

3.4 V to AVDD

0.5 mA Typ. 10 A Typ. 1.5 mA Typ. 0.7 mA Typ.

* 1. 2. 3.

PD7810, 7811, 78C10 and 78C11 are maintenance products.

K, E, P masks apply from 4 MHz to 12 MHz. The PD7810HG and 7811HG G masks, PD7810HCW and 7811HCW K masks apply TA = 0 to +70 C.

50

PD78C10A,78C11A,78C12A

PD78C10A, 78C11A,
78C12A

PD78CP14

PD78CP18

159 kinds (STOP instruction added) ROM less (PD78C10A) 4K 8 bits (PD78C11A) 8K 8 bits (PD78C12A)

16K 8 bits (PROM)

32K 8 bits (PROM) 1024 8 bits

256 8 bits 28 (ZCM register added) 4 to 15 MHz 5 V 10 % 40 to +85 C 6 to 15 MHz 5 V 5 % 40 to +85 C

4 to 15 MHz 5 V 10 % 40 to +85 C

Three kinds: Halt mode, software STOP mode, and hardware STOP mode. All data of on-chip RAM are held by low power supply voltage (2.5 V) in software/hardware STOP mode.

12 STOP Low level Self-bias control possible (by ZCM register specification) By analog delay

Operation stop impossible (VAREF pin operation)

0.4% (TA = 10 to +70 C, VAREF = 4.0 V to AVDD) 0.6% (TA = 40 to +85 C, VAREF = 4.0 V to AVDD) 0.8% (TA = 40 to +85 C, VAREF = 3.4 V to AVDD)

3.4V to AVDD 0.3 V to VAREF + 0.3 V 0V to VAREF 0.5mA Typ. 10 A Typ. 1.5 mA Typ. 0.7 mA Typ. 0.3 V to VAREF + 0.3 V

51

PD78C10A,78C11A,78C12A

DIFFERENCES IN 87AD SERIES PRODUCTS (2/2)

Product Name RD/WR Operation during RESET ALE PD/PF*4 On-chip pull-up register (Mask option) Device configuration Standby current NMOS 3.2 mA (10 to +70C) MAX. 3.5 mA (40 to +85C) MAX. 203.2 mA (10 to +70C) MAX. Current consumption Cycle time input SCK (Unit: ns) Low level width High level width TLDW Bus timing TWD (Unit: ns) TDW Hardware STOP mode restrictions Asyncronous mode restrictions during external SCK input. No 223.5 mA (40 to +85C) MAX. 20T 10T + 80 10T 80 T + 110 100 4T 100 Yes Yes 64-pin plastic shrink DIP 64-pin plastic QUIP straight*8 64-pin plastic QUIP 64-pin plastic QFP (14 20 mm, 2.05 mm thickness) 64-pin plastic QFP (14 20 mm, 2.70 mm thickness) 68-pin plastic QFJ Pin connection*10 VCC (64-pin), VDD (63-pin) VDD (64-pin), STOP (63-pin) *5 203.2 mA MAX. 25 mA MAX. 3.2 mA MAX.

Item

PD7810, 7811*1
High level Output

PD7810H, 7811H

PD78C10, 78C11*1

High-impedance

Zero is output at the pin specified by the address bus. Other pins are high impedance. Impossible CMOS 50 A MAX. (VDD = 5 V 10 %)

64-pin plastic shrink DIP Package 64-pin plastic QUIP straight*7 64-pin plastic QUIP

* 1. 4. 5.

PD7810, 7811, 78C10 and 78C11 are maintenance products. For PD7810, 7810H, 78C10 and 78C10A.
(Unit : ns) For the asyncronous mode with clock rate x1, syncronous mode, and I/O interface mode Cycle time input SCK Low level width High level width 12T 5T + 5 5T + 5 For the asyncronous mode with clock rate 16 and 64 6T 2.5T + 5 2.5T + 5

Remarks

T = tCYC = 1/fxx

52

PD78C10A,78C11A,78C12A

PD78C10A, 78C11A,
78C12A

PD78CP14

PD78CP18

High-impedance

Only PD78C11A, 78C12A possible (ports A, B, C) CMOS 50 A MAX. (VDD = 5 V 10 %) 25 mA MAX.

Impossible

1 mA MAX. (VDD = 5 V 5 %) 32 mA MAX.

50 A MAX. (VDD = 5 V 10 %) 35 mA MAX.

*5

T + 110 110 4T 100 Yes*6 No 64-pin plastic shrink DIP 64-pin plastic QUIP 64-pin plastic QFP (14 20 64-pin plastic shrink DIP mm, 2.70 mm thickness) 64-pin plastic QUIP straight*9 68-pin plastic QFJ 64-pin plastic QUIP 64-pin ceramic shrink DIP 64-pin plastic QFP (14 20 with window mm, 2.70 mm thickness) 64-pin ceramic QUIP with 68-pin plastic QFJ window 64-pin ceramic WQFN VDD (64-pin), STOP (63-pin) No

T + 130 140 4T 140

64-pin plastic shrink DIP 64-pin plastic QUIP 64-pin plastic QFP (14 20 mm, 2.70 mm thickness) 64-pin ceramic shrink DIP with window 64-pin ceramic WQFN

6. K mask products only 7. PD7811, 7811H only 8. PD78C11, only 9. PD78C11A, 78C12A only 10. Items in the parentheses are the pin numbers for the 64-pin plastic shrink DIP, 64-pin plastic QUIP straight and 64-pin plastic QUIP.

Caution

Since the oscillator characteristics, I/O level, and some internal operation timing are different, be careful when studying direct replacement of the mPD78C10A, 78C11A, 78C12A and PD7810, 7811, 7810H, 7811H, 78C10, 78C11.

53

PD78C10A,78C11A,78C12A

9. PACKAGE INFORMATION

64 PIN PLASTIC SHRINK DIP (750 mil)

64 33

1 A

32

K L J I

F D

NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.

ITEM A B C D F G H I J K L M N R

MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 0.05 0.17 0~15

INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 0.003 0.007 0~15 P64C-70-750A,C-1

54

PD78C10A,78C11A,78C12A

55

PD78C10A,78C11A,78C12A

56

PD78C10A,78C11A,78C12A

64PIN PLASTIC QFP (14 20) (UNIT: mm)

A B

51 52

33 32

detail of lead end

64 1

20 19

I M

J K

N L P64GF-100-3B8,3BE,3BR-1 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.40 0.10 0.20 1.0 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 0.05 0.12 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795+0.009 0.008 0.551+0.009 0.008 0.693 0.016 0.039 0.039 0.016 +0.004 0.005 0.008 0.039 (T.P.) 0.0710.009 0.031+0.009 0.008 0.006+0.004 0.003 0.005 0.106 0.004 0.004 0.119 MAX.
+0.008

55

57

PD78C10A,78C11A,78C12A

ES 64PIN CERAMIC QFP (REFERENCE DRAWING) (UNIT: mm)

Cautions

1. 2. 3.

The metal cap is connected to pin 26 and is VSS (GND) level. The bottom leads are tilted. Since cutting of the end of the leads is no process-controlled, the lead length is unspecified.

58

PD78C10A,78C11A,78C12A

68PIN PLASTIC QFJ (

950 mil) (UNIT: mm)

A B

E U

T K M N
M

C D

68 1

P68L-50A1-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K M N P Q T U MILLIMETERS 25.2 0.2 24.20 24.20 25.2 0.2 1.94 0.15 0.6 4.4 0.2 2.8 0.2 0.9 MIN. 3.4 1.27 (T.P.) 0.40 1.0 0.12 23.12 0.20 0.15 R 0.8 0.20 +0.10 0.05 INCHES 0.992 0.008 0.953 0.953 0.992 0.008 0.076+0.007 0.006 0.024 0.173+0.009 0.008 0.110+0.009 0.008 0.035 MIN. 0.134 0.050 (T.P.) 0.016+0.004 0.005 0.005 0.910+0.009 0.008 0.006 R 0.031 0.008+0.004 0.002

59

PD78C10A, 78C11A, 78C12A

10. RECOMMENDED SOLDERING CONDITIONS

The PD78C10A, 78C11A, and 78C12A should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our sales personnel.

Table 10-1 Surface Mounting Type Soldering Conditions (1) PD78C10AGF-3BE : 64-pin plastic QFP (14 20 mm)

PD78C11AGF--3BE : 64-pin plastic QFP (14 20 mm) PD78C12AGF--3BE : 64-pin plastic QFP (14 20 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature : 235 C, Duration : 30 sec. max. (210 C min.), Number of times : 2 max. <Points to note> (1) Start the second reflow after the device temperature by the first reflow returns to normal. (2) Flux washing by the water after the first reflow should be avoided. Package peak temperature : 215 C, Duration : 40 sec. max. (200 C min.), Number of times : 2 max. <Points to note> (1) Start the second reflow after the device temperature by the first reflow returns to normal. (2) Flux washing by the water after the first reflow should be avoided. Wave soldering Solder bath temperature : 260 C max., Duration : 10 sec. max., Number of times : 1 Pre-heating temperature : 120 C max. (package surface temperature) Pin temperature : 300 C max., Duration: 3 sec. max. (per device side) WS60-00-1 Recommended Condition Symbol IR35-00-2

VPS

VP15-00-2

Pin part heating

Caution

Do not use two or more soldering methods in combination (except the pin part heating method).

(2) PD78C10AL PD78C11AL-

: : :

68-pin plastic QFJ ( 68-pin plastic QFJ ( 68-pin plastic QFJ (

950 mil) 950 mil) 950 mil)

Soldering Conditions Recommended Condition Symbol IR30-00-1

PD78C12AL-
Soldering Method Infrared reflow

Package peak temperature : 230 C, Duration : 30 sec. max. (210 C min.), Number of times : 1 Package peak temperature : 215 C, Duration : 40 sec. max. (200 C min.), Number of times : 1 Pin temperature : 300 C max., Duration : 3 sec. max. (per device side)

VPS

VP15-00-1

Pin part heating

Caution

Do not use two or more soldering methods in combination (except the pin part heating method).

60

PD78C10A, 78C11A, 78C12A

Table 10-2 Inserted Type Soldering Conditions (1) PD78C10ACW PD78C11ACW- : 64-pin plastic shrink DIP (750 mil) : 64-pin plastic shrink DIP (750 mil) : 64-pin plastic shrink DIP (750 mil) : 64-pin plastic QUIP : 64-pin plastic QUIP : 64-pin plastic QUIP
Soldering Conditions Solder bath temperature: 260 C max. Duration: 10 sec. max. Pin temperature: 300 C max. Pin part heating Duration: 3 sec. max. (per pin)

PD78C12ACW- PD78C10AGQ-36 PD78C11AGQ--36 PD78C12AGQ--36

Soldering Method Wave soldering (pin only)

Caution

Ensure that the application of wave soldering is limited to the pins and no solder touches the main unit directly.

(2) PD78C11AGQ--37 PD78C12AGQ--37

Soldering Method Pin part heating

: 64-pin plastic QUIP straight : 64-pin plastic QUIP straight

Soldering Conditions Pin temperature: 300 C max. Duration: 3 sec. max. (per pin)

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PD78C10A,78C11A,78C12A

APPENDIX DEVELOPMENT TOOLS

The following development tools are available to develop a system which uses 87AD series products. Language Processor
This is a program which converts a program written in mnemonic to an object code that microcomputer execution is possible. Besides, it contains a function to automatically create a symbol/table, and optimize a branch instruction. Host Machine 87AD series relocatable assembler (RA87) PC-9800 series Ordering Code (Product Name)

OS MS-DOSTM Ver. 2.11 to Ver. 5.00A* PC DOSTM (Ver. 3.1)

Supply Medium 3.5-inch 2HD

S5A13RA87 S5A10RA87 S7B13RA87 S7B10RA87

5-inch 2HD 3.5-inch 2HC 5-inch 2HC

IBM PC/ATTM

PROM Write Tools

With an provided board and an optional programmer adapter connected, this PROM programmer can manipulate from a stand-alone or host machine to perform programming on single-chip microcomputer which incorporates PROM. It is also capable of programming a typical PROM ranging from 256K to 4M bits.

PG-1500

Hardware

PA-78CP14CW/ GF/GQ/KB/L PA-78CP14CW PA-78CP14GF PA-78CP14GQ PA-78CP14KB PA-78CP14L

PROM programmer adapter for PD78CP14/78CP18. Used by connecting to PG-1500. For PD78CP14CW, 78CP14DW, 78CP18CW, 78CP18DW For PD78CP14GF-3BE, 78CP18GF-3BE For PD78CP14G-36, 78CP14R, 78CP18GQ-36 For PD78CP14KB, 78CP18KB For PD78CP14L Connected PG-1500 to a host machine by using serial and parallel interface, to control the PG1500 on a host machine.

Host Machine Software PG-1500 controller PC-9800 series

OS MS-DOS Ver. 2.11 to Ver. 5.00A* PC DOS (Ver. 3.1)

Supply Medium

Ordering Code (Product Name)

3.5-inch 2HD

S5A13PG1500 S5A10PG1500

5-inch 2HD

IBM PC/AT

5-inch 2HC

S7B10PG1500

* Ver. 5.00/5.00A has a task swap function, but this function cannot be used with this software. Remarks Operation of assemblers and the PG-1500 controller are guaranteed only on the host machines and operating systems quoted above. 62

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Debugging tools An in-circuit emulator (IE-78C11-M) is available as a program debugging tool for 87AD series. The following table shows its system configuration.

IE-78C11-M Hardware

The IE-78C11-M is an in-circuit emulator which works with 87AD series. Only the IE-78C11-M should be used for a plastic QUIP package, while it should be used with a conversion socket for a plastic shrink DIP package. It can be connected to a host machine to perform efficient debugging. Conversion sockets for plastic shrink DIP. Used in combination with the IE-78C11-M. 64-pin LCC socket. Can be used as a substitute for 64-pin plastic QFP products with window in combination with the PD78CP14KB/78CP18KB. Connects the IE-78C11-M to host machine by using the RS-232-C, then controls the IE-78C11-M on host machine.

EV-9001-64

EV-9200G-64

Host Machine Software IE-78C11-M control program (IE controller) PC-9800 series

OS MS-DOS Ver. 2.11 to Ver. 3.30D PC DOS (Ver. 3.1)

Supply Medium

Ordering Code (Product Name)

3.5-inch 2HD

S5A13IE78C11 S5A10IE78C11

5-inch 2HD

IBM PC/AT

5-inch 2HC

S7B10IE78C11

Remarks

Operation of the IE controller is guaranteed only on the host machine and operating systems quoted above.

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[MEMO]

64

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NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

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The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

The customer must judge : PD78C11ACW-, 78C11AGF--3BE, 78C11AGQ--36, 78C11AGQ--37, the need for license PD78C11AL-, 78C12ACW-, 78C12AGF--3BE, 78C12AGQ--36,

PD78C12AGQ--37, 78C12AL-
License not needed :

PD78C10ACW, 78C10AGF-3BE, 78C10AGQ-36, 78C10AL

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: Standard, Special, and Specific. The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in Standard unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94.11

MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.