Assembly Language Coding (ALC) Part 3

IBM Mainframe Assembler Language Coding
The Load Address Instruction
The Load Address instruction places the effective address specified by the 2nd operand into the register designated by the 1st operand. Formats: LA R1,S2
The effective address represented in implicit form by S2 is placed into the register specified as the R1 field. LA R1,S2(X2)
The effective address computed by adding the index register value that is in operand X2 to the address represented in implicit form by operand S2, is placed in the register specified as R1. LA R1,D2(X2,B2)
The effective address computed by adding the displacement operand, D2, to the value of the index operand, X2, and the address in the B2 operand, is placed in the register specified as the R1 operand. Note: In the 24-bit addressing mode, the address is placed in bit positions 8-31 of the R1 register and bits 0-7 are set to zeros. In the 31-bit addressing mode, the address is placed in bit positions 1-31 and bit 0 is set to zero.
131

Load Address Example
LA
R7,DATA
(Assume DATA begins at address 5800)
Reg 7 before: FF FF FF FF
DATA before: 00 00 32 40
Reg 7 after: 00 00 58 00
DATA after: 00 00 32 40
132

If the index register or base register is zero then its value is assumed to be zero (in other words NO register is specified).
LA or LA R4,2(,R6) R4,2(R0,R6)
Reg 4 before: 1F AC 41 00
Reg 6 before: 00 00 48 00
Reg 4 after: 00 00 48 02
Reg 6 after: 00 00 48 00
133

The LA instruction can be used to initialize a register with a positive binary number up to 4095 (decimal) specified in the D2 field and with the X2 and B2 fields set to zero. LA R6,10(R0,R0) or LA R6,10
Reg 6 before: 00 43 28 E0
Reg 6 after: 00 00 00 0A
134

The LA instruction can also be used to increment a register (except register 0) with a positive binary number up to 4095 (decimal) specified in the D2 field. The register to be incremented should be designated by R1 and by X2 (with B2 set to zero) or B2 (with X2 set to zero).
LA R6,10(R6,R0) or LA R6,10(R0,R6)
Reg 6 before:
00 00 00 0A
Reg 6 after:
00 00 00 14
In the 24-bit addressing mode, the right-most 24 bits of the sum are retained. The left-most 8 bits are set to zero. In the 31-bit addressing mode, the rightmost 31 bits of the sum are retained. The left-most bit is set to zero. Two factors should be considered in using this method to increment a register. 1. If overflow occurs, it is lost. 2. If the original value in the R1 register is a negative signed binary number, the sign bit (bit 0) of the result will always indicate positive whether in 24-bit or 31-bit addressing mode.
135

LA
R7,DATA(R6)
(Assume DATA begins at address 5800)
Reg 7 before: 00 00 00 00
Reg 7 after: 00 00 58 40
Reg 6 before: 00 00 00 40
Reg 6 after: 00 00 00 40
DATA before: 00 00 32 40
DATA after: 00 00 32 40
136

TAG1 LA
EQU
12
R6,TAG1
Reg 6 before: 00 65 FA C0
Reg 6 after: 00 00 00 0C
137

Load Fullword
R7,WORD
Reg 7 before: 00 32 11 FF
WORD before: 00 00 01 40
Reg 7 after: 00 00 01 40
WORD after: 00 00 01 40
138

Branch on Count BCTR BCT R1,R2 (RR format)
R1,D2(X2,B2) (RX format)
When a Branch on Count instruction is executed, two things take place, in this order: 1. A positive 1 is algebraically subtracted from the register designated by the first operand, R1, and the result is placed into that register. 2. Then the result obtained is tested to see if it is zero. If it is not zero, a branch is made to the address designated by the second operand. However, if the result is zero, no branch is made; instead execution proceeds at the instruction that immediately follows the Branch on Count instruction. Counting is performed without branching when the R2 field in the RR format contains a zero. BCTs are most commonly used for loop control. See the example on the next page.
139

Branch on Count START EQU LA LA LTR BNP COMPARE EQU CLI BNE MVI NEXT EQU LA BCT BYPASS EQU . * R4,STRING R5,LENGTH R5,R5 BYPASS * 0(R4),C'!' NEXT 0(R4),C'.' * R4,1(R4) R5,COMPARE *
(STRING is in a workblock - not in the program.) (Presume it contains the character data as shown.) STRING LENGTH DS C'TEST! WILL IT WORK? YES!' EQU *-STRING
last updated 12/29/99
140

Length Attribute
Every symbolic tag or label has a length assigned when the program is assembled. The length is assigned by the assembler to generate the length portion of an instruction. This implicit length attribute can be referenced in the program by using L'. Example:
DATA DS FIELD DS CL8 CL4
To move FIELD to the first 4 bytes of DATA you could code: MVC MVC DATA(4),FIELD DATA(L'FIELD),FIELD without L' with L'
To load the length of a field into a register: LA R2,L'FIELD
Using L' to loop through a table: LA LA EQU

-
LOOP
R14,TABLE R15,100 * R14,L'TABLE(R14) R15,LOOP DS DS DS DS DS 141 0CL10 CL4 PL4 PL2 99CL10
LA BCT
-
TABLE CODE AMT RATE


Program Definition START The START instruction is used to initiate the first or only control section of a source module. If used it must be the first instruction of the source module. The CSECT instruction initiates an executable control section or indicates the continuation of an executable control section. In other words, it is the program object code.
CSECT
In TPF there is only one control section. During the assembly process your program is known to the Assembler as a control section named $IS$.
$IS$
START Your code END
The START and the CSECT are generated automatically for you.
142

The Program USING Statement
Establishing a program base register. 3 prerequisites in designating and loading the base register: Inform the Assembler which general register is to be the base register (USING statement). Inform the Assembler of the address to be used as the assumed or promised base address (USING statement). Code the instruction that will load the designated register with the base address at program execution time. (This is done automatically in TPF.) The USING statement associates a particular register with a particular layout of data (in this case, a CSECT). It generates no object code whatsoever. It is not executable code. However, it must be used in conjunction with code that loads a base register (e.g. LA, L, BASR, etc). Most often the layout of data is through a DSECT (covered later) or within an actual program. Example: {Symbol} USING BASE,REG
To load and assign the base register of a program: BASR USING R8,0 *,R8
This might be the sequence of instructions if you had to establish and load the program base register. In TPF all of this is accomplished for you automatically - for every program.
143

Branch and Save BASR BAS R1,R2 (RR format) R1,D2(X2,B2) (RX format)
The absolute (memory) address of the instruction that follows the "BAS" instruction is loaded (as link information) in the general register designated as R1. Then, an unconditional branch to the address designated by the second operand takes place. In the RX format, the second operand address is used as the branch address. In the RR format, the contents of the general register designated by R2 is used to generate the branch address. However, when the R2 field contains zero, the operation is performed without branching. The branch address is computed before the link information is loaded. In the 24-bit addressing mode, the link information consists of a 24-bit instruction address with eight zeros appended on the left. In the 31-bit addressing mode, the link information consists of a 31-bit address with a one appended on the left. The primary use of these instructions is for 'transportation'; to allow your program to access a subroutine and return. In non TPF systems the BAS might be used to load a program base register.
144

Branch and Link BALR BAL R1,R2 (RR format) (RX format)
R1,D2(X2,B2)
The absolute address of the instruction that follows the "BAL" instruction is loaded as link information in the general register designated as R1. Then an unconditional branch to the address designated by the second operand takes place. In the RX instruction format, the second operand address is used as the branch address. In the RR format, the contents of the general register designated by R2 are used to generate the branch address. However, when the R2 field contains a zero, the operation is performed without branching. The branch address is computed before the link information is loaded. The link information in the 24-bit addressing mode consists of the instruction-length code, the condition code, the program mask bits, the updated instruction address. In the 31-bit addressing mode, the link information consists of the address-mode bit (always a one) and a 31-bit updated instruction address. It is recommended that the Branch and Save (BAS and BASR) be used and Branch and Link be avoided. The only exception is if the program is actually using the ILC, CC or Program Mask Bits (in which case it must run in 24 bit mode).
145

The Dummy Control Section - DSECT
The DSECT instruction allows you to initiate a Dummy Control Section or to indicate its continuation. A DSECT is a reference control section that allows you to describe the layout of data in a storage area without actually reserving any storage. Thus you can write a sequence of Assembler language statements to describe the layout of data located outside of your program. No constants (DC's) are allowed within a DSECT. DS statements are typically used. The ORG statement is permitted. A new location counter, set to zero, is established for each DSECT. Therefore, all data areas described in each DSECT are relative to zero.
146

The Dummy Control Section - DSECT
To use a DSECT you must: 1. Reserve a storage area for the data. 2. Ensure that the data is loaded into the area at execution time. 3. Assign a unique symbol (name) to each DSECT. 4. Ensure that each symbolic label in the DSECT is unique in the entire program source file. 5. Ensure that the locations of the symbolic labels in the DSECT actually correspond to the locations of the data being described. 6. Ensure that each DSECT is terminated with either: A. another DSECT, or B. a CSECT statement, or C. an END statement. 7. Establish addressability to the reserved storage area. then you can 8. Refer to the data described in the DSECT symbolically.
147

Program Definition Terminology START The START instruction is used to initiate the first or only control section of a source module. If used it must be the first instruction of the source module. The CSECT instruction initiates an executable control section or indicates the continuation of an executable control section. In other words, it is the program itself. The DSECT instruction initiates a Dummy Control Section or indicates it's continuation. It is a reference control section that allows you to describe the layout of data without actually reserving any storage.
CSECT
DSECT
148

Program Definition Examples
$IS$
OUTPUT
$IS$
START DSECT CSECT END
149

The DSECT USING Statement
Establishing a DSECT base register. 3 prerequisites in designating and loading the base register: Inform the Assembler which general register is to be the base register (USING statement). Inform the Assembler which DSECT is to be associated with the general register (USING statement). Code the instruction that will load the designated register with the base address of the data at program execution time. The USING statement associates a particular register with a particular layout of data (in this case, a DSECT). It generates no object code whatsoever. It is not executable code. However, it must be used in conjunction with code that loads a base register (e.g. LA, L, etc).
Example:
{Symbol} USING DSECT NAME,REG L R4,CE1CR0 USING INPUT,R4 (You can use symbolic labels in the INPUT DSECT after this point in your program.) -
150

The DROP Statement - Dropping a Base Register The DROP instruction is necessary when you wish to use a base register for a different DSECT or whenever two USING statement ranges coincide or overlap. DROP frees the base register for other purposes. It breaks the association established by the USING. Format: Example:
USING DROP INPUT,R4
{Symbol}
DROP
REG1,{REG2, ....}
R4
(You can no longer refer to symbolic names in the INPUT DSECT.) LA R4,EBW000 USING OUTPUT,R4 (You can now start using symbolic labels in the OUTPUT DSECT.)
151

Example of a DROP Statement Consequences of not using the DROP if base registers overlap.
LOC OBJECT CODE ADDR1 ADDR2 STMT SOURCE USING LR MVC * USING LR MVC * USING LR MVC * STATEMENT
00002E 000030
00000 1841 0000C D202 4028 402B 00028 0002B 00000 1831 D202 4028 402B 00028 0002B 00000
000036 000038
00003E 000040
1851 D202 5028 502B 00028 0002B
68 69 70 71 72 73 74 75 76 77 78 79
RECORL,R4 R4,R1 LEG8,CTY8 RECORL,R3 R3,R1 LEG8,CTY8 RECORL,R5 R5,R1 LEG8,CTY8
(Note changes to the base registers in the object code.)
152

Define Storage
{Label}
DS
{D} -
{Ln}
Where: {Label} DS {D} T {Ln}
optional Identifier or name required symbol optional duplication factor data type (B, C, Z, P, H, F, D, X) length
A DS requests that a number of bytes be reserved for a field. DS statements are usually coded for the purpose of reserving working storage. No data is placed in the field, but you can put data within quotes for self-documentation purposes. STATE DS CL10'STATE'
The Assembler will assign a correct length to be associated with the label. In the example above, the length will be 10. In the following example, the length of STATE2 will be 18. STATE2 DS C'WHAT IS THE LENGTH'
No machine language instructions are generated. The location counter may be adjusted but no object code is generated. Allowable length of 32K.
153

Define Storage Example
Input Record INPUT NAME EMPNO ADDR HRS DATE MONTH DAY YEAR FILLER DS DS DS DS DS DS DS DS DS DS 0CL80 CL10 CL5 CL25 CL2 0CL6 CL2 CL2 CL2 CL32
Zero Duplication Factor The Zero Duplication Factor reserves no bytes of storage. Alignment is on the desired boundary. A length is assigned to the label. It allows you to provide a label for an area of storage and fields within that area (as above). It allows for the re-defining of storage. Some programmers, for 'branch to' labels, use: PARTY DS 0H
instead of: PARTY EQU *

154

Define Storage - Doubleword PACK PWORK,=C'5' CVB R4,PWORK . . PWORK DS D 5% TAX RATE FOR MATH
(DEFINED IN A WORK AREA)
PWORK BEFORE PACK INSTRUCTION ???????????????? PWORK AFTER PACK INSTRUCTION 000000000000005F REGISTER 4 AFTER CVB INSTRUCTION 00000005
155

The ORG Statement
The ORG statement is used to alter the setting of the location counter and thus controls the structure of the current control section. Like the zero duplication factor, the ORG statement allows for the re-defining of portions of a control section.
INPUT NAME EMPNO ADDR HRS DATE DAY MONTH YEAR
DS ORG DS DS ORG DS DS ORG DS ORG DS DS DS ORG
CL80 INPUT CL10 CL5 *+5 CL24 CL2 *+8 CL6 DATE CL2 CL2 CL2
0.........1.........2.........3.........4.........5.........6.. INPUT NAME EMPNO ADDR HRS DATE DAY MONTH YEAR
156

ORG Examples Layout of DATA1, DATA2,DATA3:
0.........1.........2.........3.........4.........5.........6 CODE DATA1 DATA2 DATA3
Layout of FIELD1, FIELD2, FIELD3:

0.........1.........2.........3.........4.........5.........6 CODE FIELD1 FIELD2 FIELD3
Contents of CODE determine whether to use DATAx or FIELDx labels.
Two different ways to write the overlay:

INAREA CODE DATA1 FIELD1 FIELD2 DATA2 FIELD3 DATA3 DS DS DS DS DS DS DS DS DS DS DS 0CL60 CL1 0CL10 CL8 0CL12 CL2 0CL15 CL10 0CL20 CL5 CL34 INAREA CODE DATA1 DATA2 DATA3 DS DS DS DS DS ORG DS DS DS DS ORG 0CL60 CL1 CL10 CL15 CL34 INAREA CL1 CL8 CL12 CL20
FIELD1 FIELD2 FIELD3
157

Example of a Null ORG
A null ORG is important in order to reset the location counter to the next available location in the control section after an ORG has been used to change it. (As when redefining a field.) Null ORG used:
LOC 000000 000000 000001 000006 000015 00001A 000029 00002E 00003D 000085 000001 00000B 000015 00001A 000024 000085 OBJECT CODE ADDR1 ADDR2 STMT 1 2 3 4 5 6 7 8 9 00001 10 11 12 13 14 00085 15 16 17 SOURCE STATEMENT OUTPUT DS 0CL133 CNTL DS CL1 DS CL5 AREA1 DS CL15 DS CL5 AREA2 DS CL15 DS CL5 AREA3 DS CL15 DS CL72 ORG OUTPUT+1 DS CL10 REACH1 DS CL10 DS CL5 REACH2 DS CL10 ORG NAME DC 'DOUG' END
C4D6E4C7
Null ORG not used:

LOC 000000 000000 000001 000006 000015 00001A 000029 00002E 00003D 000085 000001 00000B 000015 00001A 000024 OBJECT CODE ADDR1 ADDR2 STMT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SOURCE STATEMENT OUTPUT DS 0CL133 CNTL DS CL1 DS CL5 AREA1 DS CL15 DS CL5 AREA2 DS CL15 DS CL5 AREA3 DS CL15 DS CL72 ORG OUTPUT+1 DS CL10 REACH1 DS CL10 DS CL5 REACH2 DS CL10 NAME DC 'DOUG' END
00001
C4D6E4C7
158

Example of a DSECT
BEGIN $IS$ INREC LASTNAME FLTNUM FILL1 LUGCNT FILL2 BASEPRC FILL3 DISCNT FILL4 $IS$ START DSECT DS DS DS DS DS DS DS DS DS CSECT L LA USING CLI NAME=ZOO1,VERSION=XX (Remember - you do NOT code this.) INPUT RECORD STORAGE AREA LAST NAME OF PASSENGER FLIGHT NUMBER UNUSED SPACE LUGGAGE COUNT (NUMBER OF BAGS) UNUSED SPACE BASE TICKET PRICE UNUSED SPACE TICKET DISCOUNT EXPANSION AREA
CL10 CL3 CL1 CL1 CL1 CL6 CL1 CL2 CL55
R1,CE1CR0 R1,MI0ACC INREC,R1 LUGCNT,X'00'
ANY BAGS?
159

DSECT Example - Effect on Location Counter
LOC OBJECT CODE ADDR1 ADDR2 STMT SOURCE STATEMENT BEGIN NAME=... * PERHAPS A COMMENT .. RECORD DSECT ID DS CL1 INFO DS CL25 ORG INFO DS CL1 FLN DS CL4 CLASS DS CL1 DS CL1 DATE DS CL5 DS CL1 ORIG DS CL3 DEST DS CL3 ORG DS CL54 $IS$ CSECT L MVI R1,CE1CR0 EBW000,X'40'
000000 000000 000001 00001A 000001 000002 000006 000007 000008 00000D 00000E 000011 000014 00001A 000008 000008 00000C 58109100 92409008
00001
0001A
00100 00008
331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348
160

EXERCISE #6 PROGRAM 6. DSECT Re-code your latest "working" program with input of b@hh.tdd.ccname+ making the following changes Create the following DSECTS Input (to access any data from the input message) Work (for any ECB intermediate data areas) Output (for the display line area) Name the dsects INPUT, WORK and OUTPUT ALL labels in each dsect WILL begin with I W or O in the respective dsect. Your code may only use dsect labels you create to access storage data AND instructions can NOT use explicit lengths OR relative addressing.
161
162

Boolean Operations - Altering Bits There are three instructions in IBM 370 Assembly that alter bits: the Boolean operations "AND", "OR", and the "EXCLUSIVE OR". These three have the following in common: 1. They operate on two bit strings, each of the same length. Only the target bit string is altered. The other bit string, the "mask", selects the bits to be altered. Each bit in the mask that is a 1 selects the correspondingly positioned bit in the target.
2.
The Boolean operator "OR" sets the selected target bits to 1, regardless of the previous value. Bits not selected by the mask remain unchanged. The Boolean operator "AND" preserves the value of the selected bits and sets the remaining bits to zero, regardless of their previous value. The "EXCLUSIVE OR" operator reverses the value of the selected target bits. Unselected bits remain unchanged.
163

Boolean Operations - Altering Bits - Truth Table
0 "AND" Truth Table 0 1 0 0
1 0 1
0 "OR" Truth Table 0 1 0 1
1 1 1
0 "EXCLUSIVE OR" Truth Table 0 1 0 1
1 1 0
164

AND Fullword
R4,SECOP
Before FO FO FO FO
REG 4
FF EE FF FO
SECOP
After FO EO FO FO
REG 4
FF EE FF FO
SECOP
165

AND Register
NR
R4,R5
Before 0A 0B 0C 0D
REG 4
F1 F2 F3 F4
REG 5
After 00 02 00 04
REG 4
F1 F2 F3 F4
REG 5
166

AND Character
NC
SAVE,LETZ
Before F1 F2 F3 F4
SAVE
C1 C2 C3
LETZ
After C1 C2 C3 ??
SAVE
C1 C2 C3 ??
LETZ
167

AND Immediate
NI
SAVE,X'C3'
Before CC FF FF FF
SAVE
C3
Mask
After C0 FF FF FF
SAVE
C3
Mask
168

OR Register
OR
R4,R5
Before 0A 0B 0C 0D
REG 4
F1 F2 F3 F4
REG 5
After FB FB FF FD
REG 4
F1 F2 F3 F4
REG 5
169

OR Fullword
R4,LIST
Before 00 00 00 00
REG 4
C1 C2 FF 33
LIST
After C1 C2 FF 33
REG 4
C1 C2 FF 33
LIST
170

OR Immediate
OI
SAVE,X'C3'
Before CC FF FF FF
SAVE
C3
Mask
After CF FF FF FF
SAVE
C3
Mask
Example:
L CVD UNPK OI
5,Z 5,BCD SUM,BCD+6(2) SUM+2,X'F0'
4 byte field - Z 8 byte field - BCD 3 byte field - SUM
171

OR Character
OC
SAVE(2),TWOS
Before F1 F2 F3 F4
SAVE
C3 C4
TWOS
After F3 F6 F3 F4
SAVE
C3 C4
TWOS
172

Exclusive OR
R4,PLOT
Before F0 F0 F0 F0
REG 4
FF EE FF F0
PLOT
After 0F 1E 0F 00
REG 4
FF EE FF F0
PLOT
173

Exclusive OR Register
XR
R4,R5
Before 0A 0B 0C 0D
REG 4
F1 F2 F3 F4
REG 5
After FB F9 FF F9
REG 4
F1 F2 F3 F4
REG 5
174

Exclusive OR Immediate
XI
SAVE,X'C3'
Before CC FF FF FF
SAVE
C3
Mask
After 0F FF FF FF
SAVE
C3
Mask
175

Exclusive OR Character
XC
SAVE,SAVE
Before F1 F2 F3 F4
SAVE
After 00 00 00 00
SAVE
176

Test Under Mask - TM
TM
D1(B1),I2
The Test Under Mask instruction tests any subset of the 8 bits in a byte. The target byte can be located in any addressable memory location. The bits to be tested are designated within the mask. The mask is always the 2nd operand. Each 1 bit in the mask selects that corresponding (position) bit in the target to be tested. The results obtained indicate whether tested bits were "on" (equal to 1), or "off" (equal to zero).
TM
SAVE,X'33'
FF F1 F2 F3
SAVE
MASK VALUE: RESULT: CC =
0011 0011 xx11 xx11 3
177

Define Constant - Zoned Decimal Data ZONED1 DC ZONED1 Z'543' F5 F4 C3
ZONED2
DC ZONED2
Z'-123' F1 F2 D3
ZONED3
DC ZONED3
ZL4'+12' F0 F0 F1 C2
ZONED4
DC ZONED4
ZL2'19,-78,963,+3' F1 C9 F7 D8 F6 C3 F0 C3
178

Move Numerics
This instruction copies only the right-most 4 bits of each of the designated bytes of the source fields into the destination fields. The left-most 4 bits are not altered. Format: SAVE MVN D1(L1,B1),D2(B2) DS MVN SAVE before: 01 35 79 2D P'-135792' (presume contents
shown)
SAVE+3(1),=P'1'
SAVE after: 01 35 79 2C
179

The Execute Instruction
EX R1,D2(X2,B2)
The Execute instruction will, at run time, cause the CPU to execute another instruction, called the target instruction, located at the address given in the second operand field. One of the main uses of the EX instruction depends upon its capability for effectively changing the second byte (bits 8-15) of the target instruction. This capability makes it possible to vary the length field contents of SS instructions and to vary the mask field contents of certain RS and SI instructions. Bits 8-15 of the instruction designated by the branch address are OR'ed with bits 24-31 of the register specified by R1, except when register zero is specified, which indicates that no modification takes place. The OR'ing does not change either the contents of the register specified by R1 or the instruction in memory, and it is effective only for the interpretation of the instruction to be executed. Example:
SH EX . . B MOVE MVC AROUND EQU . R6,=H'1' R6,MOVE
AROUND 0(0,R5),0(R7) *
180

The Execute Instruction An alternative way to code the 'target' instruction (Always moves 1 character before the executed move.)
. . MVC 0(0,R5),0(R7) BCTR R6,R0 EX R6,MOVE . .
MOVE
The preferred way to code the 'target' instruction BCTR R6,R0 EX R6,MOVE . . . * DEFINE CONSTANTS . MOVE MVC 0(0,R5),0(R7) . .
181
182

EXERCISE #7. PROGRAM 7. Handling variable length data. Input: 4 variable length fields delineated by a / or EOM(+). b@x/x/x/x+ x = 1 to n characters (max input message length = 58 characters). Process: Isolate each of the 4 fields, categorize each field and display each field on a separate line followed by the category type (field is typed by the first character in the field). Categories: A-I = CATEGORY 1 J-R = CATEGORY 2 S-Z = CATEGORY 3 0-9 = NUMERICS category category
Output:
field1inputdata field2inputdata . .
183
184

Define Constant - Packed Decimal Data
DIGIT DIGIT
DIGIT DIGIT
DIGIT SIGN
PACKED1
DC PACKED1
PL3'123' 00 12 3C
185

Define Constant - Packed Decimal Data PACKED1 DC P'123' 12 3C
PACKED1
PACKED2
DC
P'-12' 01 2D
PACKED2
PACKED3
DC
PL4'-20' 00 00 02 0D
PACKED3
PACKED4
DC
PL2'1234' 23 4C
PACKED4
PACKED5
DC
2P'-12' 01 2D 01 2D
PACKED5
186

Add Packed Decimal
AP
D1(L1,B1),D2(L2,B2)
The Add Packed Decimal instruction performs the following: 1. The second operand (defined by its address) is added to the first operand (defined by its address). 2. Both operands must be in Packed Decimal format. 3. The sum is placed at the first operand location. 4. The condition code is set to 0, 1, 2 when the sum is zero, negative or positive respectively. 5. The length of the first operand must be enough to contain all the significant digits of the result and its sign. If not, an overflow condition will exist (CC = 3) and important data will be lost or corrupted, and the program will continue execution.
187

Add Packed Decimal
AP Before 00 80 5C
FLDA
FLDA,FLDB
19 9C
FLDB
After 01 00 4C
FLDA
19 9C
FLDB
CC
________
188

Add Packed Decimal
AP
FLDC,FLDE
Before 00 14 0D
FLDC
01 0C
FLDE
After 00 13 0D
FLDC
01 0C
FLDE
CC
________
189

Add Packed Decimal
AP
FLDX,FLDY
Before 84 32 1C
FLDX
42 11 1C
FLDY
After 26 43 2C
FLDX
42 11 1C
FLDY
CC
________
190

Subtract Packed Decimal
SP D1(L1,B1),D2(L2,B2)
The Subtract Packed Decimal instruction performs the following: 1. The second operand (defined by its address) is subtracted from the first operand (defined by its address). 2. Both operands must be in Packed Decimal format. 3. The result is placed at the first operand location. 4. The condition code is set to 0, 1, 2 when the sum is zero, negative or positive respectively. 5. The length of the first operand must be enough to contain all the significant digits of the result and its sign. If not, an overflow condition will exist (CC = 3) and important data will be lost or corrupted, and the program will continue execution.
191

SP Before 00 80 5C
FLDA
FLDA,FLDB
19 9C
FLDB
After 00 60 6C
FLDA
19 9C
FLDB
CC
________
192

SP
FLDA,FLDA
Before 00 80 5C
FLDA
After 00 00 0C
FLDA
CC
________
193

Zero and Add Packed Decimal ZAP D1(L1,B1),D2(L2,B2)
This instruction copies a packed decimal number from one memory location to another; padding with zeros takes place as necessary on the high-order end of the operand. The condition code is set according to whether the result was zero, positive or negative. Overflow will occur if significant digits are lost; an overflow willl be signified by CC = 3, important data will be lost or corrupted and the program will continue execution.
194

Zero and Add Packed Decimal
ZAP
RESULT,PACKED
Before F0 F0 F0 F0
RESULT
01 23 45 6C
PACKED
After 01 23 45 6C
RESULT
01 23 45 6C
PACKED
195

Multiply Packed Decimal
MP MP
D1(L1,B1),D2(L2,B2)
MULTIPLICAND,MULTIPLIER
When the Multiply Packed instruction is executed, the number at the first operand location is multiplied by the number at the second operand location. The result replaces the multiplicand in memory, but the condition code is not set. (You can use the CP instruction to determine the sign of the number.) Some rules: 1. The number of bytes in the multiplier must be less than the number of bytes in the multiplicand (L2 < L1). 2. The number of bytes in the multiplier must not exceed 8
(1 <= L2 <= 8).

3. The multiplicand must have at least L2 bytes of leading zeros. The number of bytes of the product (also the multiplicand) is equal to the sum of bytes in the multiplier and the multiplicand.
000000dddddS
Multiplicand
dddddS
Multiplier
Multiplicand Length = Multiplicand + Multiplier
196

MP
A,B
Before 00 00 00 00 01 0C
A
06 54 32 1C
B
After 00 00 65 43 21 0C
A
06 54 32 1C
B
197

MPCD MPLR ZAP MP
DC DC
P'12563' P'21'
12 56 3C 02 1C 00 00 12 56 3C 00 02 63 82 3C
PROD,MPCD PROD,MPLR
PROD
DS
CL5
(In a work block some place)
198

Divide Packed Decimal
DP D1(L1,B1),D2(L2,B2) DP DIVIDEND, DIVISOR
When the Divide Packed instruction is executed, the number at the first operand location is divided by the number at the second operand location. The result consists of two components: 1) "Q", the quotient, of length L1-L2 bytes; and 2) "R", the remainder, of length L2 bytes. The quotient and remainder are stored side-by-side as packed decimal integers in the memory location that had been occupied by the dividend. The sign of the quotient is consistent with the rules of algebra. The sign of the remainder will be the same as the sign of the dividend. Some rules: 1. The number of digits in the divisor must be less than the number of digits in the dividend, including leading zeros. (L2 < L1) 2. The number of digits in the divisor must be less than 16. (1 <= L2 <= 8 bytes) 3. The number of significant digits in the quotient must be smaller than the number of digits that can be stored in the L1 - L2 bytes allowed for the quotient. The dividend should have at least L2 bytes of leading zeros. 4. The divisor must not be zero. 199

DEND DSOR ZAP DP DC DC P'131' P'2'
13 1C 2C 00 13 1C 06 5C 1C
QREM,DEND QREM,DSOR
QREM
DS
CL3
(In a work block some place)
200

DEND DSOR DP DC DC PL4'999' P'-998'
00 00 99 9C 99 8D 00 1D 00 1C
DEND,DSOR
What is wrong with this picture?
201

DEND DSOR DP DS DC PL4'-10' P'3'
00 00 01 0D 00 3C 00 3D 00 1D
DEND(4),DSOR(2)
What's wrong with this picture?
202

Divide Packed Decimal (Presume DEND is in a work block with contents as shown.)
DEND DSOR DP DS DC P'999999' P'01'
09 99 99 9C 00 1C 99 9C 00 0C
DEND,DSOR
Decimal divide exception occurs, execution terminates. Dividend does not have the required number of leading zeros.
203

Compare Packed Decimal CP D1(L1,B1),D2(L2,B2)
This instruction will algebraically compare two operands that are of equal or unequal length (as long as each operand is less than or equal to 16 bytes in length). The condition code is set to 0 (operands equal), 1 (first operand low), or 2 (first operand high). Neither operand is changed by the instruction.
204

Compare Packed Decimal
01 24 3C
00 00 03 4D
01 24 3D
00 00 2C
00 2C
01 2D
CP CP CP CP CP
A,B C,D E,F D,E B,C
CC CC CC CC CC
= = = = =
205

Shift and Round Packed Decimal
SRP SRP
D1(L1,B1),D2(B2),I3
DATA,SHIFT-VALUE,ROUNDING-FACTOR
This instruction will round a packed decimal number and shift the digits the specified number of decimal places, either to the right or to the left. The first operand specifies the location in memory of the number to be operated on. However, the number computed as the effective address from the second operand is not used as an address. Instead, its low order 6 bits denote the number of digits to be shifted and the direction of the shift; if the 6 bits are negative the shift will be to the right; if the 6 bits are positive, the shift will be to the left. The sign is not shifted and any vacated digit positions are zero filled. Rounding occurs only during shifts to the right. However, the rounding factor must always be specified in the instruction. Before a right shift is completed, the rounding factor is added to the left-most digit to be shifted out. For right shifts, the negative integer -N is assumed by the hardware to be in two's complement form. Since the assembler does not translate N to its 6-bit two's complement representation, you should write 64-N rather than -N. See the examples on the following page. On left shifts, 31 is the maximum number of digits that can be shifted. When shifting to the right, the maximum number is 32.
206

SRP
AMT,4,5
Before
00 00 19 65 4C
AMT
After
19 65 40 00 0C
AMT
SRP
AMT,64-2,5
Before
00 00 19 65 4C
AMT
After
00 00 00 19 7C
AMT
207

SRP
AMT,61,5
Before
78 53 97 5D
AMT
After
00 07 85 4D
AMT
SRP
AMT,2,0
Before
01 0C
AMT
After
00 0C
AMT
This last situation causes an overflow error condition. The CC is set to 3 and processing continues.
208

Move With Offset
This instruction copies data from one memory location to another, but the result is shifted to the right to drop off unneeded insignificant digits. The length specified for the second operand represents the bytes to be preserved. Format: MVO D1(L1,B1),D2(L2,B2) SAVE DS PL4 contains P'1234567C'
MVO
SAVE,SAVE(3)
SAVE before: 12 34 56 7C
SAVE after: 01 23 45 6C
209
210

Assembly Language Coding (ALC) Part 3

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IBM Mainframe Assembler Language Coding

The Load Address Instruction

IBM Mainframe Assembler Language Coding

(Assume DATA begins at address 5800)

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

(Assume DATA begins at address 5800)

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

R1,D2(X2,B2) (RX format)

IBM Mainframe Assembler Language Coding

last updated 12/29/99

IBM Mainframe Assembler Language Coding

To load the length of a field into a register: LA R2,L'FIELD

Using L' to loop through a table: LA LA EQU

TABLE CODE AMT RATE

IBM Mainframe Assembler Language Coding

START Your code END

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

START DSECT CSECT END

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

1851 D202 5028 502B 00028 0002B

RECORL,R4 R4,R1 LEG8,CTY8 RECORL,R3 R3,R1 LEG8,CTY8 RECORL,R5 R5,R1 LEG8,CTY8

(Note changes to the base registers in the object code.)

IBM Mainframe Assembler Language Coding

Where: {Label} DS {D} T {Ln}

IBM Mainframe Assembler Language Coding

instead of: PARTY EQU *

IBM Mainframe Assembler Language Coding

(DEFINED IN A WORK AREA)

last updated 12/29/99

IBM Mainframe Assembler Language Coding

INPUT NAME EMPNO ADDR HRS DATE DAY MONTH YEAR

DS ORG DS DS ORG DS DS ORG DS ORG DS DS DS ORG

IBM Mainframe Assembler Language Coding

Layout of FIELD1, FIELD2, FIELD3:

Contents of CODE determine whether to use DATAx or FIELDx labels.

Two different ways to write the overlay:

FIELD1 FIELD2 FIELD3

IBM Mainframe Assembler Language Coding

Null ORG not used:

IBM Mainframe Assembler Language Coding

CL10 CL3 CL1 CL1 CL1 CL6 CL1 CL2 CL55

R1,CE1CR0 R1,MI0ACC INREC,R1 LUGCNT,X'00'

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

IBM Mainframe Assembler Language Coding

0 "AND" Truth Table 0 1 0 0

0 "OR" Truth Table 0 1 0 1

0 "EXCLUSIVE OR" Truth Table 0 1 0 1