OPERATIONAL MANUAL

FOR

SPARTAN-3 FG900 PROTOBOARD MODEL : MXS3FK- 5M Rev : 002

MECHATRONICS TEST EQUIPMENT (I)PVT.LTD. B-3,MAYUR COMPLEX, OPP. BHELKE NAGAR, NEAR YASHAVANTRAO CHAVAN NATYAGRUH, KOTHRUD, PUNE- 411038

PHONE FAX EMAIL URL

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+91-20-25386926 +91-20-25386930 mtepl@vsnl.net www.mte-india.com

TABLE OF CONTE NTS PREFACE .......................................................................................................................................1 About Thi s M anual....................................................................................................................... 1

Manual Contents ......................................................................................................................... 1

CHAPTE R 1 ....................................................................................................................................2 Introdu ction................................................................................................................................... 2

1.1 Features ................................................................................................................................ 2

CHAPTE R 2 ....................................................................................................................................5 High Speed Synchronou s S DRAM .............................................................................................. 5

2.1 Address Bus Connection ........................................................................................................ 5 2.2 Bank Address Selection ......................................................................................................... 6 2.3 Dat a Bus Connection ............................................................................................................. 6 2.4 Dat a Mask Lines Connection .................................................................................................. 7 2.5 Control Lines Connection ....................................................................................................... 7

CHAPTE R 3 ....................................................................................................................................8 US B Inte rface ............................................................................................................................... 8

3.1 Dat a Bus Connection ............................................................................................................. 9 3.2 Control Lines: ........................................................................................................................ 9 3.3. F TDI Driv er Inst allation.......................................................................................................... 9

CHAPTE R 4 .................................................................................................................................. 11 Serial Interfa ce ........................................................................................................................... 11

4.1 R S- 232 Int erf ace..................................................................................................................11 4.2 R S- 422 Int erf ace..................................................................................................................12

CHAPTE R 5 .................................................................................................................................. 13 PS/2 M ou se/Keyboa rd Interfa ce ................................................................................................ 13

5.1 PS/2 Key board .....................................................................................................................14 5.2 PS/2 Mouse..........................................................................................................................15 5.3 Control Signal C onnection .....................................................................................................16

CHAPTE R 6 .................................................................................................................................. 17 Switch es A nd LE Ds ................................................................................................................... 17

6.1 DIP Switc hes ........................................................................................................................17 6.2 Key Switches ........................................................................................................................17 6.3 LED S ...................................................................................................................................17

CHAPTE R 7 .................................................................................................................................. 19 Seven Segment LED Di splay .................................................................................................... 19 CHAPTE R 8 .................................................................................................................................. 21 VGA In terface ............................................................................................................................. 21
8.1 VGA Dis play Theory ..............................................................................................................22 8.2 VGA signal TI MING...............................................................................................................24

CHAPTE R 9 .................................................................................................................................. 25 LCD Interface ............................................................................................................................. 25

9.1 Dat a Lines C onnection..........................................................................................................26 9.2 Control Line Interf ace: ...........................................................................................................26

CHAPTE R 10 ................................................................................................................................ 27 10/100 Non P CI Ethe rnet Inte rfa ce ........................................................................................... 27

10.1 Sy stem Address Bus C onnection .........................................................................................28 10.2 Sy stem Data Bus C onnection ..............................................................................................28

10.3 Control Signals Connection..................................................................................................29

CHAPTE R 11 ................................................................................................................................ 32 Conne cto r Details....................................................................................................................... 32

11.1 I O Connectors ....................................................................................................................32 11.2 Stackable C onnect or ...........................................................................................................36

CHAPTE R 12 ................................................................................................................................ 39 Clock and Re set Sou rce s .......................................................................................................... 39 CHAPTE R 13 ................................................................................................................................ 40 SPARTAN-3 Configuration Det ails............................................................................................ 40
13.1 Boundary Scan mode: .........................................................................................................40 13.2 Master Serial Mode .............................................................................................................40 13.3 Jum per Setting....................................................................................................................40

CHAPTE R 14 ................................................................................................................................ 43 Power Supplies.......................................................................................................................... 43

14.1 Voltage Regulators ..............................................................................................................43

APPENDIX A................................................................................................................................. 44 Consolidated UCF For The Com plete Board ............................................................................ 44 APPENDIX B................................................................................................................................. 58 Operating Inst ruction To St art A Ne w De s ign ........................................................................... 58
B.1 Starting The ISE Sof tware: ....................................................................................................58 B.2 D esign Flow .........................................................................................................................58 B.3 D esign Desc ription ...............................................................................................................59 B.4 Truth Table of Half adder ......................................................................................................59 B.5 VHDL C ode f or Half adder ....................................................................................................59 B.6 Steps to implement the H alf adder in the F PGA using Xilinx iSE(8.1i) ......................................60

APPENDIX C................................................................................................................................. 74 AS CII Table 5 X 7 LCD Display ................................................................................................. 74 APPENDIX D................................................................................................................................. 75 ADC DA C Add On Card ............................................................................................................ 75 APPENDIX E................................................................................................................................. 81 Video ADC DA C Add On Card ............................................................................................... 81
F.1 Video AD C int erf ace .............................................................................................................81 F.2 VIDEO D AC .........................................................................................................................82 F.3 SYNC SEPERATOR .............................................................................................................83 F.4 Consolidated UCF f or All Mother Boards: ...............................................................................85

LIS T OF TABLES Table 1 Address Bu s Int erfa ce to SPA RTA N-3 FP GA ...................................................................6 Table 2: Ban k Addre ss Selection Inte rface to SP A RTAN-3 FPGA ................................................6 Table 3 Data Bu s Interface to S PA RTA N-3 FP GA .........................................................................6 Table 4: Data B us Inte rface to SPA RTAN-3 FPGA ........................................................................7 Table 5: Control Lines Inte rface to SP A RTAN-3 FPGA .................................................................7 Table 6: Data B us Inte rface to SPA RTAN-3 FPGA ........................................................................9 Table 7: Control Lines Inte rface to SP A RTAN-3 FPGA .................................................................9 Table 8: RS232 Inte rface t o SP ARTA N-3 FPGA.......................................................................... 11 Table 9: RS422 Inte rface t o SP ARTA N-3 FPGA.......................................................................... 12 Table 10: PS/2 Conne ctor Details................................................................................................. 13 Table 11: PS/2 Bus Tim ing ........................................................................................................... 13 Table 12: Comm on PS/2 Keyboard Comm ands.......................................................................... 15 Table 13: LED Statu s.................................................................................................................... 15 Table 14: PS/2 Inte rface to SPARTAN-3 FPGA........................................................................... 16 Table 15: DIP swit ch Interfa ce to S PA RTA N-3 FPGA ................................................................. 17 Table 16: KEY switch Inte rface to SPA RTAN-3 FPGA ................................................................ 17 Table 17: LED I nterf ace to SPA RTAN-3 FPGA ............................................................................ 17 Table 18: Seven Segm ent Di splay I nterface to SPARTA N-3 FPGA............................................ 20 Table 19: VGA Int erface to SPARTAN-3 FPGA ........................................................................... 22 Table 20: VGA sign al timing.......................................................................................................... 24 Table 21: Data Line Inte rfa ce to S PARTA N-3 FP GA ................................................................... 26 Table 22: Cont rol Line Interface to SPARTAN-3 FPGA ............................................................... 26 Table 23: Addre ss Bus I nterface to SPARTAN-3 FPGA .............................................................. 28 Table 24: Data Bus Int erfa ce to SPARTA N-3 FPGA.................................................................... 28 Table 25: Synch ron ou s Bu s Int erfa ce to SPA RTA N-3 FP GA ...................................................... 30 Table 26: A syn chronou s Bu s Inte rface to SPA RTAN-3 FPGA .................................................... 30 Table 27: M is cellaneou s Signal s Interface to S PA RTAN-3 FPGA .............................................. 31 Table 28: IOCON1 Connector Inte rface to FP GA ........................................................................ 32 Table 29: IOCON2 Connector Inte rface to FP GA ........................................................................ 33 Table 30: IOCON3 Connector Inte rface to FP GA ........................................................................ 33 Table 31: IOCON4 Connector Inte rface to FP GA ........................................................................ 34 Table 32 IOCON5 Conn ector Inte rface to FP GA ......................................................................... 34 Table 33: IOCON6 Connector Inte rface to FP GA ........................................................................ 35 Table 34: IOCON7 Connector Inte rface to FP GA ........................................................................ 35 Table 35: IOCON8 Connector Inte rface to FP GA ........................................................................ 36 Table 36: IOCON9 Connector Inte rface to FP GA ........................................................................ 36 Table 37: Stackable Connecto r Inte rfa ce to FP GA ...................................................................... 36 Table 38: IO Clock-Re set Inte rface to FPGA ............................................................................... 39 Table 39: M ode Selection Jum per Setting s.................................................................................. 40 Table 40: M ode Selection Table................................................................................................... 40 Table 41: Powe r Supply Details.................................................................................................... 43

LIS T OF FI GURES Figure 1: Block Diag ram ..................................................................................................................3 Figure 2: FPGA S DRAM Interface ...............................................................................................5 Figure 3: FPGA USB Interface.....................................................................................................8 Figure 4: FPGA RS232 I nterf ace ...............................................................................................11 Figure 5: FPGA RS422 I nterf ace ...............................................................................................12 Figure 6: PS/2 Connector.............................................................................................................. 13 Figure 7: PS/2 Timing Diagram ..................................................................................................... 14 Figure 8: PS/2 Keyb oard with scan codes.................................................................................... 14 Figure 9: Data fo rm at for P S/2 mou s e interfa ce ........................................................................... 16 Figure 10 : Seven Segm ent Di splay .............................................................................................. 19 Figure 11 : FPGA V GA Inte rfa ce .................................................................................................21 Figure 12 : CRT Di splay Tim ing..................................................................................................... 23 Figure 13 : VGA Tim ing.................................................................................................................. 24 Figure 14 : L CD Inte rface to SP ARTAN-3 FPGA .......................................................................... 25 Figure 15 : LAN 91C11 1 Interface to SPA RTA N-3 FPGA............................................................. 28 Figure 16 : Positional Details of On Bo ard Co nnectors................................................................. 38 Figure 17 : JTAG M ode Selection.................................................................................................. 41 Figure 18 : JTAG Conne cto r Details..............................................................................................42

PREFACE
A bout This Manual
This manual gives ope rational details for all the interface s. This manual contain s following ch apte rs : Chapter 1, Int rodu ction Chapter 2, High Spee d Synch ronous SDRAM Chapter 3, USB Interface Chapter 4, S erial Interface Chapter 5, P S/2 M ouse/K eyboard Int erfa ce Chapter 6, S witche s A nd LEDs Chapter 7, S even Segment LE D Display Chapter 8, V GA Interf ace Chapter 9, L CD Inte rfa ce Chapter 10, 10/ 100 Non P CI Ethe rnet Int erfa ce Chapter 11, Connecto r Detail s Chapter 12, Clock And Re set Source s Chapter 13, SPARTAN-3 Configu ration Details Chapter 14, Po wer Supplie s Appendix A Con solidated UCF for the com plete Board Appendix B Ope rating Inst ruction to Start a Ne w Design Appendix C AS CII Table 5x7 L CD Di splay Appendix D ADC DA C Add On Card Detail s Appendix E VI DEO ADC DAC Add On Card Details

Manual Cont ent s

CHAPTER 1
Introduction
SPA RTA N-3-FG900 De velopm ent Board (MXS3 FK-5M ) provide s a n ea sy to u se development platform for realizing variou s de s i gns a round SPART AN-3 FP GA.

1.1 Features

Figure 1 sho ws the SPARTAN-3 Development Board, which include s the following components and featu re s: Spartan-3 family is building on the s u ccessor Spa rtan -IIE family by increasi ng the amount of logic re sou rces, the capa city of internal RAM, the total no of I/Os and o verall level of perfo rmance as well as by improving clock managem ent function s . Revolutionary 9 0 nm proce ss techn ology Very low co st, high perform ance logic solution s f or high volume con sum ero riented application Den sitie s as high a s 74,880 logic cell s Upto 326 MHz system clock rate Three se parate power sup plies fo r the co re (1.2), I/Os(1 .2 to 3.3 ), and special function(2.5 V) Select I/O sig nalling Abundant, flexible logic cells with regi sters, wide multiplexer, dedicated 18x18 multiplier, Up to 1872 Kbit s of total block RAM Up to 520 Kbit s of total dist ributed RAM Digital clock manager (up to f our DCM ) Eight global clock lines a nd abunda nt routing. Fully s uppo rted by Xilinx ISE de velopm ent system Unlim ited reprogram ability. Very low co st. Platform Fl ash: 16 Mbit Xilinx XCF16P in-system configurable platform flash f or configuration th rough P ROM in VO 48 package. 1.8V sup ply voltage Serial or pa rallel FPGA configu ration interface (up to 33 M Hz) Available in small-footprint VO4 8, V OG48, FS48, and FS G48 pa ckages Design re vi sion technology enable s storing an d acce ss in g m ultiple design revi sion s for configuration. Built-in data decompre ssor com patible with Xilinx advanced com pre ss ion te chnology SDRAM : 4 Meg x 3 2 M icron S DRAM MT48LC4M 32B2 a s a high speed syn chronous m em ory interfa ce in TSOP-86 package PC1 00 functionality Fully s yn chronou s; all signal s regi stered on po s itive edge of system clock Internal pipelined operation; colum n addre ss can b e chan ged every clock cycle Internal ban ks fo r hiding ro w a cce ss/precharge Prog ram mable burst length s: 1, 2, 4, 8, or full page Auto Precharge, include s concu rrent Auto precha rge, and Auto Refre sh Modes Self Ref resh Mode 64ms, 4,096-cycle refre sh (15.6s/row) LVTTL-compatible inputs a nd outputs Single +3.3V 0.3V po wer supply Support s CA S latency of 1, 2, a nd 3

Figure 1: Block Dia gra m USB Controller: Co s t effective, e a sy to u se USB FI FO I C FT245 BM from FTDI in L QFP-3 2 package to t ran sfer da ta to / f rom FPGA and host PC at upto 1M byte per se cond. Single Chip USB P arallel FIFO bi-directional Da ta Tran sfe r Tran sfer Data rate to 1M Byte / Sec - D2X X Drive rs

Tran sfer Data rate to 300 Kilobyte / Sec - V CP Drive rs Simple to interface to M CU / PL D/ FPGA logic with a 4 wire hand sha ke interface Entire USB prot ocol handled on -chip, no USB -s pe cific firmware pro gram ming required 384 Byte FI FO Tx buffe r / 128 Byt e FI FO Rx Buffe r for high data throughput . Integrate d 3.3V regulato r fo r USB I O Integrate d Po we r-On -Re s e t circuit Integrate d 6MHz 48M Hz clock m ultiplier PLL USB Bul k o r I sochronou s data t ran sfe r mode s

Etherne t Controller: 10/10 0 Non P CI s ingle chip Ethernet controller LA N 91c111 f rom SMSC in QFP packa ge. Support s full duplex switched Ethe rnet. Support s bu rst tran sfer. 8 Kbytes of internal memory for receive and t ransmit FIFO buffers. Optional configuration th rough serial EEP ROM Support s 8, 1 6, 32 bit CPU accesse s. Single 25 M Hz Clock fo r both P HY an d MAC. Fully integrated I EEE 802.3 / 802. 3 u -100 Ba se TX/ 10 Ba se-T ph ys ical layer. VGA dis pla y P ort: 12 bit, 512 colours VGA di s play port. RS2 32 Serial I nte rface: 9 pin two chann el serial interfaces. DB9 9-pin female conne ctor (DCE connector) RS-232 t ran sceiver/level t ranslato r using M AX3223 in SSOP package. Use s straight -th rough serial cable to conne ct to computer or workst ation s e rial port. RS4 22 Seri al Interfac e: 1 0 pin two chann el serial interface s. 10 pin berg connector. RS-422 d ual differential drivers and re ceivers SN65C118 in TSS OP pa ckag e PS/2 Inte rface: PS/2-style mou s e/ keyboa rd port. Sev en Segment Displa y: Four-characte r, seven -segment LED display. DIP Switches: Eight DIP swit ches. LEDs : 13 onboard LEDS 8 use r LE Ds (RED) Single configuration s tat us L ED (GREE N) 4 Po wer on indicator LE Ds(RE D) Pus h Button Switches : Four momentary-contact pu sh button swit che s. LCD inte rfac e: 16 cha racter 2 row LCD . M ictor Connec tor: Facilitates p ro vision for L ogic Analyzer interface. Stackable Connector: Facilitates provision fo r interfa ce of A DD ON Bo ard s Free I Os : 289 f ree I Os. Cl ock Oscillator: 40 M Hz crystal clock o scillator. So ck e t for an auxiliary crys t al o scillator clock sou rce. J TAG port: 10 Pin FRC male connector fo r JTAG do wnload ca ble (parallel III) interface that connect s to the parallel port of ho st P C. Pow er Supplies : 5 volt s regulated po wer supply pro vided along with the board. On board 3.3 V, 2.5V, 1.8V, 1.2 V regulators. On board generation of -5V supply.

CHAPTER 2
High Speed Synchronous SDRA M
SPA RTA N-3 Developm ent Boa rd has a single 4 Meg x 32 high speed synch ronou s SDRAM (MT48LC4M 32B2), s u rface mounted on top side of the board. A detailed interface is a s shown in Figure 2.

Figure 2: FP GA SDRAM Int erface This SDRAM i s internally configured a s quad ban k DRAM with synchronou s interfa ce (all signals regi stered o n po s itive clock edge). The SDRAM provides f or p rog ram mable REA D o r W RITE bu rst length s of 1, 2, 4, o r 8 location s, or the full page, with a burst te rminate option. An auto p re charge fun ction m ay be enabled to provide a self-timed ro w p recha rge that i s initiated at the end of the b urst se quence.

2.1 Address Bus Connection

SDRAM ha s a 12 bit addre ss bus interface with FPGA. A0A11 are sam pled during the A CTIV E com mand (row-add ress A 0A10) and REA D/W RITE command (column-address A0A8 with A 10 defining auto p recha rge ) to select one location out of the m em ory arra y in the re spe ctive ba n k . A 10 i s sampled during a PRE CHA RGE command to determ ine if all banks are to be p recharged (A10 [ HIGH]) o r ban k selected b y BA0, BA1 (L OW). The addre ss input s al s o provide the op -code du ring a LOA D M ODE REGISTE R com mand. 5

Ta ble 1 Address Bus Int erface to SPARTAN-3 FPGA Address Bit "A0_S1" "A1_S1" "A2_S1" "A3_S1" "A4_S1" "A5_S1" "A6_S1" "A7_S1" "A8_S1" "A9_S1" "A10_S1" "A11_S1" FPGA Pin
AA7 Y8 Y7 K7 L8 L7 M8 M7 N8 P7 AB8 AC7

2.2 Bank Address Selection

Ban k Addre ss Input (s): BA0 and BA1 define to which ban k t he A CTIVE , READ, WRITE, o r PRE CHA RGE com mand is being applied. Ta ble 2: Ba nk Addr ess Selection Int erfa ce t o SPARTAN-3 FP GA Bank Address Selection Bit "BA0_S1" "BA1_S1" FPGA Pin
V8 W7

2.3 Data Bus Connection

32 bit bidirectional data bu s interf ace. Table 3 Data Bus Int erface t o SP ARTAN-3 FP GA Data Bit "D0_S1" "D1_S1" "D2_S1" "D3_S1" "D4_S1" "D5_S1" "D6_S1" "D7_S1" "D8_S1" FPGA Pin
AE5 AD6 AC6 AC5 AB6 AB5 AA6 Y6 L6

Data Bit "D16_S1" "D17_S1" "D18_S1" "D19_S1" "D20_S1" "D21_S1" "D22_S1" "D23_S1" "D24_S1"

FPGA Pin
T5 T6 U6 V5 V6 W5 W6 Y5 R5

Data Bit "D9_S1" "D10_S1" "D11_S1" "D12_S1" "D13_S1" "D14_S1" "D15_S1"

FPGA Pin
K6 J5 J6 H5 H6 G6 F5

Data Bit "D25_S1" "D26_S1" "D27_S1" "D28_S1" "D29_S1" "D30_S1" "D31_S1"

FPGA Pin
R6 P6 N5 N6 M5 M6 L5

2.4 Data M ask Lines Connection

DQM is sam pled high and i s an input ma sk signal fo r write a cce sse s and an output enable signal fo r re ad acce sse s. Input da ta i s masked d uring a WRITE cycle. The output buffe rs a re placed in a High -Z state (t wo clock latency) du ring a REA D cycle. DQM 0 corre sponds to DQ0 DQ7, DQM1 co rrespon ds to DQ8 -DQ15, DQM 2 corre spond s to DQ16 DQ23 and DQM3 corre spond s to DQ2 4 DQ31. DQM 0DQM3 is considered same state when referenced a s DQM . Table 4: Data Bus Int erfa ce t o SPARTAN-3 FP GA Data Bit "DQM0_S1" "DQM1_S1" FPGA Pin
R8 H7

Data Bit "DQM2_S1" "DQM3_S1"

FPGA Pin
W8 J8

2.5 Control Lines Connection

Clock: CLK i s d riven by the system clock. All SDRAM input signals are sam pled on the positive edge of CL K. CKE activat e s (HIGH) and deactivate s (LOW) the CLK signal. CS# enable s (re gi stered LOW) and di sables (regi ste red HIGH) the com mand decoder. Com mand Input s: W E#, CAS#, and RA S# (along with CS #) define the com mand. Ta ble 5: Control Lines Interface t o SPARTAN-3 FPGA Control Bit "CAS#_S1" "CKE_S1" "CLK_S1" FPGA Pin T7 K9 K10 Control Bit "CS#_S1" "RAS#_S1" "WE#_S1" FPGA Pin U7 T8 R7

CHAPTER 3
USB Interface
SPA RTA N-3 Board ha s a USB interfa ce u sing device FT245BM from FT DI. It offers data tran sfer rate s up to 8 M illion bits (1 Megabyte ) pe r se cond. To send data f rom the FPGA to the ho st com puter, simply write the byte-wide data into the m odule when TXE# is low. If the (384 -byte) t ransmit buffe r fills up o r is busy storing the previou sl y written b yte, the device keeps TXE# high in order to stop f urther da ta from being written until som e of the FI FO d ata ha s been t ran sferred ove r USB to the ho st. TXE# goe s high after every b yte written. When the ho st send s data to the FPGA over USB, the de vice will take RXF# lo w to let the FPGA know that at lea st one b yte of data i s available. The FPGA can read a data byte eve ry time RXF# goe s low. RXF# goe s high after every byte read. FTDI chip support s t wo drivers: VCP Drivers D2xx Drivers SPA RTA N-3 board use s D2 xx Drivers that allow application soft wa re to access the de vice dire ctly th roug h a published DLL ba sed API. For more details on Drivers vi sit http:// www.ftdichip. com

Figure 3: FP GA USB Interface

3.1 Data Bus Connection

8 bit bidirectional data bus for data tran sfe r from / to FPGA and USB interface. Table 6: Data Bus Int erfa ce t o SPARTAN-3 FP GA Data Bit "USB_D0" "USB_D1" "USB_D2" "USB_D3" "USB_D4" "USB_D5" "USB_D6" "USB_D7" FPGA Pin
T28 R28 R27 P28 N27 M28 M27 L28

Cont rol gro up interfa ce con s i st of following signal s: RD # : Enables reading of data byte f rom USB controller on dat a line interface when lo w. WR# : Write s data byte from D0-D7 into the transmit FIFO of USB. TXE #: Dat a write enable. RXF #: Data read e nable. Ta ble 7: Control Lines Interface t o SPARTAN-3 FPGA Control Bit "TXE#" "WR#" "RD#" "RXF#" FPGA Pin H28 J27 K28 L27

3.2 Control Lines:

3.3. FTDI Driver Installation

To ins tall the FT DI d rivers on you r PC s im ply run the FTDI_S etup.e xe file provided in the CD a ccompanied with your Developm ent board. After succe ssful in stallation following message will be displayed on screen

After inst allation when USB device plugged in Device M anager will add US B Serial Converter controller into its US B Serial Bus Controller list as sho wn belo w:

When USB device plugged in Dev ice Manager will add USB Se rial Converter controller into its US B Serial Bus Controll er list as sho wn belo w

Your system is ready to communicate t hrough USB port.

10

CHAPTER 4
Serial Interface
The SPA RTAN-3 de velopm ent board support s RS-23 2 and RS-422 (differential) se rial interface. Details of both inte rface is described below.

4.1 RS- 232 Int erface

The RS -232 tran s m it and receive si gnals appear on t he fem ale DB9 conne cto r, indicated a s in Figure 4. The conne cto r i s a DCE -style port and connect s to the DB9 DTE-style se rial port connector a vailable on most pe rsonal com puters and wo rkstations. Use a standard straight through serial cable to connect the SPARTAN-3 development board to the PCs serial port.

Figure 4: FPGA RS232 Int erfa ce Figure 4 -1 shows t he co nnection bet ween the FP GA and the DB9 conne cto r, including the M axim M AX3223 RS-232 voltage con verte r. The FPGA sup plies serial output data as L VTTL or LVCMOS level s to the Maxim device, which in turn, con vert s the logic value to the app rop riate RS-232 voltage level. Li k e wise, the M axim device con ve rts the RS-232 serial input data to LVTTL levels fo r the FPGA. Hard wa re flow cont rol is not su pported on the conne ctor. The po rts DCD, DTR, and DSR signals a re left unconne cted. Similarly, the ports CTS and Ring Indicator are u sed as an auxiliary RS232 channel signal s The FPGA connection s to the Maxim RS-232 t ran s lator app ear in Table 4-1 . Ta ble 8: RS232 Interface t o SPARTAN-3 FPGA Control Bit
"TXD1-F" "TXD2-F" "RXD1-F" "RXD2-F"

FPGA Pin
AH8 AG8 AG9 AH10

11

For more details on RS232 UA RT application please ref er th e following application note AN2 141 f rom M axim.

4.2 RS- 422 Int erface

Two RS4 22 compatible tran smit and re ceive channel s are provided o n board using SN6 5C1168 a dual differential driver a nd receive r. E xternal connectivity is p rovided using 10-pin Berg conne ctor for tran smitter as well as receive r.

Figure 5: FPGA RS422 Int erfa ce Figure 5 sho ws the connection between the FPGA an d the 10 pin e xternal connector. The FPGA supplies se rial output data as LVTTL or LV CM OS level s to t he S N65 C118.device. SN6 5C118.i s a dual differe ntial driver and re ceive r that convert s the logic value to the appropriate RS -422 voltage level and vice ve rs a. The FPGA connection s to RS-422 dual differential transm itter/receiver appear a s in Table 4-2. Ta ble 9: RS422 Interface t o SPARTAN-3 FPGA Control Bit
"TTL_IN1_QS" "TTL_IN2_QS" "TTL_OUT1_QS" "TTL_OUT2_QS"

FPGA Pin
G10 H9 E6 F6

12

CHAPTER 5
PS/2 Mouse/ Keyboard Int erface
SPA RTA N-3 de velopm ent board includes a sepa rate PS/2 p ort s for mou s e and keyboard interface using a sta ndard 6 in PS/2 conne cto r a s sho wn in figure 6.

Figure 6: P S/2 Connect or Both a P C m ou se a nd keyboa rd u se the t wo-wire PS/2 serial bu s to com municate with a host device, the SPA RTA N-3 FP GA in thi s case. The PS/2 bu s includes b oth clock and data. Both a m ouse and keyboa rd d rive the bu s with identical signal timings and both u se 11 -bit wo rds tha t include a start, stop and odd pa rity bit. Ho we ver, the data packet s a re o rganize d differently fo r a m ouse and keyboa rd. Furt herm ore, the ke yboard inte rface allows bidirectional data transfe rs. Table 10: P S/2 Connect or Details PS/2 Connector Pin 1 2 3 4 5 6 Signal DATA(PS2D) Reserved GND Voltage Supply CLK(PS2C) Reserved

The PS/2 bu s timing appears Table 11 and Figure 7. The clock and dat a signal s a re only d riven when data t ran sfers occur, and otherwi s e they a re held in the idle state at logic High. The timings define signal requirement s for mou s e -to-host com munications and bidirectional keyboard comm unications. As shown in Figure 7, the atta ched keyboard or mouse writes a bit on the data line whe n the clock s ignal i s high, and th e ho st read s the d ata line when t he clock signal i s low. Table 11: P S/2 Bus Timing Symbol TCK TSU THLD Parameter Clock high or low time Data to clock setup time Clock to data hold time Min 30s 5s 5s Max 50s 25s 25s 13

Figure 7: P S/2 Timing Dia gra m

5.1 P S/2 Keyboard

The keyboa rd u ses open-collecto r drivers s o that either the keyboa rd o r the ho st can d rive the two-wire bu s. If the ho st ne ver sends dat a to the keyb oard, then the ho st can u se simple input pins. A PS/2-st yle k e yboa rd u se s scan code s to comm unicate k e y pre ss data. Nearly all k eybo ards in us e toda y a re PS/ 2 s t yle. Each ke y ha s a single, unique scan co de that i s sent whene ver the corre sponding key i s p ressed. The scan code s fo r m o s t keys appea r in Figure 8.

Figure 8: P S/2 Key board with scan codes 14

Som e ke ys, called extende d ke ys, send a n E0 ahead of th e scan code and fu rthe rmore, the y m ay send m ore than o ne scan code. When an e xtended ke y is relea sed, a E0 F0 k e y up code is sent, followed by the sca n code . If the k e y i s pre ssed and h eld, the keyboa rd repeatedly send s the scan code e very 10 0 m s or so. When a key i s relea s ed, the ke yboard s e nds a F0 key-up code, followed b y the scan code of the relea sed key. The keybo ard sends the sam e scan code, rega rdle ss if a key has different shift and non -shift chara cters and rega rdle ss whether the Shift key is pre sse d o r not. The host dete rm ines which cha racter i s intende d. The most comm only used com mands for PS/ 2 ke yboard are as follows: Table 12: Common P S/2 Keyboard Commands Command Description Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs. The keyboard acknowledges receipt of an ED command by replying with an FA, after which the host sends another byte to set LED status. The bit positions for the keyboard LEDs appear in Table 13. Write a 1 to the specific bit to illuminate the associated keyboard LED.
Upon receiving an echo command, the keyboard replies with the same scan code EE. Resend. Upon receiving a resend command, the keyboard resends the last scan code sent.

ED

EE FE FF F3

Reset. Resets the keyboard.

Set scan code repeat rate. The keyboard acknowledges receipt of an F3 by returning an FA after which the host sends a second byte to set the repeat rate.

Table 13: LED Stat us 7 6 5 4 3 2 caps lock 1 num lock 0 scroll lock

The keyboa rd send s data to t he ho st only when bot h the data and clock line s are High, the idle state. Because the ho st i s the bu s m aster, the keyboa rd checks whet her t he ho st i s s ending dat a before d riving the bu s. The clock line can be u sed as a clea r to send signal. If the ho st pulls the clock line Lo w, the keyboard m ust not s e nd any data until the clock i s relea sed. The keyboard send s data to the ho st in 11-bit word s that cont ain a 0 sta rt bit, followed by eight bit s of scan code (L SB first), f ollowed by an odd parity bit and te rminated with a 1 stop bit. When the keyboard send s data, it generat es 11 clock transition s at around 20 to 30 kHz, and data i s valid on the falling edge of the clock a s shown in Figu re 7.

5.2 P S/2 M ouse

A mouse generate s a clock and dat a signal when moved; otherwise, the se signal s rem ain High indicating the Idle stat e. Ea ch time the mouse is moved, the mou se sends three 11 -bit words to the host. Each o f the 11 -bit words contain s a 0 start bit, followed by 8 data bit s (LSB first ), followed by an odd pa rity bit, and term inated with a 1 sto p bit. Each data tran smi ssion co ntains 33 total bit s, where bit s 0, 11, and 22 are 0 start bit s, a nd bit s 10, 2 1, and 32 are 1 stop bit s. The th ree 8-bit data field s contain m ovement data a s shown in

15

Figure 9. Da ta i s valid at the falling edge of the clock, and the clock period is 20 to 30 kHz. PS/2 mouse em ploys a relative coo rdinate system wherein m oving the mous e to the right generate s a po sitive value in the X field, and moving to the left gene rate s a negative value. Lik e wise, m oving the m ou se up gene rate s a positive value in the Y field, and m oving down repre s ent s a ne gative value. The XS and YS bit s in the statu s byte define the sign of e ach value, wh ere a 1 indicate s a n egative value. The magnitude of the X and Y values rep resent the rate of m ou se m ovement. The larger the value, the fa ster th e mouse is moving. The XV and YV bit s in the status byt e indicate when the X or Y value s exceed their maximum value, an overflow condition. A 1 indicate s when an overflow occurs. If the mou se moves continuousl y, the 33 -bit transm issions repeat eve ry 50 m s or so . The L and R fields in the statu s byte indicate Left and Right butt on presses. A 1 indicates that the a ssociated mou se butt on i s being pre ssed.

Figure 9: Data format for P S/2 mouse int erfa ce

5.3 Control Signal Connection

Ta ble 14: PS/2 Interface t o SP ARTAN-3 FPGA KEY BOARD Control Bit "KBD_CLOCK_QS" "KBD_DATA_QS" M OUSE Control Bit "MOUSE_CLOCK_QS" "MOUSE_DATA_QS" FPGA Pin
J18 K17

FPGA Pin
G19 H18

16

CHAPTER 6
Swit ches And LEDs
6.1 DIP Switches
The SPA RTAN-3 de velopm ent board has eight DIP swit che s. The switche s conne ct to an associated FP GA pin, a s sho wn in Table 15 A 4.7K se ries resi sto r provide s nominal input prote ction. Ta ble 15: DIP switch Int erface to SPARTAN-3 FPGA Control Bit FPGA Pin "IL0" AJ12 "IL1" AK11 "IL2" AJ11 "IL3" AJ10 "IL4" AK8 "IL5" AJ8 "IL6" AK7 "IL7" AJ7

When in the UP or ON position, a switch connect s t he FPGA pin to VCC O, a logic High. When DOW N o r in the OFF po s ition, the swit ch con nect s the FPGA pin to ground, a logic Lo w. The switche s typically exhibit about 2 m s of m echanical boun ce and there i s no active deboun cing circuitry, although such circuitry could ea sily be a dded to the FPGA de sign prog ram med on the board.

6.2 Key Swit ches

The SPA RTAN-3 de velopm ent board has fou r momentary-conta ct Key switche s, indicated as in Figure xx. These a re located along the lower edg e of the bo ard, toward the left edge. The switche s are labeled K0 th roug h K3.key swit ch K3 i s t he left-mo st switch, K0 the right -most switch. The switche s connect to an associated FPGA pin, a s sho wn in Table 16. P ressing a ke y generate s logic High on the associated FPGA pin. There is no active d ebouncing circuitry on the key swit che s. Ta ble 16: KEY switch Interface to SP ARTAN-3 FPGA Control Bit FPGA Pin "KEY0"
AG20

"KEY1"
AH20

"KEY2"
AG19

"KEY3" AH19

The SPA RTAN-3 de velopm ent board has eight individual su rface-m ount red LE Ds located above the key switche s, indicated by in Figure xx. The LE Ds are labeled LE D7 through LE D0 . LED7 i s the left-mo st L ED, LE D0 th e right -most LED. Table 17 sho ws the FPGA conne ctions to the LEDs. A se ries cu rrent lim iting re si s tor of 270 i s associated with every LE D. To light an individual LED, drive t he a ssociated FPGA cont rol signal High Ta ble 17: LED Int erface to SPARTAN-3 FPGA Control Bit "TESTLED0" "TESTLED1" "TESTLED2" "TESTLED3" "TESTLED4" "TESTLED5" "TESTLED6" "TESTLED7" FPGA Pin
AG18 AH17 AG15 AH14 AG13 AH12 AG12 AH11

6.3 LEDS

17

18

CHAPTER 7
Sev en Segment LED Display
The SPA RTAN-3 de velopm ent board has a four-cha racter, seven segm ent LE D di splay controlled by FP GA use r-I/O pins. Each digit shares eight comm on cont rol signals to light individual LED segm ent s . Each individual cha racter has a sepa rate cathode control input. To light an individual signal, drive the individual segm ent cont rol s ignal High along with the a sso ciated cath ode co ntrol s ignal for the individual chara cte r. The co ntrol signal i s high, enabling the control inputs for t he left-mo st chara cte r. The segm ent cont rol inputs, A th rough G and DP, drive the individual segment s that compri s e the cha racter. A High value lights the individual segm ent, a Low turn s off the se gment.

Figure 10: Sev en Segment Display The two t ype s of the seven s egment di s plays are as sho wn belo w Common Cathode Dis pla y: In thi s t ype of di splay t he cathode of all the LE Ds are tied together and the an ode terminals decides the s ta tus of the LED, either ON or OFF. To turn ON the LED i.e segment value of d riven segm ent s hould be 1 and 0 for t urn OFF.

Common Anode Display: In this t ype of display all the anode te rm inals of LEDs are tied together and the cathode t erminals de cide the s t atus of the LED either ON or OFF. To turn ON the LED i.e. segment value of driven segment should be 0 and 1 for turn OFF.

19

Interface detail s fo r the seven segment di splay with SPART AN-3 di spla y i s as follows Ta ble 18: Seven Segment Display Int erfa ce to SPARTAN-3 FP GA Control Bit "SEGA" "SEGB" "SEGC" "SEGD" "SEGE" "SEGF" "SEGG" "SEGDP" "CSDIS0" "CSDIS1" "CSDIS2" "CSDIS3" FPGA Pin
AC9 AF9 AJ6 AK5 AJ5 AJ4 AK4 AG11 AD8 AC8 AD7 AE9

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CHAPTER 8
VG A Interface
The SPA RTAN-3 de velopm ent board include s a V GA di splay po rt an d DB15 conne cto r, indicated a s in Figure 1. Thi s port con nect s directly to mo s t P C monitors or flat -panel L CD dis plays using a standa rd m onitor cable. VGA stands for Video Graphics A rray, sometimes referred to as Video Graphics Adapter. It i s a video ca rd, which i s an inte rface between a computer and it s co rresp onding monitor. The VGA card i s the m ost comm on video ca rd nea rly every video ca rd has VGA compatibility and it is fairly ea sy to program. It offers many different video modes, f rom 2 colours to 256 colour, a nd re s olutions f rom 320x20 0 to 640x480.

Figure 11: FP GA VGA Int erface

21

A s shown in Figure 11, the SPARTAN-3 FPGA cont rols 9 V GA signals: thre e for Red, three fo r Gree n, th ree fo r Blue, Horizontal Syn c, and Vertical Syn c, all available on the VGA conne ctor. The FPGA pins that drive the V GA po rt ap pear in Table 19. Ta ble 19: VGA Interface to SP ARTAN-3 FPGA Control Bit "RED_0" "RED_1" "RED_2" "GREEN_0" "GREEN_1" "GREEN_2" "BLUE_0" "BLUE_1" "BLUE_2" "HOR_SYNC" "VER_SYNC" FPGA Pin
AH7 AG7 AH6 AG5 AH4 AG4 AF4 AE3 AD4 AG3 AD3

Each colour line compri s e s of 3 bit s .Thu s total of 23 x 23 x23 i.e. 256 colours are ge nerated. The serie s re sistor u ses the 75 V GA cable termination to en s u re that the colour si gnal s remain in the VGA-specified 0V to 0.7V range. The HS and VS s ignal s are TTL level. Red, Green Blue bits a re d riven High or Low to gen erat e different colours.

8.1 VGA Di s play Theory

CRT-ba sed VGA di splays u se amplitude-modulated, moving electron beam s (or cathode rays) to display inform ation on a pho sphor-coated screen. L CD di spla ys u se an a rray of swit che s that impos e a voltage a cro ss a small amount of liquid crystal, thereb y changing light permittivity through t he crystal on a pixel-b y-pixel basi s . Although the following description is limited to CRT dis plays, LCD di s plays have evolve d to u se the same signal tim ings as CRT di splays. Con sequently, t he following di scu ssion pe rtain s to both CRT s and L CD di splays. Within a CRT dis play, current wavefo rm s pa ss th rough the coils to p roduce magnetic fields t hat deflect electron be ams to tran sverse the di s play surfa ce in a ra ster pattern, h orizont ally from left to right and ve rtically from top to bottom. As sho wn in Figu re 12, inform ation is only di s played when the beam is m oving in the f orwa rd dire ctionleft to right and to p to bottomand not during the time the beam return s back to the left or top edge of the display. Much of the potential display tim e is the refo re lost in blan king pe riod s when the beam is re set and stabilized to begin a new horizo ntal or vertical display pa ss.

22

Figure 12: CRT Display Timing The size of the beams, t he frequency at which the beam tra ces acro ss the display and the m odulation frequency of electro n beam determine the di splay re solution. M odern VGA di splays support multiple display re solution s, and the VGA co ntroller dictate s the re s olution by producing tim ing signals to con trol the rast er p atterns. The controller prod uce s TTL-level synchronizing pulse s that set the fre quency at which current flows th rough the deflection coils, an d it ensu res t hat pixel or video data i s applied to the electron gun s a t the corre ct time. Video data typically come s f rom a video ref resh memory with one or m ore bytes a ssigned to each pixel location. The controller indexe s into the video data buf fer a s the beams m ove across the di splay. The cont roller then retrieve s and applies video data to the di splay at preci sely the tim e the electron beam is moving across a given pixel. A s shown in Figure 12, the VGA cont roller generates the HS (ho rizontal syn c) a nd VS (vertical sync) tim ings signals and coordinates the delivery of video data on each pixel clock. The pixel clock define s the tim e available to display one pixel of inform ation. The VS signal defines the refre sh fre quency of th e di s play, or the f requen cy at which all information on the display i s redra wn. The m inim um refresh frequen cy i s a function of the di splays pho spho r and elect ron beam intensity, with practical re fre sh f requen cies in the 60 Hz to 120 Hz range. The number of

23

horizontal lines displayed at a given refre sh f requency d efine s the ho rizont al re tra ce frequen cy.

8.2 VGA si gnal TIM ING

The signal timings in Table 20 are de rived fo r a 6 40-pixel by 480 -row di splay u sing a 2 5 M Hz pixel clock and 60 Hz 1 ref re sh. Figu re 13 shows th e relation between each o f the tim ing symbols.

Figure 13: V GA Timing The timing for the sync pul se width (TP W) an d fro nt and back porch interval s (TFP and TBP) are based on o b s e rvations from variou s VGA di splays. The f ront and ba ck porch interval s are the pre- and po st-sync pul se times. Inf orm ation cannot be di splayed du ring the se times. Ta ble 20: V GA signal timing Symbol TS TDISP TPW TFP TBP Parameter Sync pulse time Display time Pulse width Front porch Back porch Vertical Sync Time 16.7 ms 15.36 ms 64 s 320 s 928 s Clocks 416,800 384,000 1,600 8,000 23,200 Lines 521 480 2 10 29 Horizontal Sync Time 32s 25.6 s 3.84 s 640 s 1.92 s Clocks 800 640 96 16 48

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CHAPTER 9
LCD Interface
SPA RTA N-3 de velopm ent board includes t he Orioles Di splay M odule a dot matrix liquid crystal dis play th at displays alphanum eric, Kana (Japane se) cha racters and symbols. Built in controller provide s connectivity between LCD and FPGA. This LCD ha s a built in Dot Matrix controller, with font 5x7 o r 5x10 dots, di splay data RAM for 80 characte rs ( 80 x 8 bit) and a characte r gene rato r ROM which p rovides 160 characters with 5 x7 font and 32 cha racte rs with font of 5x10. All the function s re quired fo r L CD a re p rovided internally. Internal ref re sh i s pro vided by t he Cont roller. The Interface detail s of the LCD di splay are a s shown in figure 1 4.

Figure 14: LCD Interface t o SPARTAN-3 FPGA

25

9.1 Data Lines Connection

LCD ha s 8 bit bidirectional data bu s interfa ce to FPGA. The data bu s interfa ce has a th ree s t ate con st ru ction. When Enable s ignal is at low level, the se data b us terminal remain in high impedance state. Interface detail s of the d ata lines with SPA RTAN-3 FPGA a re a s in Table 21.

Ta ble 21: Data Line Int erfa ce to SPARTAN-3 FP GA Data Bit "DL0_QS" "DL1_QS" "DL2_QS" "DL3_QS" "DL4_QS" "DL5_QS" "DL6_QS" "DL7_QS" FPGA Pin
C27 D27 D28 E27 F28 G27 G28 H27

9.2 Control Line Interface:

The control lines of LCD comprise s of RS, R/W# and E The s ignificance of the above m entioned control signals i s a s follows RS: Regi s te r select s ignal u s ed to select Data registe r or a Com mand/Statu s re gister. High on RS selects the data registe r. Low on RS sele cts the Com mand/Status regi st er. R/W#: Read/Write select cont rol line. High on R/W # selects the read operation Low on R/W # select s t he write ope ration. E: E nable signal used to e nable or di sa ble the data bus. Low on the enable signal puts the data bu s into a high im pedance st ate. High on the e nable signal select s the data bu s.

The control line interface of LCD with FPGA i s a s sho wn in table Table 22: Control Line Interface to SP ARTAN-3 FPGA Control Bit "RS_QS" "E_QS" "R/W_QS" FPGA Pin G17 D26 C25

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CHAPTER 10
10/100 Non PCI Ethernet Interface
SPA RTA N-3 de velopm ent board has a 10 / 100 M bp s Ethernet inte rface u sing LA N 91 C111 from SM SC. The block diagram for the same i s a s shown in figure 10.1. This interfa ce i s de sign ed to fa cilitate the implem entation of fast Ethernet conne ctivity for embedded applications. LA N 91C111 i s a mixed analog/digital device that implements MA C and PHY po rtion of CSM A /CD prot ocol at 10 and 100 Mbps. SMSC LAN 91C111 provides a flexible sla ve interface to industry sta ndard bu s inte rface. Support s 32, 16 and 8 bit bu s ho st interfa ce with synch ronous and asynch ronous data t ransfer m odes. Two differe nt interfa ce s are suppo rted on net work side. The first inte rface is stand ard magnetics tran smit re ceive pair inte rfacing to 10 /100 Ba se T utilizing internal phys ical layer block . Second i s a MII (Media Independent Inte rface) specification standa rd that u se nibble wide data tran sfer. Thi s i s ap plicable for both 10 and 100 M bps speed. Interface detail s fo r the Eth erne t interfa ce are as mentioned belo w.

27

Figure 15: LAN 91C111 Int erface t o SP ARTAN-3 FP GA

10.1 Syst em Address Bus Connection

These consi st of A1-A15, A EN and nB E0 -nBE 3 signals. A1-A15 : Add re ss bu s input. LA N 91C111 use s A 1-A3 to access inte rnal registe rs selection while A4-A15 i s used fo r addre ss decoding for registe r a cce ss. AEN: Ad dre ss e nable signal, active lo w on the se signal s en able s the addre ss d ecoding. nBE0 nBE3: Active lo w byt e valid u sed to define the width of acce ss and regi s te rs being acce ssed . Table 23: Address Bus Interface t o SP ARTAN-3 FPGA Address Bit "LAN_A1" "LAN_A2" "LAN_A3" "LAN_A4" "LAN_A5" "LAN_A6" "LAN_A7" "LAN_A8" "LAN_A9" "LAN_A10" "LAN_A11" "LAN_A12" "LAN_A13" "LAN_A14" "LAN_A15" "LAN_AEN" LAN_nBE0 LAN_nBE1 LAN_nBE2 LAN_nBE3 FPGA Pin
AB30 AB29 AC30 AC29 AD30 AD29 AE29 AF30 AF29 AG30 AG29 V21 T25 W22 W21 AF27 Y21 AA22 AB22 AA21

10.2 Syst em Data Bus Connection

32 bit bidirectional data bu s used to a cce ss t he LAN 91C111 internal registe rs. Data bu s h as an internal wea k pull-up. Ta ble 24: Data Bus Int erface t o SPARTAN-3 FPGA Data Bit "LAN_D0" "LAN_D1" FPGA Pin
W25 W26

28

"LAN_D2" "LAN_D3" Data Bit "LAN_D4" "LAN_D5" "LAN_D6" "LAN_D7" "LAN_D8" "LAN_D9" "LAN_D10" "LAN_D11" "LAN_D12" "LAN_D13" "LAN_D14" "LAN_D15" "LAN_D16" "LAN_D17" "LAN_D18" "LAN_D19" "LAN_D20" "LAN_D21" "LAN_D22" "LAN_D23" "LAN_D24" "LAN_D25" "LAN_D26" "LAN_D27" "LAN_D28" "LAN_D29" "LAN_D30" "LAN_D31"

V25 V26

FPGA Pin
U25 AA19 AA20 AB21 AA29 Y29 Y30 W29 W30 V29 V30 U29 T29 T30 R29 R30 W24 W23 Y24 Y23 AE28 AD27 AD28 AC27 AC28 AB27 AA28 Y27

10.3 Control Signals Connection

Cont rol signals a re broadly catego rized into three typ es Synchron ou s Bu s interface s ignal s As yn chronou s Bus interface signal s M iscellaneou s control signals

29

10.3.1 S ync hronous bus interface signals Following are the synchron ou s bu s interf ace sign als: nCycle : Active low synch ronou s signal u sed to control EI SA bu rs t cycle. nVL Bus: Active lo w signal to enable VL Bus interfa ce. W/nRD : Define s the direction of t he cycle. High enables write cycle s and lo w ena bles read signal s . LCLK : S yn chro nou s b u s clock . M aximum lim it is 50 MHz. During a syn chronou s cycle thi s pin is tied high. nSRDY : Thi s signal i s use d to extend the access in VL Bus interfa ce m ode. Falling edge of this signal indicates t he cycle com pletion nRDYRTN: Input to SM SC LA N 9 1C111 u sed to control com pletion of read cycle. Sam pled on falling edge of LCLK and synchron ous cycles a re delayed until it is sampled high. Ta ble 25: Synchronous Bus Int erface to SPARTAN-3 FPGA Control Bit
LAN_CYCLE" "LAN_nSRD" "LAN_RDYRTN" "W/nR" "\VLBUS\"

FPGA Pin
AH25 V27 W28 AG26 AG28

10.3.2 Asynchronous bus interface signals Following are the a syn chro nou s b u s interface s ig nal s ARDY: Us e d to extend the bu s access in a syn ch ronous bus inte rface. nRD : Active lo w read strob e nWR: A ctive low write st robe. nADS: Add ress A1-A15 and AEN are latched on rising edg e of nADS. Ta ble 26: Asynchronous Bus Interface t o SPARTAN-3 FPGA Control Bit ARDY nRD nWR nADS FPGA Pin
AG27 AG23 AH24 AH27

10.3.3 M iscellaneous Signals : Rese t: When thi s pin is asserte d cont roller pe rfo rms system reset.(M AC + P HY ) INTR: Active high input to interrupt the FP GA. nCS : Out put chip select used to p rovide fo r m apping of P HY fun ctions into LAN 91 C111 decoded space. nLDEV: It i s a combinatorial decode of unlatch ed add re ss and AEN s ignal. IOS0, I OS1, and I OS2 : Select t he predefined EE PROM configu ration. ENEEP: En able s acce ss to external se rial EEPROM.

30

Ta ble 27: M iscella neous Signals Int erfa ce t o SPARTAN-3 FP GA Control Bit LAN_rst LAN_INTR" "LAN_nCS" LAN_nDEV" IOS0 IOS1 IOS2 ENEEP
AH23 AG22 AG24 Y28 Y26 Y25 AA25 AB26

FPGA Pin

For detailed of SMSC L AN91C111 refe r it s datasheet and application note an96.

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CHAPTER 11
Connector Details
SPA RTA N-3 Developm ent Boa rd has provision fo r 3 t ype s connecto rs that can be cate gorize d a s follows :

11.1 IO Connectors
These provide acce ss to f ree I Os on boa rd. IOCON1: 50 pin conne ctor provide s 4 7 fre e IOs. IOCON2: 50 pin conne ctor provide s 4 0 fre e IOs. IOCON3: 50 pin conne ctor provide s 4 0 fre e IOs. IOCON4: 50 pin conne ctor provide s 3 2 fre e IOs. IOCON5:40 pin connector provide s 38 fre e IOs. IOCON6 :40 pin conne ctor provide s 3 2 fre e IOs IOCON7: 40. pin conne cto r provide s 3 2 fre e IOs IOCON8 : 4 0 pin conne cto r provide s 3 2 fre e IOs IOCON9 : 40 pin conne cto r p rovides 32 free IOs Table 28 gives the interf ace det ails of I OCON1 conne cto r to FP GA Table 28: IOCON1 Connect or Interface t o FP GA
Net Name "F_IO303" "F_IO304" "F_IO305" "F_IO306" "F_IO307" "F_IO308" "F_IO309" "F_IO310" "F_IO311" "F_IO312" "F_IO313" "F_IO314" "F_IO315" "F_IO316" "F_IO317" "F_IO318" "F_IO319" "F_IO320" "F_IO321" "F_IO322" "F_IO323" "F_IO324" "F_IO325" "F_IO326" FPGA Pin NO C10 D11 B5 A5 B6 B7 A7 B8 A8 B9 A9 B10 B11 A11 B12 A12 B13 A13 B14 B15 A15 A16 B16 B17 Connector Details #IOCON1 - 1 #IOCON1 - 2 #IOCON1 - 3 #IOCON1 - 4 #IOCON1 - 5 #IOCON1 - 6 #IOCON1 - 7 #IOCON1 - 8 #IOCON1 - 11 #IOCON1 - 12 #IOCON1 - 13 #IOCON1 - 14 #IOCON1 - 15 #IOCON1 - 16 #IOCON1 - 17 #IOCON1 - 18 #IOCON1 - 21 #IOCON1 - 22 #IOCON1 - 23 #IOCON1 - 24 #IOCON1 - 25 #IOCON1 - 26 #IOCON1 - 27 #IOCON1 - 28 Net Name "F_IO327" "F_IO328" "F_IO329" "F_IO330" "F_IO331" "F_IO332" "F_IO333" "F_IO334" "F_IO335" "F_IO336" "F_IO337" "F_IO338" "F_IO339" "F_IO340" "F_IO332" "F_IO333" "F_IO334" "F_IO335" "F_IO336" "F_IO337" "F_IO338" "F_IO339" "F_IO340" FPGA Pin NO A18 B18 A19 B19 A20 B20 B21 A22 B22 A23 B23 A24 B24 D24 B20 B21 A22 B22 A23 B23 A24 B24 D24 Connector Details #IOCON1 - 31 #IOCON1 - 32 #IOCON1 - 33 #IOCON1 - 34 #IOCON1 - 35 #IOCON1 - 36 #IOCON1 - 37 #IOCON1 - 38 #IOCON1 - 41 #IOCON1 - 42 #IOCON1 - 43 #IOCON1 - 44 #IOCON1 - 45 #IOCON1 - 46 #IOCON1 - 36 #IOCON1 - 37 #IOCON1 - 38 #IOCON1 - 41 #IOCON1 - 42 #IOCON1 - 43 #IOCON1 - 44 #IOCON1 - 45 #IOCON1 - 46

32

Table 29 gives the interf ace det ails of I OCON2 conne cto r to FP GA Table 29: IOCON2 Connect or Interface t o FP GA
Net Name "F_IO255" "F_IO256" "F_IO257" "F_IO258" "F_IO259" "F_IO260" "F_IO261" "F_IO262" "F_IO263" "F_IO264" "F_IO265" "F_IO266" "F_IO267" "F_IO268" "F_IO269" "F_IO270" "F_IO271" "F_IO272" "F_IO273" "F_IO274" FPGA Pin F7 F8 E8 F9 E9 F10 F11 E11 F12 E12 F13 E13 F14 F15 E15 E16 F16 F17 E18 F18 Connector Details #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 1 2 3 4 5 6 Net Name "F_IO275" "F_IO276" "F_IO277" "F_IO278" "F_IO279" "F_IO280" "F_IO281" "F_IO282" "F_IO283" "F_IO284" "F_IO285" "F_IO286" "F_IO287" "F_IO288" "F_IO289" "F_IO290" "F_IO291" "F_IO292" "F_IO293" "F_IO294" FPGA Pin E19 F19 E20 F20 F21 E22 F22 E23 K11 K12 H11 G11 H12 G12 H13 G14 H15 G15 G16 H16 Connector Details #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 #IOCON2 25 26 27 28 31 32 33 34 35 36 37 38 41 42 43 44 45 46 47 48

- 7 - 8 - 11 - 12 - 13 14 15 16 17 18 21 22 23 24

Table 30 gives the interf ace det ails of I OCON3 conne cto r to FP GA Table 30: IOCON3 Connect or Interface t o FP GA
Net Name "F_IO207" "F_IO208" "F_IO209" "F_IO210" "F_IO211" "F_IO212" "F_IO213" "F_IO214" "F_IO215" "F_IO216" "F_IO217" "F_IO218" "F_IO219" "F_IO220" "F_IO221" "F_IO222" "F_IO223" "F_IO224" FPGA Pin C4 D5 C6 J9 J10 D7 C7 D8 C8 D9 C11 D12 C12 D13 C14 D15 C15 C16 Connector Pin #IOCON3 - 1 #IOCON3 - 2 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 3 4 5 6 7 8 11 12 13 14 15 16 17 18 21 22 Net Name "F_IO227" "F_IO228" "F_IO229" "F_IO230" "F_IO231" "F_IO232" "F_IO233" "F_IO234" "F_IO235" "F_IO236" "F_IO237" "F_IO238" "F_IO239" "F_IO240" "F_IO241" "F_IO242" "F_IO243" "F_IO244" FPGA Pin D18 C19 D19 C20 AD24 D20 C21 D22 C23 D23 C24 J12 K13 AC24 K14 J14 K15 J15 Connector Pin #IOCON3 - 25 #IOCON3 - 26 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 #IOCON3 27 28 31 32 33 34 35 36 37 38 41 42 43 44 45 46

33

Net Name "F_IO225" "F_IO226"

FPGA Pin D16 C17

Connector Pin #IOCON3 - 23 #IOCON3 - 24

Net Name "F_IO245" "F_IO246"

FPGA Pin J16 K16

Connector Pin #IOCON3 - 47 #IOCON3 - 48

Table 31 gives the interf ace det ails of I OCON4 conne cto r to FP GA Table 31: IOCON4 Connect or Interface t o FP GA
Net Name "F_IO1" "F_IO2" "F_IO3" "F_IO4" "F_IO5" "F_IO6" "F_IO7" "F_IO8" "F_IO9" "F_IO10" "F_IO11" "F_IO12" "F_IO13" "F_IO14" "F_IO15" "F_IO16" "F_IO17" "F_IO18" "F_IO19" "F_IO20" FPGA Pin AD10 AC11 AD11 AC12 AD12 AC13 AD14 AC15 AB9 AB10 AC16 AC18 AD19 AC19 AD20 AC20 AD21 AC22 AD23 AC23 Connector Pin #IOCON4 - 1 #IOCON4 - 2 #IOCON4 - 3 #IOCON4 - 4 #IOCON4 - 5 #IOCON4 - 6 #IOCON4 - 7 #IOCON4 - 8 #IOCON4 - 11 #IOCON4 - 12 #IOCON4 - 13 #IOCON4 - 14 #IOCON4 - 15 #IOCON4 - 16 #IOCON4 - 17 #IOCON4 - 18 #IOCON4 - 21 #IOCON4 - 22 #IOCON4 - 23 #IOCON4 - 24 Net Name "F_IO21" "F_IO22" "F_IO23" "F_IO24" "F_IO25" "F_IO26" "F_IO27" "F_IO28" "F_IO29" "F_IO30" "F_IO31" "F_IO32" "F_IO33" "F_IO34" "F_IO35" "F_IO36" "F_IO37" "F_IO38" "F_IO39" FPGA Pin AF22 J13 AB23 AA24 AA11 AA12 AB12 AA13 AB13 AA15 AB15 AA16 AB16 AB17 AA17 AB18 AA18 AB19 AD10 Connector Pin #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 #IOCON4 25 26 27 28 31 32 33 34 35 36 37 38 41 42 43 44 45 46 47

Table 32 gives the interf ace det ails of I OCON5 conne cto r to FP GA Table 32 IOCON5 Connector Int erface to FP GA
Net Name "F_IO49" "F_IO50" "F_IO51" "F_IO52" "F_IO53" "F_IO54" "F_IO55" "F_IO56" "F_IO57" "F_IO58" "F_IO59" "F_IO60" "F_IO61" "F_IO62" "F_IO63" FPGA Pin AE10 AE11 AF11 AE12 AF12 AE13 AF13 AE14 AE15 AF15 AF16 AE16 AE17 AF18 AE18 Connector Pin #IOCON5- 1 #IOCON5- 2 #IOCON5#IOCON5#IOCON5#IOCON5#IOCON53 4 5 6 7 Net Name "F_IO65" "F_IO66" "F_IO67" "F_IO68" "F_IO69" "F_IO70" "F_IO71" "F_IO72" "F_IO73" "F_IO74" "F_IO75" "F_IO76" "F_IO77" "F_IO78" "F_IO79" FPGA Pin AE19 AF20 AE20 AE21 AE22 AF23 AE23 AE24 AF25 AE25 AE26 AD25 AC25 AC26 AK24 Connector Pin #IOCON5- 21 #IOCON5- 22 #IOCON5#IOCON5#IOCON5#IOCON5#IOCON5#IOCON5#IOCON5#IOCON5#IOCON5#IOCON5#IOCON523 24 25 26 27 28 31 32 33 34 35

#IOCON5- 8 #IOCON5- 11 #IOCON5- 12 #IOCON5- 13 #IOCON5- 14 #IOCON5- 15 #IOCON5- 16 #IOCON5- 17

#IOCON5- 36 #IOCON5- 37

34

"F_IO64"

AF19

#IOCON5- 18

"F_IO80"

AJ23

#IOCON5- 38

Table 33 gives the interf ace det ails of I OCON6 conne cto r to FP GA Table 33: IOCON6 Connect or Interface t o FP GA
Net Name "F_IO113" "F_IO114" "F_IO115" "F_IO116" "F_IO117" "F_IO118" "F_IO119" "F_IO120" "F_IO121" "F_IO122" "F_IO123" "F_IO124" "F_IO125" "F_IO126" "F_IO127" "F_IO128" FPGA Pin AB14 AA14 AB25 AK28 AJ26 AK26 AJ25 AJ24 AK23 AJ22 AK22 AJ21 AJ20 AK20 AJ19 AK19 Connector Details #IOCON6- 38 #IOCON6- 37 #IOCON6- 36 #IOCON6- 35 #IOCON6- 34 #IOCON6- 33 #IOCON6- 32 #IOCON6- 31 #IOCON6- 28 #IOCON6- 27 #IOCON6- 26 #IOCON6- 25 #IOCON6#IOCON6#IOCON6#IOCON624 23 22 21 Net Name "F_IO129" "F_IO130" "F_IO131" "F_IO132" "F_IO133" "F_IO134" "F_IO135" "F_IO136" "F_IO137" "F_IO138" "F_IO139" "F_IO140" "F_IO141" "F_IO142" "F_IO143" "F_IO144" FPGA Pin AJ18 AK18 AJ17 AJ16 AK16 AK15 AJ14 AK13 AJ13 AD16 AD15 AK12 AE8 AE7 AF6 AE6 Connector Details #IOCON6- 18 #IOCON6- 17 #IOCON6- 16 #IOCON6- 15 #IOCON6- 14 #IOCON6- 13 #IOCON6- 12 #IOCON6- 11 #IOCON6- 8 #IOCON6- 7 #IOCON6- 6 #IOCON6- 5 #IOCON6#IOCON6#IOCON6#IOCON64 3 2 1

Table 34 gives the interf ace det ails of I OCON7 conne cto r to FP GA. I Os on connector I OCON3 are al s o mapped to MICTOR connecto r (J10 ) for interface of Logic Analyze r. This conn ector provide s 34 I Os for interface. Table 34: IOCON7 Connect or Interface t o FP GA
Net Name "MICTOR1" "MICTOR2" "MICTOR3" "MICTOR4" "MICTOR5" "MICTOR6" "MICTOR7" "MICTOR8" "MICTOR9" "MICTOR10" "MICTOR11" "MICTOR12" "MICTOR13" "MICTOR14" "MICTOR15" "MICTOR16" FPGA Pin G1 H2 G2 H1 F2 J2 E1 J1 E2 K2 D1 L2 D2 H8 G8 G7 Connector Pin #IOCON7- 8 #IOCON7- 11 #IOCON7- 7 #IOCON7- 12 #IOCON7- 6 #IOCON7- 13 #IOCON7- 5 #IOCON7- 14 #IOCON7- 4 #IOCON7- 15 #IOCON7- 3 #IOCON7- 16 #IOCON7- 2 #IOCON7- 17 #IOCON7- 1 #IOCON7- 18 Net Name "MICTOR18" "MICTOR20" "MICTOR21" "MICTOR22" "MICTOR23" "MICTOR24" "MICTOR25" "MICTOR26" "MICTOR27" "MICTOR28" "MICTOR29" "MICTOR30" "MICTOR31" "MICTOR32" "MICTOR33" "MICTOR34" FPGA Pin L1 M2 AF8 M1 AG2 N2 W1 N1 V2 P2 V1 R2 T2 R1 U2 T1 Connector Pin #IOCON7- 21 #IOCON7- 22 #IOCON7- 38 #IOCON7#IOCON7#IOCON7#IOCON7#IOCON7#IOCON7#IOCON7#IOCON7#IOCON7#IOCON7#IOCON723 37 24 36 25 35 26 34 27 32 28

#IOCON7- 33 #IOCON7- 31

35

Table 35 gives the interf ace det ails of I OCON8 conne cto r to FP GA Table 35: IOCON8 Connect or Interface t o FP GA
Net Name "F_IO177" "F_IO178" "F_IO179" "F_IO180" "F_IO181" "F_IO182" "F_IO183" "F_IO184" "F_IO185" "F_IO186" "F_IO187" "F_IO188" "F_IO189" "F_IO190" "F_IO191" "F_IO192" FPGA Pin D4 D3 E4 F3 L10 M10 M9 N10 N9 P10 P9 R10 R9 T9 T10 U9 Connector Pin #IOCON8- 1 #IOCON8- 2 #IOCON8- 3 #IOCON8- 4 #IOCON8- 5 #IOCON8- 6 #IOCON8- 7 #IOCON8- 8 #IOCON8- 11 #IOCON8- 12 #IOCON8- 13 #IOCON8- 14 #IOCON8- 15 #IOCON8- 16 #IOCON8- 17 #IOCON8- 18 Net Name "F_IO193" "F_IO194" "F_IO195" "F_IO196" "F_IO197" "F_IO198" "F_IO199" "F_IO200" "F_IO201" "F_IO202" "F_IO203" "F_IO204" "F_IO205" "F_IO206" "MICTOR17" "MICTOR19" FPGA Pin U10 V9 V10 W9 W10 Y10 AA9 AA10 W2 Y1 Y2 AA2 AB1 AB2 AG1 AC1 Connector Pin #IOCON8- 21 #IOCON8- 22 #IOCON8- 23 #IOCON8- 24 #IOCON8- 25 #IOCON8- 26 #IOCON8- 27 #IOCON8- 28 #IOCON8- 31 #IOCON8- 32 #IOCON8- 33 #IOCON8- 34 #IOCON8- 35 #IOCON8- 36 #IOCON8- 38 #IOCON8- 37

Table 36 gives the interf ace det ails of I OCON9 conne cto r to FP GA Table 36: IOCON9 Connect or Interface t o FP GA
Net Name "F_IO145" "F_IO146" "F_IO147" "F_IO148" "F_IO149" "F_IO150" "F_IO151" "F_IO152" "F_IO153" "F_IO154" "F_IO155" "F_IO156" "F_IO157" "F_IO158" "F_IO159" "F_IO160" FPGA Pin AF2 AF1 AE2 AD2 AD1 AC2 AC4 AC3 AB4 AA3 Y4 Y3 W4 W3 V4 U3 Connector Pin #IOCON9 37 #IOCON9 38 #IOCON9 35 #IOCON9 36 #IOCON9 33 #IOCON9 34 #IOCON9 31 #IOCON9 32 #IOCON9 27 #IOCON9 28 #IOCON9 25 #IOCON9 26 #IOCON9 23 #IOCON9 24 #IOCON9 21 #IOCON9 22 Net Name "F_IO161" "F_IO162" "F_IO163" "F_IO164" "F_IO165" "F_IO166" "F_IO167" "F_IO168" "F_IO169" "F_IO170" "F_IO171" "F_IO172" "F_IO173" "F_IO174" "F_IO175" "F_IO176" FPGA Pin T4 T3 R3 R4 P3 N4 M3 M4 L3 L4 K3 J4 H3 H4 G3 G4 Connector Pin #IOCON9 17 #IOCON9 18 #IOCON9 15 #IOCON9 16 #IOCON9 13 #IOCON9 14 #IOCON9 11 #IOCON9 12 #IOCON9 7 #IOCON9 8 #IOCON9 5 #IOCON9 6 #IOCON9 3 #IOCON9 4 #IOCON9 1 #IOCON9 2

11.2 Stackable Connector

Two stackable connecto rs J1 and J2 a re p rovided on board for the interface of ADD ON daughter board s (optional) provided along with the SPARTA N-3 De velopment board. Table 37 gives the interf ace det ails of Stackable conn ecto r to FP GA. Ta ble 37: Stackable Connector Int erface to FP GA
Net Name "STEC_IO0" "STEC_IO2" FPGA Pin K18 H19 Connector Details #J1 - 2 #J1 - 4 Net Name "STEC_IO23" "STEC_IO24" FPGA Pin G25 L26 Connector Details #J1 - 27 #J1 - 32

36

Net Name "STEC_IO1" "STEC_IO3" "STEC_IO4" "STEC_IO5" "STEC_IO6" "STEC_IO7" "STEC_IO8" "STEC_IO9" "STEC_IO10" "STEC_IO11" "STEC_IO12" "STEC_IO13" "STEC_IO14" "STEC_IO15" "STEC_IO16" "STEC_IO17" "STEC_IO18" "STEC_IO19" "STEC_IO20" "STEC_IO21" "STEC_IO22" "STEC_IO46" "STEC_IO47" "STEC_IO48" "STEC_IO49" "STEC_IO50" "STEC_IO51" "STEC_IO52" "STEC_IO53" "STEC_IO54" "STEC_IO55" "STEC_IO56" "STEC_IO57" "STEC_IO58" "STEC_IO59" "STEC_IO60" "STEC_IO61" "STEC_IO62" "STEC_IO63" "STEC_IO64" "STEC_IO65" "STEC_IO66" "STEC_IO67"

FPGA Pin J19 G20 K19 H20 K20 G21 J21 H22 G24 G23 H23 F23 H24 F24 J25 E25 J26 F25 K25 F26 L25 V22 P22 U21 P21 U22 N22 T21 N21 T22 M22 R22 M21 R21 L21 V23 K22 U24 K21 T23 J22 T24 N23

Connector Details #J1 - 1 #J1 - 3 #J1 - 6 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 - 5 - 8 - 7 - 12 - 11 14 13 16 15 18 17 22 21 24 23 26

Net Name "STEC_IO25" "STEC_IO26" "STEC_IO27" "STEC_IO28" "STEC_IO29" "STEC_IO30" "STEC_IO31" "STEC_IO32" "STEC_IO33" "STEC_IO34" "STEC_IO35" "STEC_IO36" "STEC_IO37" "STEC_IO38" "STEC_IO39" "STEC_IO40" "STEC_IO41" "STEC_IO42" "STEC_IO43" "STEC_IO44" "STEC_IO45" "STEC_IO68" "STEC_IO69" "STEC_IO70" "STEC_IO71" "STEC_IO72" "STEC_IO73" "STEC_IO74" "STEC_IO75" "STEC_IO76" "STEC_IO77" "STEC_IO78" "STEC_IO79" "STEC_IO80" "STEC_IO81" "STEC_IO82" "STEC_IO83" "STEC_IO84" "STEC_IO85" "STEC_IO86" "STEC_IO87" "STEC_IO88" "STEC_IO89"

FPGA Pin H25 M25 H26 M26 G29 G30 F29 H29 E30 H30 E29 J29 D30 J30 D29 K29 B26 L29 A26 L30 B25 R24 M24 R23 M23 P24 L24 T26 L23 R26 K24 R25 J23 U28 P25 T27 N26 P29 N25 N29 M29 N30 M30

Connector Details #J1 - 31 #J1 - 34 #J1 - 33 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J1 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 #J2 36 35 38 37 40 39 42 41 44 43 46 45 48 47 50 49 52 51 28 27 32 31 34 33 36 35 38 37 42 41 44 43 46 45 48 47 52

- 25 - 28 - 2 - 1 - 4 3 6 5 8 7 12 11 14 13 16 15 18 17 22 21 24

#J2 - 23 #J2 - 26 #J2 - 25

#J2 - 51 #J2 - 54 #J2 - 53

The positional details of the se conn ectors on development board i s as sho wn in figure 16

37

Figure 16: Positiona l Details of On Board Connect ors

38

CHAPTER 12
Clock and Reset Sources
The SPA RTAN-3 Developm ent board ha s a dedicate d 40 M Hz o scillator source and an optional socket fo r another clock oscillator sou rce. This dedicated clock source ca n be u sed to de rive other f requen cie s using DCM (digital clock m angers) available in SPA RTA N-3 FP GA. Another clock o scillator can be mounted on 8 pin DI P So cket wh ose fo otprint i s compatible with os cillators upto 200 MHz. SPA RTA N-3 de velopm ent board has a on board reset ci rcuitry (a ke y switch ) th at i s u sed to re s et (a ctive high) the hard wa re p resent on the board. Board also provide s fa cility for ext ernal clo ck which i s selected b y connecting jumper JP1 The interface de tails of clock and reset with FPGA i s given in Table 31. Ta ble 38: IO Clock-Reset Int erfa ce to FP GA Control Bit Clock Clock1 Reset External Clock
AJ15 AH15 AH21 B15

FPGA Pin

39

CHAPTER 13
SPA RTA N-3 Configuration Details
SPA RTA N-3 de velopm ent board support s two configuration modes as stated belo w Bounda ry S can mode M aster Serial M ode

13.1 Boundary Scan mode:

In boundary scan m ode of configuration the SPA RTA N-3 FP GA i s directly configured via a JTAG po rt u sing the dedicated configu ration pins TCK, TMS, TDI and TDO. The jum per setting for selection of bounda ry scan mode is di s cu ssed in jum per s et ting s ection (section 12.3 ).

13.2 Mas t er Serial M ode

In m as te r serial mode the SPA RTA N-3 i s configured t hrough a FLAS H PROM. In M as te r Se rial mode, the FP GA automatically load s the configuration bit st ream in bit-s e rial form from configuration fla sh synch ronized b y the configuration clock (CCL K) generated by the FPGA. Upon po wer-up o r reconfiguration, the FP GA's mode select pins are used to select the M aste r Se rial configuration mode. Master Serial M ode provide s a s im ple configuration interface. Only a serial data line, a clock line, and two control lines (I NIT and DONE) are required t o configu re an FP GA. Dat a from the PROM is read out seque ntially on a single data line (DI N), acce ssed via the P ROM 's inte rnal address count er which is incremented on eve ry valid rising edge of CCLK. The se rial Bitst ream data must be s et up at the FPGAs DI N input pin a s ho rt time before each ri sing edge of the FP GA's internally generated CCLK signal. The jum per setting for selection of Ma ster Se rial Mode is discussed in jumper setting section (section 12.3 ).

13.3 Jumper Setting

M ode Selection Jumpers: M0, M 1, M 2 are the m ode selection jum pers used to select the configuration mode either Bounda ry Scan or M aster Serial M ode. Ta ble 39: M ode Selection Jumper Settings Configura tion Mode MODE0 (M 0) MODE1 (M 1) MODE2 (M 2) 1 z z z 2 z z z Connecting 1-2 select s Logic 0, Disconnecting 1 -2 selects L ogic- 1

Ta ble 40: Mode Selection Table Confi guration M ode Boundary Scan Mode Master Serial M ode MODE0 1 0 M ODE1 0 0 MODE2 1 0

40

J TAG Chai n Se lecti on Jumpe r: JP2 jum per i s u sed to select the JTAG chain for configuration. W hen jum per is conn ected bet ween 2 -3, then PROM and FP GA both get added in the JTA G Chain where a s conne cting jumper between 1-2 brings only FP GA in Chain.

Figure 17: JTAG Mode Selection

41

13.4 JTAG Hea der: An on board JT AG connector is pro vided for configu ring the FPGA through pa rallel port of PC via a parallel III cable. The details of thi s connecto r are a s shown in figure 1 8.

Figure 18: JTAG Connect or Deta ils

42

CHAPTER 14
Power Supplies
SPA RTA N-3 Developm ent boa rd i s p rovided with a regulated po we r s u pply of + 5V DC output. This supply i s u sed to gene rate th e re quired on b oard supply voltage s . Output of th e re gulated po wer supply i s given to powe r connector present on board. The power LED (Red L ED) lights up when po we r i s p rope rly applied to the boa rd.

14.1 Voltage Regulator s

The lis t of va riou s voltage regulators p resent on boa rd a re a s given in Table 34. Ta ble 41: Power Supply Details Voltage + 5 V DC + 3.3 V DC +2.5 V DC +1.8 V DC +1.2 V DC -5V DC Source Gene rated f rom exte rnal power supply pro vided along with the d evelopment Board. A regulated 3.3 V DC supply i s generated on boa rd u sing a DC-DC converte r PTH0501 0W with input voltage of 5 Volts A regulated 2.5 V DC supply i s generated onboa rd u sing a linear lo w d rop out regulator LT1963 with input voltage of 3.3 Volts A regulated 1.8 V DC supply i s generated onboa rd u sing a linear lo w d rop out regulator LT1963 with input voltage of 3.3 Volt s A regulated 1.2 V DC supply i s generated on boa rd u sing a DC-DC converte r PTH0501 0W with input voltage of 5 Volts A negative supply i s generated on boa rd u s ing a inverting charge pump M AX1673 with input voltage of 5 Volt s

Ove rall, the 5V DC switching powe r adapter powers the b oard. a 3.3V regulato r, po we red by the 5V DC supply, p rovide s po we r to th e input s of th e 2.5V and 1.2V regulators. Similarly, the 3.3V regulator fee ds all the V CCO voltage supply input s to the FPGAs I/O banks and powers mo st of the component s o n the board. The 2.5V re gulator supplie s po we r to the FPGAs VCCA UX supply input s . The FPGA configuration interface o n the boa rd i s po wered by 3.3V. Con sequently, the 2.5V supply has a cu rrent shunt resi sto r to pre vent reverse current. Finally, a 1.2V regulator supplies powe r to the FP GA s VCCI NT voltage inputs, which p ower t he FPGAs core logic.

43

APPENDIX A
Consolidated UCF For The Complete Board

Clock And Reset

net net net net "CLOCK" "CLOCK1" "RESET" LOC = LOC = LOC = LOC = AJ15 AH15 AH21 B15

External Clock

Free IOs
net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net "F_IO1_QS" "F_IO2_QS" "F_IO3_QS" "F_IO4_QS" "F_IO5_QS" "F_IO6_QS" "F_IO7_QS" "F_IO8_QS" "F_IO9_QS" "F_IO10_QS" "F_IO11_QS" "F_IO12_QS" "F_IO13_QS" "F_IO14_QS" "F_IO15_QS" "F_IO16_QS" "F_IO17_QS" "F_IO18_QS" "F_IO19_QS" "F_IO20_QS" "F_IO21_QS" "F_IO23_QS" "F_IO24_QS" "F_IO25_QS" "F_IO26_QS" "F_IO27_QS" "F_IO28_QS" "F_IO29_QS" "F_IO30_QS" "F_IO31_QS" "F_IO32_QS" "F_IO33_QS" "F_IO34_QS" "F_IO35_QS" "F_IO36_QS" LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = AD10 AC11 AD11 AC12 AD12 AC13 AD14 AC15 AB9 AB10 AC16 AC18 AD19 AC19 AD20 AC20 AD21 AC22 AD23 AC23 AF22 J13 AB23 AA24 AA11 AA12 AB12 AA13 AB13 AA15 AB15 AA16 AB16 AB17 AA17

44

net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net

"F_IO37_QS" "F_IO38_QS" "F_IO39_QS" "F_IO49_QS" "F_IO50_QS" "F_IO51_QS" "F_IO52_QS" "F_IO53_QS" "F_IO54_QS" "F_IO55_QS" "F_IO56_QS" "F_IO57_QS" "F_IO58_QS" "F_IO59_QS" "F_IO60_QS" "F_IO61_QS" "F_IO62_QS" "F_IO63_QS" "F_IO64_QS" "F_IO65_QS" "F_IO66_QS" "F_IO67_QS" "F_IO68_QS" "F_IO69_QS" "F_IO70_QS" "F_IO71_QS" "F_IO72_QS" "F_IO73_QS" "F_IO74_QS" "F_IO75_QS" "F_IO76_QS" "F_IO77_QS" "F_IO78_QS" "F_IO79_QS" "F_IO80_QS" "F_IO113_QS" "F_IO114_QS" "F_IO115_QS" "F_IO116_QS" "F_IO117_QS" "F_IO118_QS" "F_IO119_QS" "F_IO120_QS" "F_IO121_QS" "F_IO122_QS" "F_IO123_QS" "F_IO124_QS" "F_IO125_QS"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

AB18 AA18 AB19 AE10 AE11 AF11 AE12 AF12 AE13 AF13 AE14 AE15 AF15 AF16 AE16 AE17 AF18 AE18 AF19 AE19 AF20 AE20 AE21 AE22 AF23 AE23 AE24 AF25 AE25 AE26 AD25 AC25 AC26 AK24 AJ23 AB14 AA14 AB25 AK28 AJ26 AK26 AJ25 AJ24 AK23 AJ22 AK22 AJ21 AJ20

45

net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net

"F_IO126_QS" "F_IO127_QS" "F_IO128_QS" "F_IO129_QS" "F_IO130_QS" "F_IO131_QS" "F_IO132_QS" "F_IO133_QS" "F_IO134_QS" "F_IO135_QS" "F_IO136_QS" "F_IO137_QS" "F_IO138_QS" "F_IO139_QS" "F_IO140_QS" "F_IO141_QS" "F_IO142_QS" "F_IO143_QS" "F_IO144_QS" "F_IO145_QS" "F_IO146_QS" "F_IO147_QS" "F_IO148_QS" "F_IO149_QS" "F_IO150_QS" "F_IO151_QS" "F_IO152_QS" "F_IO153_QS" "F_IO154_QS" "F_IO155_QS" "F_IO156_QS" "F_IO157_QS" "F_IO158_QS" "F_IO159_QS" "F_IO160_QS" "F_IO161_QS" "F_IO162_QS" "F_IO163_QS" "F_IO164_QS" "F_IO165_QS" "F_IO166_QS" "F_IO167_QS" "F_IO168_QS" "F_IO169_QS" "F_IO170_QS" "F_IO171_QS" "F_IO172_QS" "F_IO173_QS"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

AK20 AJ19 AK19 AJ18 AK18 AJ17 AJ16 AK16 AK15 AJ14 AK13 AJ13 AD16 AD15 AK12 AE8 AE7 AF6 AE6 AF2 AF1 AE2 AD2 AD1 AC2 AC4 AC3 AB4 AA3 Y4 Y3 W4 W3 V4 U3 T4 T3 R3 R4 P3 N4 M3 M4 L3 L4 K3 J4 H3

46

net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net

"F_IO174_QS" "F_IO175_QS" "F_IO176_QS" "F_IO177_QS" "F_IO178_QS" "F_IO179_QS" "F_IO180_QS" "F_IO181_QS" "F_IO182_QS" "F_IO183_QS" "F_IO184_QS" "F_IO185_QS" "F_IO186_QS" "F_IO187_QS" "F_IO188_QS" "F_IO189_QS" "F_IO190_QS" "F_IO191_QS" "F_IO192_QS" "F_IO193_QS" "F_IO194_QS" "F_IO195_QS" "F_IO196_QS" "F_IO197_QS" "F_IO198_QS" "F_IO199_QS" "F_IO200_QS" "F_IO201_QS" "F_IO202_QS" "F_IO203_QS" "F_IO204_QS" "F_IO205_QS" "F_IO206_QS" "F_IO207_QS" "F_IO208_QS" "F_IO209_QS" "F_IO210_QS" "F_IO211_QS" "F_IO212_QS" "F_IO213_QS" "F_IO214_QS" "F_IO215_QS" "F_IO216_QS" "F_IO217_QS" "F_IO218_QS" "F_IO219_QS" "F_IO220_QS" "F_IO221_QS"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

H4 G3 G4 D4 D3 E4 F3 L10 M10 M9 N10 N9 P10 P9 R10 R9 T9 T10 U9 U10 V9 V10 W9 W10 Y10 AA9 AA10 W2 Y1 Y2 AA2 AB1 AB2 C4 D5 C6 J9 J10 D7 C7 D8 C8 D9 C11 D12 C12 D13 C14

47

net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net

"F_IO222_QS" "F_IO223_QS" "F_IO224_QS" "F_IO225_QS" "F_IO226_QS" "F_IO227_QS" "F_IO228_QS" "F_IO229_QS" "F_IO230_QS" "F_IO231_QS" "F_IO232_QS" "F_IO233_QS" "F_IO234_QS" "F_IO235_QS" "F_IO236_QS" "F_IO237_QS" "F_IO238_QS" "F_IO239_QS" "F_IO240_QS" "F_IO241_QS" "F_IO242_QS" "F_IO243_QS" "F_IO244_QS" "F_IO245_QS" "F_IO246_QS" "F_IO255_QS" "F_IO256_QS" "F_IO257_QS" "F_IO258_QS" "F_IO259_QS" "F_IO260_QS" "F_IO261_QS" "F_IO262_QS" "F_IO263_QS" "F_IO264_QS" "F_IO265_QS" "F_IO266_QS" "F_IO267_QS" "F_IO268_QS" "F_IO269_QS" "F_IO270_QS" "F_IO271_QS" "F_IO272_QS" "F_IO273_QS" "F_IO274_QS" "F_IO275_QS" "F_IO276_QS" "F_IO277_QS"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

D15 C15 C16 D16 C17 D18 C19 D19 C20 AD24 D20 C21 D22 C23 D23 C24 J12 K13 AC24 K14 J14 K15 J15 J16 K16 F7 F8 E8 F9 E9 F10 F11 E11 F12 E12 F13 E13 F14 F15 E15 E16 F16 F17 E18 F18 E19 F19 E20

48

net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net

"F_IO278_QS" "F_IO279_QS" "F_IO280_QS" "F_IO281_QS" "F_IO282_QS" "F_IO283_QS" "F_IO284_QS" "F_IO285_QS" "F_IO286_QS" "F_IO287_QS" "F_IO288_QS" "F_IO289_QS" "F_IO290_QS" "F_IO291_QS" "F_IO292_QS" "F_IO293_QS" "F_IO294_QS" "F_IO303_QS" "F_IO304_QS" "F_IO305_QS" "F_IO306_QS" "F_IO307_QS" "F_IO308_QS" "F_IO309_QS" "F_IO310_QS" "F_IO311_QS" "F_IO312_QS" "F_IO313_QS" "F_IO314_QS" "F_IO315_QS" "F_IO316_QS" "F_IO317_QS" "F_IO318_QS" "F_IO319_QS" "F_IO320_QS" "F_IO321_QS" "F_IO322_QS" "F_IO323_QS" "F_IO324_QS" "F_IO325_QS" "F_IO326_QS" "F_IO327_QS" "F_IO328_QS" "F_IO329_QS" "F_IO330_QS" "F_IO331_QS" "F_IO332_QS" "F_IO333_QS"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

F20 F21 E22 F22 E23 K11 K12 H11 G11 H12 G12 H13 G14 H15 G15 G16 H16 C10 D11 B5 A5 B6 B7 A7 B8 A8 B9 A9 B10 B11 A11 B12 A12 B13 A13 B14 B15 A15 A16 B16 B17 A18 B18 A19 B19 A20 B20 B21

49

net net net net net net net

"F_IO334_QS" "F_IO335_QS" "F_IO336_QS" "F_IO337_QS" "F_IO338_QS" "F_IO339_QS" "F_IO340_QS"

LOC LOC LOC LOC LOC LOC

= = = = = =

A22 B22 A23 B23 A24 B24 D24

LOC =

M ICTOR Connector
net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net "MICTOR1_QS" "MICTOR2_QS" "MICTOR3_QS" "MICTOR4_QS" "MICTOR5_QS" "MICTOR6_QS" "MICTOR7_QS" "MICTOR8_QS" "MICTOR9_QS" "MICTOR10_QS" "MICTOR11_QS" "MICTOR12_QS" "MICTOR13_QS" "MICTOR14_QS" "MICTOR15_QS" "MICTOR16_QS" "MICTOR17_QS" "MICTOR18_QS" "MICTOR19_QS" "MICTOR20_QS" "MICTOR21_QS" "MICTOR22_QS" "MICTOR23_QS" "MICTOR24_QS" "MICTOR25_QS" "MICTOR26_QS" "MICTOR27_QS" "MICTOR28_QS" "MICTOR29_QS" "MICTOR30_QS" "MICTOR31_QS" "MICTOR32_QS" "MICTOR33_QS" "MICTOR34_QS" LOC = LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = G1 H2 G2 H1 F2 J2 E1 J1 E2 K2 D1 L2 D2 H8 G8 G7 AG1 L1 AC1 M2 AF8 M1 AG2 N2 W1 N1 V2 P2 V1 R2 T2 R1 U2 T1

Stackable Connector
net net net net "STEC_IO0" "STEC_IO1" "STEC_IO2" "STEC_IO3" LOC LOC LOC LOC = = = = K18 H19 J19 G20

50

net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net

"STEC_IO4" "STEC_IO5" "STEC_IO6" "STEC_IO7" "STEC_IO8" "STEC_IO9" "STEC_IO10" "STEC_IO11" "STEC_IO12" "STEC_IO13" "STEC_IO14" "STEC_IO15" "STEC_IO16" "STEC_IO17" "STEC_IO18" "STEC_IO19" "STEC_IO20" "STEC_IO21" "STEC_IO22" "STEC_IO23" "STEC_IO24" "STEC_IO25" "STEC_IO26" "STEC_IO27" "STEC_IO28" "STEC_IO29" "STEC_IO30" "STEC_IO31" "STEC_IO32" "STEC_IO33" "STEC_IO34" "STEC_IO35" "STEC_IO36" "STEC_IO37" "STEC_IO38" "STEC_IO39" "STEC_IO40" "STEC_IO41" "STEC_IO42" "STEC_IO43" "STEC_IO44" "STEC_IO45" "STEC_IO46" "STEC_IO47" "STEC_IO48" "STEC_IO49" "STEC_IO50" "STEC_IO51"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

K19 H20 K20 G21 J21 H22 G24 G23 H23 F23 H24 F24 J25 E25 J26 F25 K25 F26 L25 G25 L26 H25 M25 H26 M26 G29 G30 F29 H29 E30 H30 E29 J29 D30 J30 D29 K29 B26 L29 A26 L30 B25 V22 P22 U21 P21 U22 N22

51

net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net

"STEC_IO52" "STEC_IO53" "STEC_IO54" "STEC_IO55" "STEC_IO56" "STEC_IO57" "STEC_IO58" "STEC_IO59" "STEC_IO60" "STEC_IO61" "STEC_IO62" "STEC_IO63" "STEC_IO64" "STEC_IO65" "STEC_IO66" "STEC_IO67" "STEC_IO68" "STEC_IO69" "STEC_IO70" "STEC_IO71" "STEC_IO72" "STEC_IO73" "STEC_IO74" "STEC_IO75" "STEC_IO76" "STEC_IO77" "STEC_IO78" "STEC_IO79" "STEC_IO80" "STEC_IO81" "STEC_IO82" "STEC_IO83" "STEC_IO84" "STEC_IO85" "STEC_IO86" "STEC_IO87" "STEC_IO88" "STEC_IO89"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

T21 N21 T22 M22 R22 M21 R21 L21 V23 K22 U24 K21 T23 J22 T24 N23 R24 M24 R23 M23 P24 L24 T26 L23 R26 K24 R25 J23 U28 P25 T27 N26 P29 N25 N29 M29 N30 M30

LED i nterface
net net net net net net net net "TESTLED0" "TESTLED1" "TESTLED2" "TESTLED3" "TESTLED4" "TESTLED5" "TESTLED6" "TESTLED7" LOC = LOC = LOC LOC LOC LOC LOC = = = = = AG18 AH17 AG15 AH14 AG13 AH12 AG12 AH11

LOC =

52

Switch interface
net net net net net net net net "IL0" "IL1" "IL2" "IL3" "IL4" "IL5" "IL6" "IL7" LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = AJ12 AK11 AJ11 AJ10 AK8 AJ8 AK7 AJ7

Serial I nterface RS23 2

net net net net "TXD1-F" "TXD2-F" "RXD1-F" "RXD2-F" LOC = LOC = LOC = LOC = AH8 AG8 AG9 AH10

Serial I nterface RS42 2

net net net net "TTL_IN1_QS" "TTL_IN2_QS" "TTL_OUT1_QS" "TTL_OUT2_QS" LOC = LOC = LOC = LOC = G10 H9 E6 F6

Sev en Segment LE D Dis play interface

net net net net net net net net net net net net "CSDIS0_QS" "CSDIS1_QS" "CSDIS2_QS" "CSDIS3_QS" "SEGA_QS" "SEGB_QS" "SEGC_QS" "SEGD_QS" "SEGDP_QS" "SEGE_QS" "SEGF_QS" "SEGG_QS" LOC LOC LOC LOC LOC = = = = = AD8 AC8 AD7 AE9 AC9 AF9 AJ6 AK5 AG11 AJ5 AJ4 AK4

LOC = LOC = LOC = LOC = LOC = LOC = LOC =

LCD inte rface

net net net net net net net net net net net "DL0_QS" "DL1_QS" "DL2_QS" "DL3_QS" "DL4_QS" "DL5_QS" "DL6_QS" "DL7_QS" "E_QS" "R/W_QS" "RS_QS" LOC = LOC = LOC LOC LOC LOC LOC LOC = = = = = = C27 D27 D28 E27 F28 G27 G28 H27 D26 C25 G17

LOC = LOC = LOC =

53

KEY Inte rface

net net net net "KEY0" "KEY1" "KEY2" "KEY3" LOC LOC LOC LOC = = = = AG20 AH20 AG19 AH19

VGA inte rface

net net net net net net net net net net net "GREEN_0" "GREEN_1" "GREEN_2" "RED_0" "RED_1" "RED_2" "BLUE_0" "BLUE_1" "BLUE_2" "HOR_SYNC" "VER_SYNC" LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = AG5 AH4 AG4 AH7 AG7 AH6 AF4 AE3 AD4 AG3 AD3

USB interface
net net net net net net net net net net net net "USB_D0" "USB_D1" "USB_D2" "USB_D3" "USB_D4" "USB_D5" "USB_D6" "USB_D7" "RD#" "WR#" "TXE#" "RXF#" LOC = LOC = LOC = LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = T28 R28 R27 P28 N27 M28 M27 L28 K28 J27 H28 L27

PS/2 Ke y Board I nterface

net net "KBD_CLOCK_QS" "KBD_DATA_QS" LOC = LOC = G19 H18

PS/2 Mouse Interfa ce

net net "MOUSE_CLOCK_QS" "MOUSE_DATA_QS" LOC = LOC = J18 K17

LAN inte rface

Data Lines net net net net net net "LAN_D0" "LAN_D1" "LAN_D2" "LAN_D3" "LAN_D4" "LAN_D5" LOC LOC LOC LOC = = = = W25 W26 V25 V26 U25 AA19

LOC = LOC =

54

net net net net net net net net net net net net net net net net net net net net net net net net net net Address Lines: net net net net net net net net net net net net net net net net net

"LAN_D6" "LAN_D7" "LAN_D8" "LAN_D9" "LAN_D10" "LAN_D11" "LAN_D12" "LAN_D13" "LAN_D14" "LAN_D15" "LAN_D16" "LAN_D17" "LAN_D18" "LAN_D19" "LAN_D20" "LAN_D21" "LAN_D22" "LAN_D23" "LAN_D24" "LAN_D25" "LAN_D26" "LAN_D27" "LAN_D28" "LAN_D29" "LAN_D30" "LAN_D31"

LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC = LOC =

AA20 AB21 AA29 Y29 Y30 W29 W30 V29 V30 U29 T29 T30 R29 R30 W24 W23 Y24 Y23 AE28 AD27 AD28 AC27 AC28 AB27 AA28 Y27

"LAN_A1" "LAN_A2" "LAN_A3" "LAN_A4" "LAN_A5" "LAN_A6" "LAN_A7" "LAN_A8" "LAN_A9" "LAN_A10" "LAN_A11" "LAN_A12" "LAN_A13" "LAN_A14" "LAN_A15" "LAN_nBE0" "LAN_nBE1"

LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = =

AB30 AB29 AC30 AC29 AD30 AD29 AE29 AF30 AF29 AG30 AG29 V21 T25 W22 W21 Y21 AA22

LOC = LOC = LOC = LOC = LOC LOC LOC LOC = = = =

55

net net net Control Sign als net net net net net net net net net net net net net net net net net net net

"LAN_nBE2" "LAN_nBE3" "LAN_AEN"

LOC = LOC = LOC =

AB22 AA21 AF27

"ENEEP" "IOS0" "IOS1" "IOS2" "LAN_ARDY" "LAN_CYCLE" "LAN_INTR" "LAN_nADS" "LAN_nCS" "LAN_nDEV" "LAN_nLCLK" "LAN_nRD" "LAN_nSRD" "LAN_nWR" "LAN_RDYRTN" "LAN_RST" "\INIT\" "\VLBUS\" "W/nR"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = =

AB26 Y26 Y25 AA25 AG27 AH25 AG22 AH27 AG24 Y28 W27 AG23 V27 AH24 W28 AH23 AG16 AG28 AG26

LOC = LOC = LOC =

SDRAM interface
Address Lines net net net net net net net net net net net net net net DATA Lines net net net net net net "A0_S1" "A1_S1" "A2_S1" "A3_S1" "A4_S1" "A5_S1" "A6_S1" "A7_S1" "A8_S1" "A9_S1" "A10_S1" "A11_S1" "BA0_S1" "BA1_S1" LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = AA7 Y8 Y7 K7 L8 L7 M8 M7 N8 P7 AB8 AC7 V8 W7

LOC =

"D0_S1" "D1_S1" "D2_S1" "D3_S1" "D4_S1" "D5_S1"

LOC LOC LOC LOC LOC LOC

= = = = = =

AE5 AD6 AC6 AC5 AB6 AB5

56

net net net net net net net net net net net net net net net net net net net net net net net net net net net net net net Control Lines net net net net net net

"D6_S1" "D7_S1" "D8_S1" "D9_S1" "D10_S1" "D11_S1" "D12_S1" "D13_S1" "D14_S1" "D15_S1" "D16_S1" "D17_S1" "D18_S1" "D19_S1" "D20_S1" "D21_S1" "D22_S1" "D23_S1" "D24_S1" "D25_S1" "D26_S1" "D27_S1" "D28_S1" "D29_S1" "D30_S1" "D31_S1" "DQM0_S1" "DQM1_S1" "DQM2_S1" "DQM3_S1"

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = =

AA6 Y6 L6 K6 J5 J6 H5 H6 G6 F5 T5 T6 U6 V5 V6 W5 W6 Y5 R5 R6 P6 N5 N6 M5 M6 L5 R8 H7 W8 J8

LOC = LOC = LOC =

"CKE_S1" "CLK_S1" "CS#_S1" "RAS#_S1" "CAS#_S1" "WE#_S1"

LOC LOC LOC LOC

= = = =

K9 K10 U7 T8 T7 R7

LOC = LOC =

57

APPENDIX B
Operat ing Instruction To St art A N ew Design
B.1 Starting The ISE Softwar e:
Start ISE f rom the Sta rt menu by selecting S tart -> Programs -> Xilinx ISE Proj ect Nav igator.

B.2 Design Flow

DESIGN ENTRY SIMULATION SYNTHESIS IMPLEM ENTATION DEVI CE PROGRAM MING

58

Sam ple De sign of Half Adder i s u sed to e xplain the Desig n Flow.

B.3 Design Description

A B Sum

Half Adder

Carry

B.4 Trut h Table of Half adder

Inputs A B 0 0 0 1 1 0 1 1

Output
Sum 0 1 1 0 Carry 0 0 0 1

B.5 VHDL Code f or Half adder

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half_adder is Port ( a : in std_logic; b : in std_logic; c : in std_logic; sum : out std_logic; carry : out std_logic); end full_adder; architecture Behavioral of half_adder is begin sum <= a xor b ; carry <= a and b;

end Behavioral;

59

B.6 St eps to implement the Half adder in t he FPG A using Xilinx iSE( 8.1i)
Step 1 : Start th e Xilinx Project Na vigator by u s ing t he de sktop sho rtcut or b y u sing the Sta rt Prog rams Xilinx ISE (8.1i)

Source Window

Workspace

Process Window Transcript

Step 2

Create a new project In the window g o to FILE New p roje ct. Specify the project name and location and say NEXT

Select Device. Use the pull-down arro w to select the Value for each Property Nam e. Click in the field to access the pull-do wn list.

60

Say FINIS H. Project summ ary is see n.

61

Step 3:

Creating a new VHD file Click on the symbol of FPGA device and then right click Click on new source VHDL mo dule and give the File name

VHDL Module

Then say Next Define ports.In this case a and b are the input port s defined a s in sum and ca rry are output p ort s defined a s out after thi s say Next t wice an d then Finish Skeleton of the de sign is sho wn in the V HDL editor.

62

Step 4:

Writing the Behavioral VHDL Code in VHDL Editor Sam ple code is given below f or thi s expe rim ent.

Design Entry

Step 5 Step 6

Che ck Syntax Run th e Check syntax Process window synthe sizecheck syntax >, and rem ove errors if pre sent. Creating a test bench file Verify the ope ration of you r de s ig n before yo u im plement it as hard ware. Simulation can be don e u sing ISE sim ulator. Fo r thi s click on the symbol of FP GA device and then right click Click on new sou rce Test Bench Wavefo rm an d give the na me Select entityFinish.

Select the desi red pa rameters fo r s im ulating your de s ign. In thi s ca se combinational circuit and Si mulation time. 63

Step 7:

Si mulate the code Si mulation Tools ISE tool supports the following si mulation tools: HDL Bencher is an automated test be nch creation tool. It is f ully integrated with Pro ject Na vigator. Mod elSi m f rom Model Technology, In c., is integrated in Project Navigator to simulate the d esign at all steps (Fun ctional and Timing). Mo delSim XE, the Xilinx Edition of Model Tech nology, Inc.s ModelSi m application, can be installed fro m the MTI CD included in your ISE Tool In source Window from the Drop-down m enu select Behavio ral Si mulation to view the created te st Bench file.

64

For simulation

Click on te st bench file. Te s t bench file will open in main window. A ssign all the signal s and s a ve File. From the source of pro ce ss window. Click on Si mulate Behavioral Mod el in Proce ss window.

Verify you r de sign in wave windo w b y se eing behaviou r of output signal with re s p ect to input s ignal. Clo se the ISE sim ulator windo w

65

Simulated Output

Step 8:

Synthe size the de sign using X ST. Tran s late your de sign into gates and optimize it for the target a rchitecture . This i s t he synthe si s pha se. Again for synthesi zing you r de s ig n, from the source window s elect, synthe sis/ Imple mentation f rom the drop-down m enu.

Synthesis

Highlight file in the Source s in Project windo w. To run synthesi s, right-click on 66

Synthe size, and t he Run option, o r double-click on Synth esize in the P roce sse s for Cu rrent Sou rce window. Synt hesi s will run, and a green che ck 9 will appear ne xt to S ynthesi ze when it i s su cce ssfully com pleted. a red cross 8indicate s an error was gene rated and a yellow exclamation ! mark indicate s th at a wa rning wa s gene rate d, (warnings a re OK). Che ck the synthe si s report. If there are an y errors correct it and re run synth e s i s..

Synthesis complet ed successfully

Step 9:

Create Con straints File(UCF) Click on the symbol of FPGA device and then right click Click on ne w source Implementation Con s traint s File and give the nam e Select entity Fini s h. Click on User Constraint and in that Double Click on Assign Package Pins option in Pro cess window. Xilinx PA CE windo w open s. Enter all the pin a ssignm ent s in PA CE., depending upon ta rget de vice and number of input and output s used in your design. (sa mple code is given below for given design.)

67

Pin assignments

Step 10 :

Implementing a De sign Once synthesi s i s complete, you can place and route you r d e s ign to fit into a Xilinx device, and you ca n als o get som e post place-and -route timing inform ation about the de sign. The im plementation stage consi sts of taking the synthesi zed netlist through tran slation, mapping, and place and route. To check you r de sign a s it i s implem ented, repo rts a re available for ea ch stage in the im plementation proce ss. Use the Xilinx Const raint s E ditor to add timing and location con st raints fo r the implem entation of your design. Thi s procedure run s you through the ba s i c flow fo r implem entation. Right-click on Implement De sign, and choo se the Run option, or double left-click on Implement De sign.

Implement ation done

68

Step 11 : Step 12

Generating Progra mming File Right-click on Generate P rog ramming File, choo se t he Run option, or double left-click on Generate Prog ramming File. This will generate the Bit stream Downloading in Boundary Scan M ode. Note : Xilinx provides 2 -tools for d ownloading purpose, viz. iMPA CT - is a command line and GUI bas ed tool PROM File For matte r

Boundar y Scan Mode

Pro cedu re for downloading using iMPACT Bounda ry S can Mode 1. Right click on Configure Device (i MPACT) -> and Say RUN or Double click on Configure Device (i MPA CT). 2. Right click in wo rkspace and sa y Initialize chain .The device i s seen. 3. Right click on the de vice and say Prog ram.

If the device i s prog ramm ed prope rly, it says Progra mming Su cceeded or else. Prog ra mming Failed. The DONE Led glows green if programming succ eeds. 69

Step 13 : Step 14 :

Note: Before downloading m ake su re that P roto board i s conn ected t o PC's parallel port with the cable provided and po wer to the P rotobo ard i s ON. Apply input thro ugh DIP S witche s, output is displayed on LE Ds Configu ration thro ugh PROM : Gene rating P ROM file: FP GA can also be configured in Master Serial M ode through P ROM. For this you need to program the PROM through a .m cs file. Right click on Generate P ROM,A CE or JTA G file -> and S ay RUN o r Double click on Generate PROM,ACE or JTAG file

Specify the PROM file name and location where it is to be gene rated.

70

Specify the de sire d pa ram eters of the PROM on board and s a y ADD th en FINISH

71

Say Gene rate File from the Proce ss Window.

Note: Check the Jumper setting on the board. Ref er the Chapt er jumper Setting

PROGRAMMING THE PROM

Similar to Step 12.Initialize chain through iM PACT. P ROM and FP GA devices on board a re seen .A ssign the gene rated m cs file and bit file as d e s ired. Right click the PROM sym bol and say P ROGRA M.

72

No w, when eve r the bo ard i s powere d on in m ast er serial m ode, FPGA i s configure d through PROM autom atically.

73

APPENDIX C
ASCII Table 5 X 7 LCD Display
The AS CII code fo r 5 x 7 L CD Display is a s shown below:

74

APPENDIX D
ADCDA C Add On Card
About this Card: ADC- DA C add on card pro vide s an a nalog interface to the VIRTEX -5, VIRTEX-4 and SPA RTA N-3 ba sed de velopment board de veloped by Bitma pper I ntegrati on Tec hnol ogies PVT Ltd.. This interface enable s t he u ser to implement design that involve dual channel analog input and output fun ction that can be u sed fo r com munication, video and DSP b ased applications. Add On Card Details: ADC-DA C add on card com pri ses of a two single ch annel A DC A D9240 and DA C 7541 fo rm TI. The specifications of t he above mentioned are a s follows: ADC AD9240: 14 bit analog to digital converte r with sam pling rate of 10 MSPS. Operate s on s ingle supply voltage of 5 V. As ingle-ended CLK input control s con vert er o peration. Input ran ge of 0 to 5 .0 V. DAC AD7541: 12 bit 10 MSPS digital to analog conve rter. Dual input chan nel. Single supply voltage of 5V. Cont rol of the A/ Ds and D/ A s i s handled by the FPGA through a SAMTEC connect or interface provided on mother boa rd and add on card. The sup ply voltage for the A DC/DA C interface is als o pro vided via a SAM TE C connecto r. The interface de tails fo r the ADC and DA C u nit with FPGA a re a s m entioned in s e ction E-1 and E-2. E-1: ADC I nterfac e Details: Block diagram for A DC interfa ce a s sh own below:

75

Unipolar analog input of am plitude range 0 5.0 V can be a pplied at analog in of SMA connector J3 and J4. ADC can sample the input at up to 10Msp s sampling rate with a resolution of 14 bit. Data line s of A DC are inte rfaced to FP GA to p ro cess the sampled data. OTR s ign al provide s the o ver-range indication. Clock to A DC is p rovided th roug h FPGA. The AD9 240 uses four-sta ge pipeline architecture with a wideband input sample-and-hold amplifier (S HA) implem ented on a co st -effective CMOS p rocess. Ea ch stage of the pipeline, excluding the la st, con si s t s of a lo w re solution fla sh A/ D connected to a switched capa citor DA C and inters ta ge residue amplifier (M DA C). The re sidue am plifier amplifies the difference bet ween the re con s t ru cted DAC output and t he fla sh in put fo r the ne xt stage in the pipeline. One bit of redundan cy is u sed in each of the stages to fa cilitate digital correction of fla sh e rro rs . The last stage simply con s i st s of a flash A/ D. The pipeline architecture allows a grea ter t hroughput rate at the expe n s e of pipeline delay or latency. This m eans that while the convert er is capable of captu ring a new input sample eve ry clock cycle, it actually ta kes three clock cycles for t he conversion to be fully proce ssed an d appear at the output. This latency i s not a con cern in most applications. The digital output, together with the out -of -range indicator (OT R), i s latched into an output buffe r to d rive the o utput pin s . The ou tput d rivers can be configured to interface with +5 V or +3. 3 V logic families.

76

The timing diagram for ADC i s as sho wn belo w:

Output of A DC i s in s traight binary f ormat with lowest value repre senting all 0s and highe st value rep re senting all 1s. For more detail s on A DC A D9240 please ref er th e data sheet provided along with thi s boa rd

77

E-2: DAC I nterfac e Details: Block diagram for DAC interfa ce i s as sho wn below

Data line s of bot h the DACs a re interfa ced to FP GA. Analog output o f DACs i s available on SMA connector J5 and J6.The range a vailable at DA C output extend s f rom 0 to 5V for a refe rence voltage of 2. 5V. Thi s range can be varied b y adju sting the value of V ref by varying the value of pre set PR11 and PR12 fo r DA C1 and DA C2 re spectively. AD7 541A does not require an input clock for it s operation and h a s a con version tim e of 100n s with 12 bit re solution. Input to DAC is in straight bina ry fo rmat with lo we st value re presented by all 0s and highe st value repre sent ed by all 1s. For more details on DA C plea se refer the data sheet p rovided along with the boa rd.

78

The User constraint file for the ADC DAC add on ca rd i s as in table C-1.
NET NAME CONNECTOR PIN NO. VIRTEX-4 PROTOBOARD DAC-1 "DAC1-D0" "DAC1-D1" "DAC1-D2" "DAC1-D3" "DAC1-D4" "DAC1-D5" "DAC1-D6" "DAC1-D7" "DAC1-D8" "DAC1-D9" "DAC1-D10" "DAC1-D11" DAC-2 "DAC2-D0" "DAC2-D1" "DAC2-D2" "DAC2-D3" "DAC2-D4" "DAC2-D5" "DAC2-D6" "DAC2-D7" "DAC2-D8" "DAC2-D9" "DAC2-D10" "DAC2-D11" ADC-1 "ADC1_D1" "ADC1_D2" "ADC1_D3" "ADC1_D4" "ADC1_D5" "ADC1_D6" "ADC1_D7" "ADC1_D8" "ADC1_D9" "ADC1_D10" "ADC1_D11" "ADC1_D12" "ADC1_D13" "ADC1_D14" "ADCCLK1" "OTR1" ADC-2 "ADC2_D1" "ADC2_D2" "ADC2_D3" FPGA PIN NO. SPARTAN-3 5M PROTBOARD LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = H30 J29 J30 K29 L29 L30 H29 M26 M25 L26 L25 K25 K18 H19 H20 G21 H22 G23 H23 G24 J21 K20 K19 J19 T27 P24 R24 L21 M21 M22 N21 N22 P21 P22 U22 V22 U21 U24 R21 N29 SPARTAN-3 5M PCI PROTOBOARD LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = G6 F5 F6 E6 F8 F7 T4 G11 H12 G12 H13 G14 J12 K13 K14 J14 K15 M3 H8 G7 J9 J10 K11 K12 AD3 U3 AD20 AE6 AE5 AD6 AC6 AC5 AB6 AB5 AC13 AC12 AD12 AC18 AD16 AE3 VIRTEX-5 PROTOBOARD

IO-34 IO-36 IO-38 IO-40 IO-42 IO-44 IO-32 IO-28 IO-26 IO-24 IO-22 IO-20 IO-0 IO-1 IO-5 IO-7 IO-9 IO-11 IO-12 IO-10 IO-8 IO-6 IO-4 IO-2 IO-82 IO-72 IO-68 IO-59 IO-57 IO-55 IO-53 IO-51 IO-49 IO-47 IO-50 IO-46 IO-48 IO-62 IO-58 IO-86 IO-67 IO-69 IO-71

#J1-42 #J1-44 #J1-46 #J1-48 #J1-50 #J1-52 #J1-40 #J1-36 #J1-34 #J1-32 #J1-28 #J1-26 #J1-2 #J1-1 #J1-5 #J1-7 #J1-11 #J1-13 #J1-16 #J1-14 #J1-12 #J1-8 #J1-6 #J1-4 #J2-46 #J2-34 #J2-28 #J2-15 #J2-13 #J2-11 #J2-7 #J2-5 #J2-3 #J2-1 #J2-6 #J2-2 #J2-4 #J2-22 #J2-16 #J2-52 #J2-25 #J2-27 #J2-31

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

H21 G24 H23 H24 J23 K23 H22 J22 K21 K22 L21 N22 C24 D16 D17 D18 C19 D19 G23 F24 F23 E24 E23 D24 V23 AA24 V22 U21 J20 K20 L19 L20 M19 M20 P20 R20 P19 W21 Y21 U24

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

M24 N23 N24 P24 P23 R23 R21 P21 N22 N21 M22 M21 K20 J19 T25 P26 P25 G21 P20 N19 M20 M19 Y12 L19 AB24 AB20 AB19 U20 U19 V19 W20 W19 Y20 Y18 Y12 Y10 Y11 AB17 AA15 AA24

LOC = R23 LOC = P22 LOC = R24

LOC = N23 LOC = M24 LOC = M23

LOC = AF8 LOC = AE9 LOC = AF9

LOC = Y22 LOC = W21 LOC = U21

79

NET NAME

CONNECTOR PIN NO. VIRTEX-4 PROTOBOARD

FPGA PIN NO. SPARTAN-3 5M PROTBOARD LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = L24 L23 K24 J23 P25 N26 N25 M29 M30 N30 K21 K22 J22 SPARTAN-3 5M PCI PROTOBOARD LOC = AE10 LOC = AE11 LOC = AF11 LOC = W4 LOC = Y3 LOC = Y4 LOC = AA3 LOC = AB4 LOC = AG3 LOC = AF4 LOC = AE7 LOC = AF6 LOC = AE8 VIRTEX-5 PROTOBOARD LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC = = = = = = = = = = = = = U22 T22 W23 W24 V23 V24 U24 T23 T24 Y23 AA22 T19 Y21

"ADC2_D4" "ADC2_D5" "ADC2_D6" "ADC2_D7" "ADC2_D8" "ADC2_D9" "ADC2_D10" "ADC2_D11" "ADC2_D12" "ADC2_D13" "ADC2_D14" "ADCCLK2" "OTR2"

IO-73 IO-75 IO-77 IO-79 IO-81 IO-83 IO-85 IO-87 IO-89 IO-88 IO-63 IO-61 IO-65

#J2-33 #J2-35 #J2-37 #J2-41 #J2-43 #J2-45 #J2-47 #J2-51 #J2-53 #J2-54 #J2-21 #J2-17 #J2-23

LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC

= = = = = = = = = = = = =

P23 P24 N24 N23 M24 M23 L24 L23 K24 T23 T21 U22 T24

Ta ble E-1: ADC DAC Add on Card User Constraint File

80

APPENDIX E
Video A DC DA C Add On Card
About this Card: Video ADC- DA C add on card pro vide s an Video interfa ce to the VI RTEX-5, VIRTEX-4 and SPA RTA N-3 ba sed de velopment board de veloped by Bitma pper I ntegrati on Tec hnol ogies PVT Ltd. This interface enable s t he u ser to im plement des ign that involve f or digitizing of video data for Digital TV, Digital Video, M ultimedia, Video Capture, Video Editing and Se curity Applications. Interface co n s i st s of th ree channel s Video ADC TLV 7534 a nd th ree ch annels Video DAC THS8133 b and a SYNC Separato r from Texa s a nd support s NTSC and PAL compliant video input. Cont rol of the Video A/ D and D/A i s handled by t he FPGA th rough a SAMTEC connector interface pro vided on m other board a nd add on ca rd. The supply voltage fo r the Video ADC/ DA C interface is al s o provided th roug h SAM TEC conn ecto r. The interface de tails fo r the ADC and DA C u nit with FPGA a s de scribed below

FP GA VIDEO Int erface

F.1 Video ADC interface

Add on card ha s a TLV 5734 A DC f rom Texa s In strument s . The TLV5734 i s a t riple 8-bit converte r with high-p re ci s ion clamp for digitizing video signal s in RGB or YUV color spa ces. The device suppo rts pixel rate s up to 30 MSPS. The TLV5734 i s powe red from a s ingle 3.3-V supply. Separate clamping levels a re p rovided fo r the RGB a nd Y UV analog component video inputs. The clam p timing window is pro vided by an external pul se. The o utput -data formatter selects from output form ats of 4:4:4, 4: 1:1, and 4: 2:2. For RGB applications, the 4:4:4 o utput fo rm ats with clam p can be u sed. For more details on Video A DC refer TLV573 4 datasheet.

81

A s shown in figure R(Y ) video input ca n be applied at SM A conn ecto r J7, G(U) video input ca n be applied at SMA connect or J6 and B(V) video input is applied at SMA conne ctor J8. The interface de tails fo r the Video ADC interfa ce are as described below: Pin Description f or Video ADC Int erfa ce
Name Mode0, Mode1 Pin Description Output format mode selector Output initialized. The output data is synchronized with the first falling edge of CLK after INIT changes from low to high. INIT is a control terminal that allows the external system to initialize the TLV5734 data conversion cycl External clamp pulse input (active high) Video input mode selector, low for RGB, high for YUV Data output of ADC A (MSB:AD8, LSB:AD1) (format 1, format 2, format 3) Data output of ADC B (MSB:BD8, LSB:BD1) (format 2) Data output of ADC C (MSB:CD8, LSB:CD1) (format 2) Clock input. The clock frequency is four times the frequency subcarrier (fsc) for most video systems

INIT

EXTCLP G/Y AD1 AD8 BD1 BD8 CD1 CD8 CLK

F.2 VIDEO DAC

The THS8133 is a gene ral-pu rpose t riple high-speed D/ A con ve rter (DAC) optimized for u se in video/graphics application s. The de vice operates f rom a 5-V analog s upply and a 3 -V to 5 -V range digital supply. The T HS8133 ha s a sam pling rate up to 80 MSPS . The device consi sts of three 10 -bit D/A conve rters and additional circuitry fo r bi-level/t ri-level sync and blanking level generation in video application s. The current -stee ring DA Cs can be directly terminated in re s i stive load s to p rodu ce voltage o utput s. Furtherm ore, the T HS8133 can generate both a t raditional bi-level sync and a t ri-level sync signal, a s per the SMPTE standard s , via a digital control interface. The sync sig nal is in s e rted on one of the a nalog output channels (sync-on -g reen/lum inance) o r on all output ch annel s. Als o, a blan king con trol s ignal set s the out put s to defined level s du ring the nona ctive video window. DAC output i s a vailable on SM A connecto r J3, J4 and J5. For more details refer THS8133b Handboo k. The interface de tails fo r the Video DA C interfa ce are as described below: Pin Descript ion f or Video DAC
Name DAC0-Pb9 to DAC0-Pb0 DAC0-Pr9 to DAC0-Pr0 DAC0-Y9 to DAC0-Y0 Pin Description Blue or Pb pixel data input bus. Index 0 denotes the least significant bit Red or Pr pixel data input bus. Index 0 denotes the least significant bit. Green or Y pixel data input bus. Index 0 denotes the least significant bit.

82

BLANK-0 #

Blanking control input, active low. A rising edge on CLK latches BLANK. When asserted, the ARPr, AGY and ABPb outputs are driven to the blanking level, irrespective of the value on the data inputs. SYNC takes precedence over BLANK, so asserting SYNC (low) while BLANK is active (low) will result in sync generation. Sync control input, active low. A rising edge on CLK latches SYNC. When asserted, only the AGY output or ARPr, AGY and ABPb outputs are driven to the sync level, irrespective of the values on the data or BLANK inputs. Consequently, SYNC should remain low for the whole duration of sync, which is in the case of tri-level sync both the negative and positive portion. Sync tri-level control, active high. A rising edge on CLK latches SYNC_T. When asserted, a positive sync (higher than blanking level) is generated when SYNC is low. When disabled, a negative sync (lower than blanking level) is generated when SYNC is low. When generating a tri-level (negative-to-positive) sync, a L "H transition on this signal positions the start of the positive transition. See Figure 6 for timing control. The value on SYNC_T is ignored when SYNC is not asserted (high). Clock input. A rising edge on CLK latches RPr0-9, GY0-9, BPb0-9, BLANK, SYNC, and SYNC_T. The M2 input is latched by a rising edge on CLK also, but only when additional conditions are satisfied, as explained in its terminal description.

SYNC -0 #

SYNC_T0

CLK DAC

M1, M2

Used for operational mode configuration.

F.3 SYNC SEP ERATOR

The EL4583 the Syn c Sep arato r e xtracts timing from video sync in NTS C, P AL, and SECAM systems, and non standard fo rmat s, o r from com puter g raphics o perating at higher scan rates. Timing adjustm ent is via an external re s i stor. Input without valid vertical interval (no serration pulse s) pro duce s a defa ult vertical output. Output s are : compo s ite sync, vertical sync, filter, burst/back porch, horizontal, no signal detect, level, and odd/even output (in interlace d scan fo rm ats only). The EL4583 sync slice level is set to the m id-point between sync tip and t he blan king level. This 50% point i s dete rmined by t wo internal sam ple and hold circuit s that t rack syn c tip and back porch level s . It pro vides hum and noi s e rejection and compen sate s for input level s of 0.5V to 2.0VP -P. A built in filter attenuate s the ch rom a signal to prevent color b urst from distu rbing the 50% syn c slice. Cut of f fre quency i s set by a resi sto r to g round f rom the Filter Cut Off pin. Additionally, the filter can be by-passed and video signal fed directly to the Video Input. The level output pin provide s a signal with twice the sync amplitude which may be u sed t o cont rol an e xtern al AGC function. A TTL/ CM OS com patible No Signal Detect Outp ut flag s a loss or red uction in input signal level. A re s i stor set s the Set Detect Le vel. 83

Pin Description of the sync separator interface to that of FPGA i s a s s ho wn below: Pin Descript ion f or SYNC Separator Interfa ce
Name Vertical Sync Output Pin Description The vertical sync output is synchronous with the first serration pulse rising edge in the vertical interval of the input signal and ends on the trailing edge of the first equalizing Output pulse after the vertical interval. It will therefore be slightly more than 3H lines wide. This is a digital output which goes high when either a) loss of input signal or b) the input signal level falls below a predetermined amplitude as set by RLV on pin 2. There will be several horizontal lines delay before the output is initiated. The start of back porch output is triggered on the trailing edge of normal H sync, and on the rising edge of serration pulses in the vertical interval. The pulse is timed out internally to produce a one-shot output. The pulse width is a function of RSET. This output can be used for d.c. restore functions where the back porch level is a known reference. Odd-even output is low for even field and high for odd field. The operation of this circuit has been improved for rejecting spurious noise pulses such as those present in VCR signals. This output produces only true H pulses of nominal width 5s. The leading edge is triggered from the leading edge of the input H sync, with the same prop. delay as the composite sync. The half line pulses present in the input signal during vertical blanking are eliminated with an internal 2H eliminator circuit.

No Signal Detect Output

Burst/Back Porch Output

Odd/Even Output

Horizontal Sync Output

84

F.4 Consolidated UCF for All M other Boards:

Net Name DAC INTERFACE "DAC0Pb<0>" "DAC0Pb<1>" "DAC0Pb<2>" "DAC0Pb<3>" "DAC0Pb<4>" "DAC0Pb<5>" "DAC0Pb<6>" "DAC0Pb<7>" "DAC0Pb<8>" "DAC0Pb<9>" "DAC0Pr<0>" "DAC0Pr<1>" "DAC0Pr<2>" "DAC0Pr<3>" "DAC0Pr<4>" "DAC0Pr<5>" "DAC0Pr<6>" "DAC0Pr<7>" "DAC0-Pr<8>" "DAC0Pr<9>" "DAC0Y<0>" "DAC0Y<1>" "DAC0Y<2>" "DAC0Y<3>" "DAC0Y<4>" "DAC0Y<5>" "DAC0Y<6>" "DAC0Y<7>" "DAC0Y<8>" "DAC0Y<9>" "DAC0_BLANK_BAR" "DAC0_CLK" "DAC0_M1" "DAC0_M2" "DAC0_SYNC_BAR" "DAC0_SYNC_T" SYNC SEPERATOR "HORSYNC_OP" "NOSIG_OP" "ODDEVEN_OP" "VERTSYNCOP" "BBPORTCH_OP" "COMPSYNC_OP" ADC INTERFACE "ADCAD<1>" "ADCAD<2>" "ADCAD<3>" "ADCAD<4>" "ADCAD<5>" "ADCAD<6>" "ADCAD<7>" Connector Pin Number FPGA Pin No. SP3-5M G30 H30 J29 J30 K29 L29 L30 E29 B25 A26 M26 M25 L26 L25 K25 J26 J25 E25 F24 F23 H19 G20 H20 G21 K18 J19 K19 K20 J21 G24 G23 H23 D29 B26 H22 H24 G29 F25 H26 F29 H25 E30 M22 N21 N22 P21 P22 V22 U21 FPGA Pin No SP3-PCI H11 G6 F5 F6 E6 F8 F7 F3 H15 G15 G11 H12 G12 H13 G14 G10 H9 M4 M3 T3 K13 J13 K14 J14 J12 K12 K11 J10 J9 G7 J15 H8 F9 E9 K15 G8 H4 L3 H3 G3 J4 G4 AD6 AC6 AC5 AB6 AB5 AC12 AD12 FPGA Pin No VIRTEX-4 J21 H21 G24 H23 H24 J23 K23 C21 D23 C23 J22 K21 K22 L21 N22 N21 M22 E18 F17 E17 D16 C17 D17 D18 C24 D24 E23 E24 F23 F24 D19 G23 C22 D22 C19 M21 E22 F18 E21 C20 F20 D20 K20 L19 L20 M19 M20 R20 P19 FPGA Pin No VIRTEX-5 R22 M24 N23 N24 P24 P23 R23 L24 K26 L25 P21 N22 N21 M22 M21 T20 R20 H22 H21 G22 J19 J20 T25 P26 K20 L19 L20 M19 M20 N19 G21 P20 M26 M25 P25 P19 J23 J21 H24 J24 H23 K23 V19 W20 W19 Y20 Y18 Y10 Y11

#J1-38 #J1-42 #J1-44 #J1-46 #J1-48 #J1-50 #J1-52 #J1-41 #J1-51 #J1-49 #J1-36 #J1-34 #J1-32 #J1-28 #J1-26 #J1-24 #J1-22 #J1-21 #J1-17 #J1-15 #J1-1 #J1-3 #J1-5 #J1-7 #J1-2 #J1-4 #J1-6 #J1-8 #J1-12 #J1-14 #J1-13 #J1-16 #J1-45 #J1-47 #J1-11 #J1-18 #J1-35 #J1-23 #J1-33 #J1-37 #J1-31 #J1-39 #J2-11 #J2-7 #J2-5 #J2-3 #J2-1 #J2-2 #J2-4

85

Net Name "ADCAD<8>" "ADCBD<1>" "ADCBD<2>" "ADCBD<3>" "ADCBD<4>" "ADCBD<5>" "ADCBD<6>" "ADCBD<7>" "ADCBD<8>" "ADCCD<1>" "ADCCD<2>" "ADCCD<3>" "ADCCD<4>" "ADCCD<5>" "ADCCD<6>" "ADCCD<7>" "ADCCD<8>" "CLK_VIDEO1" "EXTCLP" "GY" "INIT" MODE0 MODE1

Connector Pin Number #J2-6 #J2-31 #J2-27 #J2-25 #J2-23 #J2-21 #J2-17 #J2-15 #J2-13 #J2-22 #J2-28 #J2-34 #J2-46 #J2-52 #J2-51 #J2-47 #J2-45 #J2-41 #J2-16 #J2-43 #J2-37 #J2-35 #J2-33

FPGA Pin No. SP3-5M U22 M23 M24 N23 J22 K21 K22 L21 M21 U24 R24 P24 T27 N29 M29 N25 N26 J23 R21 P25 K24 L23 L24

FPGA Pin No SP3-PCI AC13 AF9 AE9 AF8 AE8 AE7 AF6 AE6 AE5 AC18 AD20 U3 AD3 AE3 AB4 AA3 Y4 W4 AD16 Y3 AF11 AE11 AE10

FPGA Pin No VIRTEX-4 P20 R24 P22 R23 T24 T21 U22 U21 J20 W21 V22 AA24 V23 U24 L23 L24 M23 N23 Y21 M24 N24 P24 P23

FPGA Pin No VIRTEX-5 Y12 U21 W21 Y22 Y21 AA22 T19 U20 U19 AB17 AB19 AB20 AB24 AA24 T23 U24 V24 W24 AA15 V23 W23 T22 U22

86