CHAPTER 5: BUS SYSTEM

INTRODUCTION
Bus System Bus A communication pathway connecting two or more devices Connects the CPU with main memory and other system components Devices other than the CPU and primary storage Common timing reference for all attached devices Rate at which data is transmitted through a medium or communication channel, as a measurement in data units per time interval The format, content and timing of data, memory addresses and control messages sent across the bus

Peripheral Devices Bus Clock Pulse Data Transfer Rate

Bus Protocol

INTERNAL and EXTERNAL BUSES

Internal Bus Located within a CPU chip Communicate among the components in a CPU chip Outside a CPU chip for connecting the rest of the system components of the CPU Supported by third-party hardware and software

External Bus

System Bus consists of

Address Bus Data Bus Control Bus Used to transfer address from PC to memory Carry data, instruction and address between main memory and ALU Carry signals such as interrupt, timing and acknowledgment to and from other components

Problems with Single Bus

Many devices may share one single bus for their operations This may lead to Propagation Delay Propagation Delay is the time taken for a signal to travel from a point of input to a point of output Results with be measured in microseconds, nanoseconds, etc Propagation delay has impact on the speed at which the output is received

Bus Hierarchy
The Processor Bus This is the highest-level bus that is used to send information to and from the processor Higher-level architectures employ a dedicated bus for accessing the system cache This is a second-level system bus that connects the memory subsystem to the processor This is a high-speed input/output bus used for connecting performancecritical peripherals to the memory and processor Used for slower peripherals (mice, modems, regular sound cards, lowspeed networking) and also for compatibility with older devices

The Cache Bus

The Memory Bus

The Local I/O Bus

The Standard I/O Bus

Data, Address and Control Bus Bus Width

Bus Speed

Bus Bandwidth

Every bus will have these three components The number of bits that can travel in parallel along the bus The wider the bus, the better it is since more data can flow at one time How many bits can be sent within a second How fast the bits are flowing through the bus Also known as throughput which refers to the total amount of data that can be transferred on the bus in a given unit of time Measured in Bits per second or bytes per second Bandwidth = Bus Speed x Bus Width

PERFORMANCE OF A BUS
Transfer Time Amount of time taken for a data to be delivered in a single transaction Measures the capacity of the bus How much can the bus send at one time

Bandwidth

Bus Standards
Industry Standard Architecture (ISA) Bus Micro Channel Architecture (MCA) Bus The most common bus 8 and 16 bit bus First introduced in 1987 Very slow with limited number of addresses Introduced in late 80s which have 32 bits. Most EISA cards produced were either SCSI or network cards.

Extended Industry Standard Architecture (EISA) Bus

VESA Local Bus (VLB)

The first local bus to gain popularity Used to enhance graphics capability
Most popular local I/O bus Designed to speed up the display of graphics Have these capabilities: Burst Mode During burst mode, the data bus is controlled by one single device to ensure speed in transmitting data It is used in RAM, Hard disk and graphic ports Bus Mastering A feature that allows a control bus to communicate directly with the other components without going through the CPU This allows the CPU to do other tasks while allowing the peripherals to communicate with RAM High Bandwidth Very fast speed

Peripheral Component Interconnect (PCI) Local Bus

Accelerated Graphics Port (AGP)

Used to improve performance for video