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VHDLAMS Modeling and Simulation Support for SoC Design and Implementation of AC Motor Drives

Juan R. Pimentel and Arturo RojasMoreno


Kettering University, 1700 W Third Avenue Flint, Michigan 48504, USA Universidad Tecnologica, corner 28 de Julio Ave. with Petit Thouars Ave., Lima 1, Peru

Abstract This paper details how the VHDLAMS language can be used to support steps I through IV of a six step SoC (system on chip) design and synthesis methodology with high productivity gains. This is because about 80 to 90% of the VHDL code used for synthesis in phases V and VI is the same code developed in phases I through IV with the VHDLAMS language. A case study involving the motor drive of a hybrid electric vehicle is used to demonstrate the details of the methodology. The SoC is a Spartan 3A FPGA of Xilinx. Detailed models, simulations, VHDLAMS code and VHDL synthesis code is included. Index Terms System on chip, system level design, based FPGA motor drive implementation, VHDLAMS.

I. Introduction In some industries, e.g., hybrid electric and electric vehicles, there is a need to design and implement AC motor drives with high performance while optimizing cost [1]. However these systems are complex and designing and implementing them with high productivity gains poses signicant challenges [2]. These challenges are particularly severe if the design and implementation is to be done by junior engineers or even upper classmen engineering students because they do not have enough knowledge and/or experience. To overcome these challenges a design methodology using system level design (SLD) or system on a chip (SoC) has been proposed [3]. For many applications, FPGAs offer advantages over traditional microcontrollers in terms of cost and performance. SLD or SoC implementation of AC motor drives on FPGAs are becoming attractive because of their potential to achieve high performance at a relatively low cost [4]. The system design methodology described in [3] helps to undertake complex projects even by engineers with limited knowledge or experience. This paper details how the VHDLAMS language can simplify the entire process and in fact produce target code that can be directly synthesizable on the FPGA, thus achieving high productivity gains. This is because VHDL, the primary synthesis language used in many designs, is a true subset of VHDLAMS [5]. By using a tool such as SystemVision (from Mentor Graphics), one can begin with VHDLAMS simulations and gradually convert the simulation models to VHDL taking into account the hardware details of the particular FPGA. Thus the nal VHDLAMS code can be directly synthesizable using the FPGA vendor tools. The main elements of AC motor drives are the AC motor, the motor controller, the power inverter, and the inverter
Work on this paper was supported in part by a grant from Mentor Graphics to Kettering University.

ring controller as shown in Fig. 1 that pictures how these components are congured to build the powertrain for a hybrid electric vehicle (HEV). VHDLAMS is a relatively new yet powerful language that is a superset of the widely used simulation and synthesis language VHDL. As such, it has several features that make it advantageous to provide a high level of support to SoC design and implementation methodologies. In this paper, we discuss a number of issues related to the use of VHDLAMS as the primarily language to support the modeling, design, simulation, and implementation of ac motor controllers using FPGAs. The simulation tool is SystemVision that implements VHDL AMS.

Fig. 1. Main components of HEV powertrain.

II. SoC Implementation of AC Motor Drives The objective of the SoC design and implementation of the motor drive is the FPGA design and synthesis of the AC motor controller including the inverter ring controller. A number of authors have proposed the use of a phased approach in the SLD or SoC design methodology such as the one describe in the following consisting of six phases [3]:
Phase I: Behavioral VHDLAMS modeling and simulation. Phase II: Behavioral VHDLAMS architectural modeling and simulation. Phase III: Digital properties modeling and simulation. Phase IV: Synthesizable modeling and simulation. Phase V: Logic Synthesis. Phase VI: Overall nal test, verication, and validation.

Phases I and II aim at modeling the behavior of the entire system in a monolithic fashion and architectural fashion respectively. Whereas phase I is done any which way, phase II introduces structure through architectural components

as shown in Fig. 2. In fact VHDLAMS supports these two phases almost naturally through a behavioral architecture and a structural architecture respectively [5]. The aim of phases I and II is to obtain an intuitive understanding through modeling and simulation independently of the implementation platform. Thus, phases I and II are useful even if the implementation is done with microcontrollers or other means other than FPGAs. Whereas phases I and II are independent of the implementation, phases III and IV are specic to the synthesis platform and details of the specic FPGA are necessary for their completion. In this paper, we are using the Xilinx Spartan 3A FPGA, thus a great deal of the details are specic to this SoC. Nevertheless, phases III and IV are still in the modeling and simulation domain. Thus, although the details correspond to a specic FPGA, they are still general models that can be executed in any VHDLAMS tool such as SystemVision.

II of the design methodology then gradually convert the VHDLAMS models into a pure VHDL model by replacing the analog components with equivalent digital components in accordance with the specics of the SoC to be used in the synthesis. Thus, at the end of phase IV we end up with VHDL code specic to the FPGA in question but that can be simulated with a VHDLAMS tool such as SystemVision. This is signicant because in the last phases of the methodology (V and VI) we simply tweak and/or make minor modications to the VHDL code from phase IV to meet tool or design constraints. Such process results in signicant reduction of complexity and high productivity gains. More specically, VHDLAMS is advantageous to support the above SoC design methodology involving HEV components such as ac motors, motor controllers, power inverters, and inverter ring controllers [6]. VHDLAMS is ideally suited for modeling and simulation of phases I through IV because the language supports behavioral models and architectural models. This is advantageous when analyzing the behavior, performance, and architectural properties of a design. VHDLAMS is also ideal for modeling phase III: digital properties modeling and simulation. The synthesizable modeling and simulation step in phase IV involves both digital and analog (e.g., DSP algorithms) components that must be gradually converted to fully digital. In the following we provide details on how VHDLAMS supports phases I through IV of the SoC design methodology. The details are illustrated for the HEV components shown in Figs. 1 and 2. A. VHDLAMS Support for Phase I Phase I of the SoC design methodology basically involves the use of top level behavioral models in VHDLAMS and there are many examples in textbooks and websites that illustrate this level of modeling and simulation [5]. The models are simplied to keep the entire simulation simple (e.g., model of an AC motor in synchronous coordinates in the d-q axis) [7]. The emphasis is on an intuitive understanding of the behavior of each component as well as the entire system. In the context of the modeling and simulation of HEV components, this phase is particularly important for the modeling, simulation, and design of ac motor control systems. It is important to keep in mind that this phase is independent from the target implementation (e.g., microcontroller or FPGA), independent of the implementation architecture, and not directly related to synthesis. A.1 Modeling and Simulation of the AC Motor and Motor Controller To illustrate the typical models considered in phase I we provide an example that corresponds to an AC induction motor modeled in actual three phase coordinates (A, B, C) with a FOC (eld oriented control) speed control system modeled in synchronous coordinates (d, q). The operation of the AC motor control system is summarized next. The actual motor speed (VR_V) is subtracted from the reference speed or velocity (V_CND) and the er-

Fig. 2. Architectural constituent components of the motor controller and inverter ring controller.

The nal phases V and VI are no longer modeling and simulation, rather they correspond to the actual synthesis on a specic SoC. These phases are outside the scope of this paper and of a tool such as SystemVision and they are carried out by tools provided by the vendor of the SoC (e.g., ISE from Xilinx). It is important to note the role of modeling and simulation in phases I through IV of the design methodology. In this paper we describe how VHDLAMS can be eectively used in phases I through IV of the design methodology to achieve high productivity gains. This is because about 80 to 90% of the VHDL code used for synthesis in phases V and VI is the same code developed in phases I through IV in VHDLAMS. III. Role of VHDLAMS in the Design Methodology As noted, VHDL-AMS can be eectively used to support phases I through IV of the SoC design methodology. The main idea is to start with a behavioral and architectural VHDLAMS model of all HEV components in phases I and

ror signal (V_ERR) is used as the input to the PI controller. The output of the PI controller (IEQS) represents the reference current iq . A transformation is used to convert from synchronous coordinates iq (IEQS) and id (IEDS) to stationary coordinates ISA, ISB, and ISC. The motor model accepts three-phase motor currents in stationary coordinates to generate angular velocity , motor shaft angle , and torque. The graphical depiction of the model in SystemVision is shown in Figs. 3 and 4. The results of the simulation is depicted in Fig. 5 showing the reference and actual motor speed on the top (w_cnd and w_r), followed by the synchronous currents ieds and ieqs, and followed by a superposition of the three phase stationary currents of the motor isa, isb, and isc. B. VHDLAMS Support for Phase II In phase II, structure is introduced to what is modeled in phase I by means of an architecture, its constituent components, and interfaces between components. In this phase, the component interfaces of the architecture are carefully dened. The overall system is decomposed into constituent architectural components related to nal implementation but still independent from the target implementation (e.g., microcontroller or FPGA) and independent from synthesis. To illustrate this phase, we provide results of an architectural model that corresponds to the power inverter and power inverter ring controller of Fig. 2. The architectural model that includes the motor but not the motor controller is shown in Fig. 6. The inverter is a standard 3leg, 6 switch power inverter that drives the three inputs of the three phase AC motor. Two types of inverters can be modeled: ideal switch and IGBT switch. Fig. 7 shows an inverter model based on ideal switches. The inputs to the model are the three digital control signals SA, SB, and SC, while the outputs are the three phase motor stator voltages VA, VB, and VC. The power inverter accepts a generic DC battery voltages of E volts.

Fig. 4. SystemVision model of a FOC for an induction motor (Right portion).

B.1 Modeling and Simulation of the Power Inverter

Fig. 5. Simulation results for the SystemVision model of a FOC for an induction motor.

Fig. 6. Test bench for testing the inverter ring controller, power inverter, and motor.

B.2 Modeling and Simulation of Inverter Firing Controller We have developed a generic model for the inverter ring controller that is capable of working with a wide variety of power inverters that includes an arbitrary number of samples of the sinusoidal signals (variable frequency). The initial simulations use the standard sixstep inverter based on

Fig. 3. SystemVision model of a FOC for an induction motor (Left portion).

of 124.85 rad/s but has a signicant high frequency ripple due to high frequency harmonics of the switched voltages given by the inverter. This high frequency noise needs to be reduced by proper control methods.

Fig. 7. Details of the ideal switch model of the power inverter.

6 samples per period. As depicted in Fig. 2, the inverter ring controller consists of two blocks, the pulse control block and the PWM control block. Whereas the latter block calculates the duty cycles (i.e., widths) and the timing, the pulse control block actually generates the digital control signals Sa, Sb, and Sc,. The inverter ring controller uses the following as input parameters in their calculations: Inverter DC voltage E, motor frequency f , sampling period Ts , motor speed , and rotor angle . The inputs to the inverter ring controller are the voltage outputs generated by the control algorithm block. The three-phase duty cycles are: T T T D = D = D = (1) Ts Ts Ts where T = Ta + T b + T c Vref E Vref E T = Tb + To 2 T = To 2 (2)

Fig. 8. Waveforms of test experiment depicting Sa , Sb , Sc , Va , Vb , and motor speed r .

C. VHDLAMS Support for Phase III Since the nal FPGA design is digital in nature, we begin by modeling and simulating the digital properties of the synthesizable design in phase III. This is important because the VHDLAMS model at the end of phase II contains both digital and analog components. We need to gradually replace the analog components with digital components taking into account the detailed characteristics of the target SoC. Of course the exception is the analog components that correspond to physical devices such as the motor or the power inverter which do not need to be synthesized by a SoC. A SoC device such as an FPGA is a purely digital system and any analog component must be provided externally to the FPGA. For example, the Xilinx Spartan 3A device needs external devices for analog to digital conversion, providing outputs for a video monitor, or driving communication channels such as Ethernet or CAN. The typical digital properties considerations in this phase include whether an embedded processor is to be used (e.g., microblaze of Power PC), the accuracy of the analog to digital converters, whether xed point or oating point is to be used for signal processing, the accuracy of the calculations, and the digital architecture of the digital DSP calculations. For example, Figs. 9 and 10 correspond to the entity and architectural model of two analog to digital converters available on the Spartan 3A. Note that the detailed models consider actual hardware items such as clock (i.e., aclk_i) and reset (rst_i) pins. The architecture rt1 of the entity a dc_interface has three processes: clk_gen, conv_ctrl, and data_read. For space considerations, only portions of the the data_read process is detailed. Note that the nal digital 12 bit representation of the converted analog signals ch0_s, and ch1_s are read from a long shift register named shift_reg_s.

Ta Tb

= =

3Ts sin(/3 ) 3Ts sin Tc = Ts Ta Tb (3)

and Vref is the magnitude of the three phase reference voltages (Va , Vb , Vc ) given by the motor control algorithms. For example, for the open loop system of Fig. 6, with f = 20 Hz, T = 0.05 sec, E = 200 V, Vref = 43.478 V, Ts = T /6 = 8.333 ms, the width of the PWM signals Ta , Tb , and Tc with their corresponding duty cycles are given in Table I.
TABLA I Width of the three-phase PWM waveforms Ta 0.003138 Tb 0.003138 Tc 0.002058 Duty Cycle D 0.876533 Duty Cycle D 0.5 Duty Cycle D 0.123467

The simulation results are shown in Fig. 8 where we can see validated waveforms for Sa , Sb , and Sc on the top, followed by two of the three phase voltages given by the power inverter (Va and Vb ), and followed by the motor speed r . It can be noticed that the motor speed has an average value

entity adc_interface is port ( clk_i : in std_logic; rst_i : in std_logic; sck_o : out std_logic; ad_conv_o : out std_logic; sdo_i : in std_logic; ch0_o : out std_logic_vector(11 downto 0); ch1_o : out std_logic_vector(11 downto 0) ); end; -- entity adc_interface Fig. 9. Analog to digital conversion entity. architecture rtl of adc_interface is signal ad_conv_s : std_logic; signal ch0_s : std_logic_vector(11 downto 0); signal ch1_s : std_logic_vector(11 downto 0); signal clk_cntr_s : std_logic_vector(7 downto 0); signal conv_cntr_s : std_logic_vector(11 downto 0); signal rd_cntr_s : std_logic_vector(7 downto 0); signal sck_fe_s : std_logic; signal sck_q1_s : std_logic; signal sck_re_s : std_logic; signal sck_s : std_logic; signal shift_reg_s : std_logic_vector(33 downto 0); begin -- rtl -- Drive output ports. sck_o <= sck_s; ad_conv_o <= ad_conv_s; ch0_o <= ch0_s; ch1_o <= ch1_s; -- ADC Clock Generation -clk_gen : process (clk_i, rst_i) is constant clk_tmo_c: std_logic_vector(7 downto 0):=x"18"; begin -- . . . end process; -- clk_gen -- Conversion Control -conv_ctrl : process (clk_i, rst_i) is constant conv_tmo_c: std_logic_vector(11 downto 0):=x"1FF"; begin -- . . . end process; -- conv_ctrl -- Data Read -data_read : process (clk_i, rst_i) is constant rd_tmo_c: std_logic_vector(7 downto 0):=x"22";--34 begin if (rst_i = 1) then rd_cntr_s <= rd_tmo_c; shift_reg_s <= (others => 0); ch0_s <= (others => 0); ch1_s <= (others => 0); elsif (rising_edge(clk_i)) then -- Load read counter when a conversion is commanded. --- Shift ADC data into shift register and read data -if (sck_fe_s = 1) then if (rd_cntr_s /= 0) then shift_reg_s <= shift_reg_s(32 downto 0) & sdo_i; end if; end if; if (sck_fe_s = 1) then if (ad_conv_s = 1) then ch0_s <= shift_reg_s(31 downto 20); ch1_s <= shift_reg_s(15 downto 4); end if; end if; end if; end process; -- data_read end rtl; Fig. 10. Portions of the analog to digital conversion architecture.

D. VHDLAMS Support for Phase IV In this phase, the VHDLAMS model of phase II is completely converted to VHDL (i.e., from a combination of digital and analog to a strictly digital model) taking into account the modeling considerations of phase III. Thus, this phase is target dependent as it takes into consideration, for example, how a specic SoC converts analog to digital, the nature and speed of clock signals, the hardware initialization handshake, PWM channels, synchronization signals, and data buering. For example, Fig. 11 shows a listing of the pwm entity in VHDLAMS used for generating a PWM signal on the Spartan 3A. The corresponding architecture rt1 that implements the way the PWM signal is actually generated is listed in Fig. 12.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity pwm is port ( clk_i : in std_logic; rst_i : in std_logic; f3_i : in std_logic_vector(11 downto 0); fout_o : out std_logic ); end; -- entity pwm Fig. 11. Denition of the pwm entity. architecture rtl of pwm is signal duty_s : std_logic_vector(11 downto 0):= x"FFF"; signal fout_s : std_logic := 0; signal pwm_cntr_s: std_logic_vector(11 downto 0) := x"FFF"; signal pizza: std_logic_vector(10 downto 0):= "11111111111"; signal pancake : std_Logic_vector(11 downto 0):=x"FFF"; begin -- rtl fout_o <= fout_s; pwm_ctrl : process (clk_i, rst_i) is begin if (rst_i = 1) then pwm_cntr_s <= (others => 0); duty_s <= (others => 0); fout_s <= 0; elsif (rising_edge(clk_i)) then pwm_cntr_s <= pwm_cntr_s+1; if (pwm_cntr_s = 0) then duty_s <= f3_i; end if; --- Initialize the PWM output when the counter rolls over pizza <= x"7FF" - duty_s(11 downto 1); pancake <= 0 & pizza; if (pwm_cntr_s = pancake) then fout_s <= 1; elsif (pwm_cntr_s =(x"FFF" - pancake)) then fout_s <= 0; end if; end if; end process; -- pwm_ctrl Fig. 12. Portions of the architectural implementation of the pwm entity.

E. VHDLAMS Support for Phases V and VI There is no direct support of VHDLAMS for phases V and VI as these phases are done using the tool provided by the SoC vendor (e.g., ISE of Xilinx). As noted, if all previous phases are done correctly, then about 80 to 90% of the synthesizable VHDL code in phases V and VI are obtained from executing phases I through IV. As such, phases V and VI are outside the scope of this paper.

IV. Discussion The complexity of the simulation, design, and implementation of a HEV powertrain is well acknowledged. Successfully designing a complete HEV powertrain requires extremely knowledgeable people with a great deal of experience. The needed resources in terms of time, devices, components, and qualied personnel is high thus resulting in a low productivity gain. The challenge is to successfully complete and test a design with personnel having an average level of knowledge and experience and in a shorter timeframe, thus increasing signicantly the productivity gains. If this is accomplished, then it would be easier to complete designs in a shorter time frame with less experienced personnel resulting in lower costs. The methodology used in this paper has been proven effective in reducing the complexity of the design and implementation of HEV components and achieving productivity gains. One of the main advantages of the methodology is that the code developed through modeling and simulation using the VHDLAMS language through phases I to IV is the nal target code (with minor editing) used to synthesize the FPGA. Thus, another outcome of using the methodology is that it results in software reuse. Since the design is architectural, the various elements can be easily changed resulting in an extremely exible, modular, and scalable system. The modular approach makes it easy for large teams working on various aspects of a typical project, e.g., hardware, wiring, software, communications, testing, validation, and system integration working almost simultaneously. But the methodology only works if appropriate models and tools are available. In this paper we have presented models in the VHDLAMS language well supported by the tool SystemVision of Mentor Graphics. The simulation can be done at various levels of accuracy but requires additional modeling eort and simulation time. The cost, speed, and performance of FPGA based controllers is promising, particularly for playing an important role in the electronics of HEVs. The testing of individual components and the entire system is simplied (e.g., testing the ADC or PWM ) because they can be tested via simulation, before they are synthesized. Of course the actual components and nal system needs to be thoroughly tested but this process is simplied by the testing done in simulation mode. Vendor tools used in phases V and VI (e.g., ISE) also have some powerful simulation features. But these synthesis and simulation tools lack analog features and they cannot be used for simulating the entire system including the power inverter, battery, and motor. Having analog features and the capability of simulating components other that what is synthesized is perhaps the main advantage of the VHDLAMS language and associated tools in the context of the SoC design methodology. In this paper, we have extended the use and advantages of VHDLAMS modeling and simulation to directly support SoC synthesis on target systems.

V. Summary and Conclusions The use of VHDLAMS in the context of a SoC design methodology can be eective in reducing and managing the complexity involved in the overall SoC design and implementation of entire systems such as an AC motor drive. More specically, in the case study presented, VHDLAMS has simplied most steps in the SoC design methodology giving the designer condence in all phases of the design. In addition it has helped to test, verify, and validate the entire design before implementation. At the implementation stage it has helped to design and validate the digital portion of the SoC synthesis (e.g., the inverter ring controller). One of the main advantages of the methodology is that the code developed through modeling and simulation in the VHDLAMS language through phases I to IV is the nal target code (with minor editing) used to synthesize the FPGA. One advantage of simulation is that it gives considerable freedom to try a variety of algorithms, architectures, models, design properties, implementation properties, tradeos thus oering the possibility of improving or optimizing designs and saving considerable time. Acknowledgements The authors thank the assistance provided by Kevin Klopfenstein of Xilinx and Mike Biggs of Avnet with some FPGA programming aspects of phases III and IV. Additional thanks go to D. Teegarden and S. Cooper from Mentor Graphics for their help on VDHLAMS programming aspects. In addition, the great eort by the following Kettering University students: Anthony Lane, Tim Masters, Nathan Nephew, Brett Ponton, Barry Troxell, and Kurt Wachowski who participated in a capstone senior design project that used the methodology described in this paper, is also acknowledged. References
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