Low Power high speed 16x16 bit multiplier using Vedic Mathematics

R.K. Bathija, R.S. Meena, and S. Sarkar

Abstract: A simple digital multiplier (henceforth referred to as Vedic multiplier) method is that the power dissipation of this circuit is 0.17 mW. & propagation
architecture based on the Urdhva Tiryakbhyam (Vertically and Cross wise) Sutra of delay of the proposed architecture is 27.15ns. These results are improvements Vedic Mathematics is presented. An efficient technique for low power and high speed over power dissipations and delays reported in literature for Vedic and Booth multiplier of two binary numbers (16 bit each) is developed. An algorithm is proposed Multiplier. and implemented for 16nm CMOS technology. The designed 16x16 bit multiplier dissipates a power of 0.17 mW. The propagation time of the proposed architecture is 27.15ns. These results are improvements over power dissipations and delays reported in literature for Vedic and Booth Multiplier. In the section 2 introduction of the method will be discuss, with the description of the sutra, steps of multiplication. In section 3 design of the 16x16 bit multiplier with the basic building blocks like 2x2 bit Multiplication, 4x4 bit multiplication, 8x8 bit multiplication. In section 4 we state the comparison of different multiplier. In section 5 we conclude. 2. Introduction to Proposed Technique: A. Urdhva Triyagbhyam Sutra The basic sutras and upa sutras in the Vedic Mathematics helps to do almost all the numeric computations in easy and fast manner[3]. The sutra which we employ in this project is Urdhva Triyagbhyam (Multiplication). B. Description of Sutra This is the general formula applicable to all cases of multiplication [3]. Urdhva Triyagbhyam means Vertically and Crosswise, which is the method of multiplication followed.

Keywords: Vedic Mathematics, Urdhva Tiryakbhyam, Power consumption,

Propagation delay. 1. Introduction: The ancient system of Vedic Mathematics was rediscovered from the Indian Sanskrit texts known as the Vedas, between 1911 and 1918 by Sri Bharati Krsna Tirthaji (1884-1960) from the Atharva Vedas. According to his research all of mathematics is based on sixteen Sutras, or word-formulae. These formulae describe the way the mind naturally works and are therefore a great help in directing the student to the appropriate method of solution. In the Vedic system 'difficult' problems or huge sums can often be solved immediately by the Vedic method. These striking and beautiful methods are just a part of a complete system of mathematics which is far more systematic than the modern 'system'. Vedic Mathematics manifests the coherent and unified structure of mathematics and the methods are complementary, direct and easy. Vedic Mathematics is the branch of mathematics which involved certain tricks to solve the problem of arithmetic operations and also advance mathematics problems (solving differential equation, etc.) with a little bit of effort. In this paper a simple digital multiplier is proposed which is based on Urdhva Triyagbhyam (Vertically Crosswise) sutra of the Vedic Maths. Two binary numbers ( 16-bit each) are multiplied with this sutra. The potential of this

Illustration: 12 * 24 12 24 ---------------------2: 4+4: 8 = 288

-----------------------Steps: i. We multiply the left-hand-most digit 1 of the multiplicand vertically by the left-hand-most digit 1 of the multiplier, get their product 1 and set it down as the left hand-most part of the answer. ii. We then multiply 1 and 3, and 1 and 2 crosswise, add the two, get 5 as the sum and set it down as the middle part of the answer; and iii. We multiply 2 and 3 vertically, get 6 as their product and put it down as the last right-hand-most part of the answer. Thus 12 * 24 = 288 For Binary Illustration: 11 * 10 11 10 ---------------------1; 1+0; 0 = 110 (result) ---------------------Steps: i. Multiply LSBs (Least Significant Bits) 0 and 1; place product 0 as LSB of the result: Vertical Multiplication ii. Multiply Crosswise 1 and 1; 0 and 1; add the product terms and place obtained sum as middle term of the result: Crosswise Multiplication iii. Multiply the MSBs (Most Significant Bits) 1 and 1; place product 1 as MSB of the result: Vertical Multiplication 3. DESIGN OF THE 16X16 MULTIPLIER A. The Fundamental Block (22 block)

In the design of the proposed Vedic multiplier a 22 block is a fundamental block (Basic block) is shown in fig 1. Also symbol of this fundamental block is shown to be used in 4 x 4 bit Multiplier. We know that in binary multiplication basically we AND each two bits in 2-input AND gate. First off all vertical bits (LSBs) are anded this will result in the LSB of the result. Than we and crosswise bits and than result is added using a half adder. The sum output of the half adder is the next bit of the result right to the LSB. The carry output is also added in half adder with the AND output of the MSBs. The carry of this adder is the MSB of the result. The waveforms of input and output of 2-bit multiplier using Urdhva Tiryakbhyam sutra of Vedic mathematics is shown in figure 2. Power dissipation of this multiplier is 23.2 W and propagation delay is 1.51 nsec. 62 transistors are used in this design.

A1 AND GATE

B1

A1

B0 A0

B1

A0

B0

AND GATE

AND GATE

AND GATE P0

Half Adder P1 Half Adder 4-BIT P3 P2

2Bit Mul

Figure1) 2 x 2 Bit Multiplier and & its symbol

bit-pair is handled by a separate 22 Vedic multiplier to produce four partial product rows. These partial products rows are then added in a 4-bit carry lookahead adder optimally to generate final product bits. The figure 3 shows the schematic of a 44 block designed using 22 blocks. The partial products represent the Urdhva vertical and cross product terms. Then using or and half adder assembly to find the final product. Power dissipation of this multiplier is 0.18 mW and propagation delay is 1.71 nsec. 618 transistors are used in this design.

B3B2A 3A2 2-BIT MUL

B1B0A 3A2 2-BIT MUL

B3B2A 1A0 2-BIT MUL

B1B0A 1A0 2-BIT MUL

P1P0 B A

4-BIT Carry Look Ahead Adder

4-Bit Mul

Figure 2 Input Output waveforms of 2x2 Bit multiplier B. Design of 44 block The design of 44 block is a simple arrangement of 22 blocks in an optimized manner. The first step in the design of 44 block will be grouping the 2 bit of each 4 bit input. These pair terms will form vertical and crosswise product terms. Each input
Half Adder Half Adder P7 P 6

4-BIT Carry Look Ahead Adder 2 BIT OR GATE

P5 P4 P3 P2 A B

4-Bit Mul

Figure 3) 4x4 bit multiplier using 2x2 block with its symbol.

C. Design of 88 block The design of 88 block is a similar arrangement of 44 blocks in an optimized manner as in figure 3. The first step in the design of 88 block will be grouping the 4 bit (nibble) of each 8 bit input. These quadruple terms will form vertical and crosswise product terms. Each input bit-quadruple is handled by a separate 44 Vedic multiplier to produce eight partial product rows. These partial products rows are then added in a 8-bit carry lookahead adder optimally to generate final product bits. The figure 4 shows the schematic of a 88 block designed using 44 blocks. The partial products represent the Urdhva vertical and cross product terms. Then using or and half adder Figure 4) 8x8 bit multiplier using 4x4 block with its symbol.
D. DESIGN OF A 1616 MULTIPLIER

The design of 1616 block is a similar arrangement of 88 blocks in an optimized manner as in figure 4. The first step in the design of 1616 block will be grouping the 8 bit (byte) of each 16 bit input. These lower and upper bytes pairs of two inputs will form vertical and crosswise product terms. Each input byte is handled by a separate 88 Vedic multiplier to produce sixteen partial product rows. These partial products rows are then added in a 16bit carry lookahead adder optimally to generate final product bits. The figure 5 shows the schematic of a 1616 block designed using 88 blocks. The partial products represent the Urdhva vertical and cross product terms. Then using or and half adder

B3B2B1B B3B2B1B B7B6B5B B3B2B1B assembly to find the final product. Power dissipation of this multiplier 0A3A2A1 0A3A2A1 0A3A2A1 is 0.035mW and propagation delay is4 1.72 nsec. 3222 transistors are used in this A0 A0 A3A2A1A A0 design. 44440 BIT BIT BIT BIT MUL MUL MUL MUL 8-BIT Carry Look Ahead Adder 8-BIT Carry Look Ahead 2 BIT Adder OR GATE P7P 6P5 P4 P3P 2P1 P0
A B

B15-B8 B15- dissipation B7-B0 assembly to find the B7-B0 final product. Power of this multiplier is B8 nsec. 618 transistors A7-A0 0.18 mWA15and propagation A15delay is 1.71 are used in this
design. 8-

A8

BIT MU L

Half Adde r ASSE MBLY

P11P 10P9 P8

8-Bit Mul

Half Adde r ASSE MBL Y

A8 A7-A0 88BIT BIT MU MU L L 16-BIT Carry Look Ahead Adder 16-BIT Carry Look Ahead 2 BIT Adder OR GATE P1 5P8

8BIT MU L

P 7P 0
B

P3 1P1 6

16Bit Mul

Figure 5) 16x16 bit multiplier using 8x8 block with its symbol. 4. Conclusion The proposed Vedic multiplier (discussed in section 3) is simulated using Tanner Tool v14.1. The Comparison between proposed multiplier and Booth radix-4 multiplier and the multiplier in [1] is shown in table I. Schematic from SEdit is shown in figure 6. Table I Comparison of 16x16 bit multipliers

S. No. Parameter My of design Papers Booth design 1 2 3 comparison algorithm Delay (ns)27.14865 37.66846.740 Power (mW) 0.1692638 29.34 Transistors used Figure 6) Schematic Diagram of 16 x 16 bit multiplier using SEdit

151.34

14382 4299 7296

References 1. Scripture E.W. (1891) American Journal of Psychology, Vol. IV 1-59 2. Mitchell F.D. (1907) American Journal of Psychology, Vol. XVIII 61-143 3. Williams K.R. (1991) The Natural Calculator, Inspiration Books