ENGR 298

Successive Approximation Analog to Digital Converter

Presented to Ali M. Zargar On April 30, 2010

By Team Number 7 Nila Barot

Committee Members Faculty Reader Prof. Morris Jones, Retired from Intel Corp. Industrial Sponsor Srenik Mehta, Atheros Comm.
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2010 Nila Barot ALL RIGHT RESEREVED

APPROVED FOR THE GENERAL ENGINEERING DEPARTMENT

Morris Jones

Srenik Mehta

__________________________________________ Ali M. Zargar

APPROVED FOR THE UNIVERSITY

ABSTRACT

This master project report contains implementation of design and economic justification of SAR ADC. The main motivation is to implement design of capacitor array DAC and achieve high speed with medium resolution using 45nm technology. The current SAR architecture has in built sample and hold circuit, so there is significant saving in chip area. The other advantage is matching of capacitor can be achieved better then resistor. The market and cost analysis says current SAR ADC has better future.

ACKNOWLEGEMENT

Writing and implementing this master project was a very rewarding for me. I would like to say thanks to my project guides Prof. Morris Jones and Srenik Mehta for their guidance and support for design the SAR ADC using capacitor array DAC. I would like to say thanks to Prof. Ali Zargar for his direction to planning and writing this master project report. Finally, thanks to the readers of this project report for their suggestions and comments.

Contents
1. Introduction...............................................................................................................................................8 1.1 Selection of the right ADC architecture.............................................................................................. 8 1.2.1 SAR ADC Architecture................................................................................................................... 8 1.2.2. Advantages and limitations............................................................................................................. 9 1.3 VNB company.................................................................................................................................10 2. Objective.................................................................................................................................................10 2.2 Summary of phenomena................................................................................................................... 10 2.3 Description of Internal Major Blocks............................................................................................... 12 2.3.1 Design of Capacitor array DAC................................................................................................. 12 2.3.2OperationforbinaryweightedcapacitorarrayDAC.................................................................13 2.3.3 SAR Logic.................................................................................................................................17 2.3.4 Design of Comparator................................................................................................................ 18 2.4.1 Experimental Procedures............................................................................................................... 23 2.4.1.1Staticparameters.................................................................................................................... 24 2.4.1.2 Dynamic parameters............................................................................................................... 24 2.4.2 Resources Utilized......................................................................................................................... 25 2.4.3 Project Schedule ............................................................................................................................. 25 3. Literature Survey....................................................................................................................................26 4. Economic Justification............................................................................................................................ 28 4.1 Executive Summary.......................................................................................................................... 28 4.2. Market Survey..................................................................................................................................28 4.3. Current SAR ADC........................................................................................................................... 33 4.4 Cost Survey.......................................................................................................................................34 5. Applications of Data Converters............................................................................................................. 35 6. Cost Analysis..........................................................................................................................................36 6.1 Human Resources............................................................................................................................. 36 6.2 Product Cost......................................................................................................................................37 6.3. Product Revenue.............................................................................................................................. 38 6.4 Breakeven Analysis.......................................................................................................................... 39 6.5 Profit & Loss Analysis...................................................................................................................... 42 6.6 SWOT Assessment........................................................................................................................... 44 6

7. Relevance of core courses....................................................................................................................... 45 8. Conclusion..............................................................................................................................................46 9. Future Work............................................................................................................................................46

1. Introduction 1.1 Selection of the right ADC architecture The selection of the right architecture is a very crucial decision. The following figure 1 shows the common ADC (Analog to Digital Converter) architectures, their applications, resolutions and sampling rates. Sigma Delta ADC architectures are very useful for lower sampling rate and higher resolution (approximately 12-24 bits). The common applications for Sigma-delta ADC architecture are found in voice band, audio and industrial measurements. The Successive Approximation (SAR) architecture is very suitable for data acquisition; it has resolutions ranging from 8bits to 18 bits and sampling rates ranging from 50 KHz to 50 MHz. The most effective way to create a Giga rate application with 8 to 16 bit resolution is the pipeline ADC architecture. (Kester, W. 2005, June)

Figure 1 ADC architecture, applications, resolution, and sampling rates. (Kester, W. 2005, June) 1.2.1 SAR ADC Architecture The SAR architecture mainly uses the binary search algorithm. The SAR ADC consists of fewer blocks such as one comparator, one DAC (Digital to Analog Converter) and one control logic.
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The algorithm is very similar to like searching a number from telephone book. For example, to search a telephone number from telephone book, first, the book is opened and the number may be located either in first half or in the second half of the book. Further, relevant section is divided into half. This procedure can be followed until finding relevant number. (Moscovici, A. 2001)

Figure 2 Block diagram of SAR ADC which has a capacitive DAC, a comparator and a digital logic ( BP Ginsburg, A. C. 2007). 1.2.2. Advantages and limitations The main advantage of SAR ADC is good ratio of speed to power. The SAR ADC has compact design compare to flash ADC, which makes SAR ADC inexpensive. The physical limitation of SAR ADC is, it has one comparator throughout the entire conversation process. If there is any offset error in the comparator, it will reflect on the all conversion bits. The other source is gain error in DAC. However, the static parameter errors do not affect dynamic behavior of SAR ADC. Furthermore, higher the speed, it is difficult to obtain the dynamic behavior of ADC. One solution is to use time-interleaved converters. (Moscovici, A. 2001)

1.3 VNB company

Currently, VNB Company has one student engineer named Nila Barot and two expert guides Prof. Morris Jones (Ex. VP of Intel) and Srenik Mehta (Director of Analog Design at Atheros). Data convertor is major product of company. Company has started business during year 2009, and currently company has implemented the SAR ADC design. Furthermore, performance testing of SAR ADC is under progress.

2. Objective The Data Converters are widely used in wireless communication, digital audio and video applications. There are many kind of ADC such as flash ADC, Integrating ADC, pipeline ADC and SAR ADC. The SAR ADC can be build using resistor string DAC or Capacitor array DAC. The current SAR ADC design uses capacitor array DAC using 45nm CMOS (Complementary Metal oxide Semiconductor) technology. (BP Ginsburg, A. C. 2007) 2.2 Summary of phenomena The main goal of this project is to design a successive approximation (SAR) ADC using binary weighted split capacitor array DAC. The basic algorithm of binary search is to convert analog signal into digital signal/quantized form. The conversion process starts after discharging the capacitors. During sampling mode capacitor array is charged by vIN (input voltage). During charge redistribution mode, MSB (Most Significant Bit) set to one and remaining bits set to zero. The MSB capacitor is charge to Vref (Reference Voltage). If Comparator output is high, bottom plate of MSB capacitor remains connected to Vref. On the other hand, if comparator output is low, the MSB capacitor connects to the ground. The conversion process continue for the next largest MSB same way, and the second largest capacitor charges to Vref while the remaining LSB (Least Significant Bit) capacitor array connect to the ground. If the comparator output is high, the second largest MSB capacitor connects to Vref otherwise it connects to the ground.

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This process continues until the last conversion. The figure 3 shows the logic over view of SAR ADC, where Vx is voltage at top plate of capacitor

Discharge

Vx=VCM

Sample

Vx=VCM

Hold Bitcycle Start

Vx=Vin+VCM

Vx=Vin+VCM+Vref/2

N Vx>VCM?

Bitchanged toZero

Y Bi=0 Vx=Vx+Vref/ 2^(i+1) Bi=1 Vx=VxVref/ 2^(i+1)

Bitremain Unchanged

I=i+1,Bi=1

>N

Y Stop

Figure 3. Logic over view of SAR ADC

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2.3 Description of Internal Major Blocks As mentioned in summary of phenomena, the SAR ADC consists of three major blocks such as a comparator, a successive approximation register (SAR), and a DAC. The current SAR ADC builds using following blocks: Capacitor array DAC Comparator Control logic.

2.3.1 Design of Capacitor array DAC The conventional binary weighted capacitor array has limitation for higher resolution due the larger capacitor ratio from MSB capacitor to LSB capacitor. To eliminate this problem, one technique can be applied known as split capacitor technique. (BP Ginsburg, A. C. 2007). For example, to achieve the 8bits resolution, the capacitor array can be splited as shown in following figure 4. The attenuation capacitor divides the LSB capacitor array and MSB capacitor array. Here, the ratio between LSB to MSB capacitor (C to 8Cc) reduces drastically compare to the conventional binary weighted capacitor array (C to 128C). (Baker, J. R., Li, H. W., & Boyce, D. E.1998)

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AttenuationCapacitor

16/15C

2C

8C

2C

4C

8C

VCM Vin Vrefn

Vrefp

Figure 4. Split capacitor array DAC for 8 bits resolution (Baker, J. R., Li, H. W., & Boyce, D. E., 1998)
2.3.2OperationforbinaryweightedcapacitorarrayDAC

The capacitor array works in four different phases such as Discharge Sample Charge transfer (Hold) Charge redistribution

The following paragraphs describe all the phases in detail.

2.3.2.1Dischargephase

During discharge phase, comparator act as unity gain buffer as shown in figure 5, and the reset switch is on. All bottom plates of capacitor array are connected to VCM. (In this case 0.5V),

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hence voltage across capacitor plate are zero. As shown in figure 5, Vx is voltage at top plate of capacitor array, and VCM is common mode voltage.

2C

VCM

VCM

Figure 5. Discharge phase

2.3.2.2Samplingphase

During sampling phase bottom plates of capacitor array are connected to Vin as shown in figure 6. The reset switch still on hence the top plate is on VCM; and voltage across capacitor array is Vin-VCM.

2C

Vin

VCM

Figure 6. Sampling Phase

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2.3.2.3Chargetransfer/Holdphase

During Charge transfer phase, bottom plates of capacitor array are switched to VCM and top plates are floating as shown figure 7. In this phase, reset switch is off. Hence, Voltage at top plate Vx, which is as follows: Vx= VCM - (Vin-VCM) = -Vin. For example: Vin = 0.7V Vx=0.5- (0.7-0.5) =0.5-0.2=0.3V

2C

VCM

VCM

Figure 7. Charge transfer Phase

2.3.3.4Chargeredistributionphase

During the Charge redistribution phase, first the MSB is set to high, and the bottom plate of MSB capacitor is connected to Vrefp (Reference voltage Positive) (In this case 1V) as shown in figure 8. The other remaining bits are set to zero, hence bottom plates of these capacitors are connected to Vrefn (Reference voltage Negative) (In this case GND). If the comparator output is high, the MSB reset to high and bottom plate of MSB capacitor remains connected to Vrefp. If

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Comparator output is low, the bottom plate of MSB is then connected back to the GND. The voltage at top of the capacitor array Vx is: Vx = -Vin + Vos + D N-1 * (Vrefp/2) = 0.3 + Vos+ 1*(1/2)* 1(for time being Vos=0) =0.8 V

2C Vrefp 2C

VCM Vrefn

Figure 8. Charge redistribution phase (MSB set to High) Then, the next largest capacitor is tested in the same manner clearly shown in figure 9. The conversion process continues until the last bit. (Baker, J. R., Li, H. W., & Boyce, D. E. 1998)

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2C Vrefp

2C

2C VCM Vrefn Vrefn

Figure 9. Testing second largest bit during charge redistribution phase

2.3.3 SAR Logic SAR logic is purely a digital circuit, and it consists of three major blocks; Counter Bit register Data register

The counter provides timing control and switch control. For 8 bits conversion, seven DFFs (D flip-flops) are used. The following table 1 explains which bit set to high during different phases of SAR operation. Phase Discharge/Reset Sample/ Reset q0 0 1 q1 0 0 q2 0 0 q3 0 0 q4 0 0 q5 0 0 q6 0 0

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Hold (charge Transfer) Test7 Test6 Test5 Test4 Test3 Test2 Test1 Test0 Unused EOC (end of conversion) [D7] [D6] [D5] [D4] [D3] [D2] [D1] [D0]

1 1 1 1 1 1 0 0 0 0 0

1 1 1 1 1 1 1 0 0 0 0

0 1 1 1 1 1 1 1 0 0 0

0 0 1 1 1 1 1 1 1 0 0

0 0 0 1 1 1 1 1 1 1 0

0 0 0 0 1 1 1 1 1 1 1

0 0 0 0 0 1 1 1 1 1 1

Table 1. Control of switches during different four phases

2.3.4 Design of Comparator 2.3.4.1 Characterization of a comparator A comparator is a circuit, which has a binary output and its value is based on a comparison of two analog inputs. The output of the comparator is high (VOH) when the difference between the non inverting and the inverting inputs is positive. The output is low (VOL) when the difference is negative, which clearly shown in figure 10. This is an ideal behavior of comparator, which is impossible in a real time.

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Figure 10. Ideal Transfer curve of comparator (Anonymous) Ideally, output of comparator is defined as follows:

Practically, comparator cannot achieve infinite gain; hence, the output is defined as follows:

(Anonymous)

Figure 11. Transfer curve of comparator with finite gain (Anonymous)

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Another important characteristic of comparator is slew rate. If the input voltage is larger which will results into a smaller delay time. However, it has upper limit. (Philips E. Allen 2002) Another non- ideal characteristic of comparator is input offset. The output of comparator does not change until the input difference reached the input offset Vos. The figure 12 shows the transfer characteristic of comparator with input offset. The output is defined as follows:

(Philips E. Allen 2002) and (Anonymous)

Figure 12. Transfer curve of a comparator including input offset voltage (Anonymous)

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Figure 13. Ideal Comparator with gain 1000, Vm (0 10 1V), Vp(0.3V) Input voltage Vm varies from 0 to 1V while another input Vp is set nearly 500mV. The result of simulation is shown in figure 14.

Figure 14. Simulation data of ideal comparator with gain 1000

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Furthermore, often a comparator is placed in noisy environment; hence, the output of comparator is noisy. By adding hysteresis into the comparator, better results can be achieved. The hysteresis can be added by adding positive feedback externally or internally. For current SAR ADC internal positive feedback is used. (Philips E. Allen 2002) 2.3.4.2 Regenerative comparator There are many types of comparator such as two stage open loop comparator, discrete time comparator and folded cascade comparator. For current SAR ADC design, discrete time comparator is used. The discrete time comparator works on some portion of time, and it is clock driven. The block diagram of comparator is as shown in figure 15. The first stage is pre amplification stage to amplify the input signal. The second stage is decision circuit or sense amplifier with latch. The current regenerative comparator uses positive feedback for comparison of two signals. The latch works on two phases, one disable the positive feedback and other phase enables the latch. The latch keeps the voltage high or low relative to its value. The last part of comparator is an output buffer. (Baker, J. R., Li, H. W., & Boyce, D. E. 1998), and (Philips E. Allen 2002)

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F r o m c a p a c i t o r

SenseAmplifier Preamplification /DecisionCircuit Postamplification

Figure 15 Three stage Comparator block diagram (Baker, J. R., Li, H. W., & Boyce, D. E., 1998)

2.4.1 Experimental Procedures Referred the different internal blocks circuits from literatures, books and online materials, and applied the concepts to the circuits. The next phase is mathematical calculation which were done using Microsoft Excel and manually. The schematic capture is done using the Cadence Composer Tool. The next task was to simulate the design at circuit level, and to integrate all the circuits to check the functionality. Another major task was to measure the performance evaluation. The performance parameters are the essential part of any kind of design to satisfy the design specification. There is two kinds of parameter of ADC; one is static and other is dynamic. The static parameters are offset error, gain error, Integral Non linearity (INL), and Differential Non linearity (DNL). While the dynamic
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parameters are, signal to noise ratio (SNR), ENOB (Effective Number of Bits), and Total harmonic distortion.
2.4.1.1Staticparameters

Offset error is defined as the difference between the actual value and theoretical value of input voltage required to obtain the transition from first code 00000 to next code 00001. (Moscovici, A. 2001) Gain error is defined as ratio of difference between actual maximum input voltage and actual minimum input voltage to difference between theoretical maximum input voltage and theoretical minimum input voltage. (Moscovici, A. 2001) Integral Non-linearity (INL) is defined as the difference between the data converter code transition points and straight line with all other error set to zero. (Baker, J. R., Li, H. W., & Boyce, D. E. 1998) Differential Non-linearity (DNL) is defined as difference between the actual code width of a non-ideal converter and ideal case. (Baker, J. R., Li, H. W., & Boyce, D. E. 1998) 2.4.1.2 Dynamic parameters Signal to Noise Ratio (SNR) is ratio of the value of the highest RMS (Root Mean Square) input signal to the RMS value of the noise. (Baker, J. R., Li, H. W., & Boyce, D. E. 1998) Effective numbers of bits (ENOB) specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. (Maxim Integrated Product 2010) Total harmonic distortion (THD) is defined as the ratio of the RMS sum of the selected harmonics of the input signal to the fundamental itself. (Maxim Integrated Product 2010)

24

2.4.2 Resources Utilized For the design and simulation, Microsoft Excel and Cadence tools are used. For the implementation of the design, Cadence Composer tool is used. In the next step is simulated the design using the Cadence Circuit Simulator and the performance parameters are checked

2.4.3 Project Schedule This Project contains two phases; Phase I and Phase II. Both the phases involve the eight major tasks. Each task has approximately eleven to sixteen days duration. The Table 1 and Gnatt Chart present the activities of phase II as shown in following.

Task No

Task

Nos. of Days

Start Time

Finish Time

Status

1 2 3 4 5 6 7 8

Design of Capacitor array DAC Design of control Logic Design of Comparator Integration of all blocks Simulation of Data Convertor Performance Evaluation Final Report Final Report Presentation

16 11 15 4 18 11 6 6

1/22/10 2/12/10 2/26/10 3/18/10 3/23/10 4/16/10 4/09/10 4/23/10

2/12/10 2/26/10 3/18/10 3/23/10 4/16/10 4/30/10 4/16/10 4/30/10

Completed Completed Completed Completed Completed Under Progress Completed Under Progress

Table 2 Project Schedule for Project Phase II

25

Figure 16. Gnatt Chart for Project Phase II

3. Literature Survey Several IEEE documents, companys websites and on line newsletters are analyzed. The table 3 shows the summary of performance of a SAR ADC for 65nm CMOS technology. Technology Supply Voltage Sampling Rate Resolution Input Range SNDR(fin=3.3 MHz) SNDR(fin=239 MHz) SFDR(fin=239 MHz) DNL INL 65 nm CMOS 1P6M 1.2v 500 MS/s 5 bits 800m Vpp Differential 27.8 dB 26.1dB -41.5dB 0.26 LSB 0.16 LSB

Table 3. Summary of Performance (BP Ginsburg, A. C. 2007)

26

Texas Instruments have announced the 16, 14, 12 bits six channel simultaneously sampling analog to digital converter. The maximum data rate per channel is around 500kSPS [3]. The following data shows the detail features about six channel SAR ADCs. (Incorporated, T. I. 2009, August). Features of six channel SAR ADCs Family of 16, 14, 12 bits, Pin and software Compatible ADC Six SAR ADCs Grouped in three Pairs Maximum Data Rate Per Channel with Internal Conversion Clock and Reference: ADS8556: 630kSPS (PAR) or 450kSPS (SER) ADS8557: 670kSPS (PAR) or 470kSPS (SER) ADS8558: 730kSPS (PAR) or 500kSPS (SER) Maximum Data Rate with External Conversion Clock and Reference: 800kSPS (PAR) or 530kSPS Pin Selectable or Programmable Input Voltage Ranges: Up to 12V Excellent Signal to Noise Performance: 91.5dB (ADC8556) 85 dB (ADS8557) 73.9 dB (ADS8558) Programmable and Buffered Internal Reference: 0.5V to 2.5V and 0.5V to 3.0V

Operating Temperature Range:

27

-40

C to +125

LQFP -64 Package (Incorporated, T. I. 2009, August)

4. Economic Justification 4.1 Executive Summary Currently, VNB Company has one full time student engineer from San Jose State University under the guidance of Professor Morris Jones (Ex. VP of Marketing at Intel Corporation) and Srenik Mehta (Director of Analog Design at Atheros). The present job of the VNB Company is to implement the design of SAR ADC using 45nm technology. To achieve this mission VNB Company, currently uses resources from SJSU Electrical Department Lab. Additionally, for research VNB company explores the library database, books and online materials. These equipments and materials are easily accessible and economical. The Companys progress seems to be satisfactory, and profit of approximately $1.5 million is expected to be achieved within first five to six years. To accomplish a target the Company is putting hours of hard work, and it also needs initial funding of approximately $250,000. The wireless communication and battery powered equipment companies are target user of VNB products.

4.2. Market Survey There are many IC companies, which make different kinds of data convertors. The following is list of some companies, which make data converters:

Analog Devices National Semiconductors

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Texas Instruments Maxim Cirrus Logic Universal Semiconductor, Inc Accord Solutions, Inc Aimtron Technology Analog Microelectronics Arizona Microtek, Inc CE Infosys GmbH Empire Technology Group Euram Electronics Source, Inc Foresight Technologies, Inc Quickfilter Technologies Inc. Royal Philips Electronics Shanghi Belling Co. Ltd Smith Semiconductor, Inc Swindon Silicon Systems T.D Stringer THine Electronics, Inc Yeeuntech Co. Ltd (Global Spec, 1999-2000)

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Analog Devices announced a few new releases, which have SAR ADC architectures ranging from 6-bit, 8-bit, and 12-bit up to 28-bits. The newly released data converters are applicable for low power and high-speed application. (Analog Devices I., 1995-2009) The table 4 shows important features for currently released AD7985/AD7980, and similar products.

Product ID

Resolution Speed bits MSPS 2.5 1.0 1 1 1 1 1 1.33 1.33 2 3

Power Consumption(mw) 15.5 7.0 9 9 9.25 9 9.3 12 55 85 86

AD7985 AD7980 AD7450A AD7450 AD7451 AD7440 AD7441 AD7983 AD7623 AD7622 AD7621

16 16 12 12 12 10 10 16 16 16 16

Table 4. Products and its features (Analog Devices, 2009) and (Analog Devices I., 1995-2009)

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National Semiconductor has a large variety of ADCs, which have sampling rate ranging from kSPS (Kilo Samples Per Second) to GSPS (Giga Samples Per Second). Here, in table 5, few products are listed which use SAR ADC architecture. The resolution range is from 8 to 12 bits. In addition the Graph 1 shows comparison between Analog Devices and National Semiconductor. (Anonymous, 2009, June)

Product ID

Resolu Speed tion (bits) (kSPS)

Power Consumption(mw) 3V

Power Consumption(mw) 5v 0.78 0.78 0.78 0.78 0.78 0.78

Supply Voltage

ADC081C021 ADC101C021 ADC121C021 ADC081C027 ADC101C027 ADC121C027

8 10 12 8 10 12

5.5 to 189 5.5 to 189 5.56 to189 5.5 to 189 5.5 to 189 5.56 to189

0.26 0.26 0.26 0.26 0.26 0.26

2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5 2.7 to 5.5

Table 5 National Semiconductor products, resolution, speed, power and supply voltage

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3.5 3 2.5 SpeedinMSPS 2 1.5 1 0.5 0 8 8 10

SpeedVsResolution

SpeedMSPS(National Semiconductor) SpeedMSPS(AnalogDevice)

10

12

12

12

16

16

16

16

Resolutioninbits

Graph 1 Comparison between Analog Devices and National Semiconductor

National Semiconductor has similar products for ultra high speed and medium resolution; however, those products use pipeline architecture. The table 6 contains product ID and its resolution with corresponding speed.

Product ID ADC081000 ADC08D1000 ADC08D1020 ADC081500 ADC08D1500

Resolution bits 8 8 8 8 8

Speed (GSPS) 1 1 1 1.5 1.5

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ADC08D1520 ADC083000 ADC08B3000

8 8 8

1.5 3 3

Table 6 National Semiconductors ultra high speed and medium speed products (Anonymous, 2009, June) 4.3. Current SAR ADC From the market survey, the SAR ADC has resolution from 8 to 16 bits with sampling rate few kSPS to few MSPS. The current SAR ADC has resolution of 8 bits and sampling rate more than 50 MSPS. The current SAR ADC will be useful for high speed with medium resolution application. The following graph 2 shows a clear picture for the current SAR ADCs comparison with Analog Device and National Semiconductor SAR ADCs in terms of sampling rates and resolutions.

18 16 Resolution 14 12 10 8 6 1.00E+02 1.00E+04 1.00E+06 1.00E+08 AnalogDevices NationalSemi Current

SamplingRate

Graph 2 Analog Devices, National Semiconductor and current SAR ADC

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The design specification mentioned under following table no. 7 is for the current SAR ADC.

Targeted Technology Supply Voltage Sampling Rate Resolution Integral Nonlinearity Differential Nonlinearity Power Consumption Signal to Noise Ratio 45 nm 1P6M ~1v >50MSPS 8 bits +/- 0.5 LSB +/- 0.5 LSB Future work Future work

Achieved 45 nm 1v >50MSPS 8 bits Under progress Under progress Future work Future work

Table 7. Targeted and Achieved Design specification for 8 bit SAR ADC 4.4 Cost Survey The sampling rate of Analog Device products is higher compared to some of National Semiconductor ADC products, which make Analog Device Products costlier than National Semiconductor products for same resolution.

Analog Device

National Semiconductor

AD7985BCPZ

$30.99

ADC081S021CIMF $0.67

34

AD7980ARMZ AD7980BRMZ AD7626BCPZ AD7626BCPZ-RL7

$13.38 $17.85 $34.95 $34.95

ADC12C105CISQ

$24.00

ADC12C105CISQE $24.00 ADC12C105CISQ ADC12C170CISQ $24.00 $33.00

Table 8. Pricing for Analog device products and National Semiconductor (Analog Device, I., 2009), and (Anonymous. (2009, Oct)) However, for comparable resolution and speed both companies have more or less same prices.

5. Applications of Data Converters

TheapplicationsofDataConvertersarelistedbelow:

Battery powered equipment Wireless Communication Data acquisition systems Medical instruments Test and measurement Industrial imaging (Analog Device I., 2009), and (Analog Device I., 1995-2009)

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Figure 17. Data converters applications (Anonymous, 2009, June)

6. Cost Analysis 6.1 Human Resources Currently VNB Company has a single employee under the technical guidance from Prof. Morris Jones (San Jose State University) and Srenik Mehta (Director of Analog design at Atheros Comm.). VNB Company has already completed the preliminary phase of research. In the research phase, the company has done literature survey, market survey, and cost survey. The implementation part of this project has already completed successfully and the testing part is done partially. Currently, the performance testing part is in progress. The table 9 shows past and estimated growth from year 2009 to year 2013 of the VNB Company.

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Department Engineering Marketing Human Resources

2009 1 1 0

2010 1 1 0

2011 2 1 Consultant

2012 3 2 Consultant

2013 6 5 Consultant

Table 9. Past and Estimated growth of VNB Company

6.2 Product Cost From the literature survey, the SAR ADC design seems to be challenging, and from the market survey and cost analysis, it seems marketable and profitable. Currently at the starting point, the VNB Company has limited resources such as PC, communication tools, and University resources. As the company expands, it will have more resources such as office space, workstations, and marketing facilities. For design purpose, company will provide tools like Cadence, Mentor Graphics, Synopsis Powermill, and Smart Spice etc. The Company will bear the license cost of the mentioned tools. The table 10 and Graph 3 explain the past and estimated company product development cost. (Inc., M. , 2006-09), and (Inc., Y. 2009)

Category Employee Salary

2009 80

2010 90

2011 300

2012 550

2013 740

Marketing

10

10

30

40

600

37

Manufacturing Other Total

0 0 90

20 10 140

100 40 470

150 50 790

3000 100 3700

Table 10. Past and Estimated VNB company product development cost (in thousand $)

5000 4500 4000 Dollorsinthousand 3500 3000 2500 2000 1500 1000 500 0 2009

DevlopmentCost

Others Manufacturing Marketing Engineering

2010

2011 Year

2012

2013

Graph 3. Graphical presentation of development cost of VNB Company 6.3. Product Revenue From the cost survey and design cost, the price of VNB Companys product is estimated around $30.00. As the company will expand, there will be similar group of products. The breakeven point reaches in the year 2011 when the company will start making profit. (Inc., M. 2006-09), and (Inc., Y. 2009. The table 11 shows the past and estimation of product revenue.

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2009 Nos. of Units Revenue Cost Profit 0 0 90 -90

2010 2500 75 140 -65

2011 18,000 540 470 70

2012 32,000 960 790 150

2013 1,206,000 4,020 3,700 320

Table 11. Past and Estimation of Product Revenue in thousand dollars 6.4 Breakeven Analysis Breakeven analysis can be represented graphically or mathematically. Breakeven analysis relates fix cost and variable cost with number of units produced or number of operation hours. Breakeven point says when company starts making profit. Breakeven analysis is very important technique for firms economic evaluation. (Blanchard, B. S., & Fabrycky, W. J. (2006)) It is estimated that VNB Company will sell 2500 units in year 2010 and then next coming years sale will increase. The fix cost which must be paid regardless of production. The selling price is estimated $30.00. Hence, the total revenue is calculated from number of sold units and selling price. Total revenue = #of units sold * selling price = 2500 * $30 = $75000 It is assumed that variable cost is around $9 per unit.

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Hence, total variable cost

= # of unit sold * variable cost/unit = 2500 * $9 =$22,500 (for year 2010)

Breakeven =FC / SP VC Where FC is fix cost, SP is selling price and VC is variable cost. Breakeven = $63000 / ($30 - $9) = 3000 Similar way breakeven calculation can be done for following years. The graph 4 shows breakeven analysis for VNB Company. (S., Patel, K., & Byron, Spring 2009)

$4,500 $4,000 $3,500 $inthousands $3,000 $2,500 $2,000 $1,500 $1,000 $500 $0 2009

BreakevenAnalysis

Cost Revenve

breakeven

2010

2011 Year

2012

2013

Graph 4. Breakeven Analysis

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Initial Years VNB Companys profit is negative; however, after year 2011 VNB Company will first make profit. The total investment is $ 250,000. The return of investment is calculated below. Return on Investment = Net profit total investment / total investment x 100 = ($385,000 -$250,000) / $ 250,000 x100 = .54 x 100 =54% The Graph 5 explains the Norden Rayleigh Estimation for each year before VNB Company makes its first net profit. VNB Company expects approximately $250,000 funding for initial years.

NordenRayleighEstimation
180 160 140 120 100 80 60 40 20 0 20 0 Dollorsinthousands

Dollorsinthousands

3 Year

Graph 5. Norden Rayleigh Estimation for funding

41

6.5 Profit & Loss Analysis

Profit and Loss analysis is estimated for year 2009 to 2011.The table 12 to 14 shows profit and loss with income and expense in tabular form. Quarter Qtr 3 '09 Qtr 4 '09 Income Expense Profit/Loss 0 0 60 30 -60 -30

Table 12 Past and Estimated Profit and Loss for Qtr 3 09 to Qtr 4 09 ($ in thousands) The graph 6 shows VNB Company did not make any money in year 2009, however loss is reduce in following years.

80 60 40 $inthousands 20 0

P&LQtr3'09toQtr4'09

Income Expense Qtr3'09 Qtr4'09 Profit/Loss

20 40 60 80 Quarter&Year

Graph 6 Past and Estimated Profit and Loss for Qtr 3 09 to Qtr 4 09

42

Quarter Qtr 1 '10 Qtr 2 '10 Qtr 3 '10 Qtr 4 '10

Income I Ex xpense 10 1 30 3 35 3 40 4 -20 0 -20 0 50 50

Pr rofit/Loss -20 0 -20 0 -15 -10 0

Table 13 Estimated Profit P and Lo oss for Qtr 1 10 to Qtr 410 4 ($ in tho ousands)

50 40 30 $inthousands 20 10 0 Qtr1'10 10 20

P&L & Qtr1'10toQtr4'1 10

Income e Expens se Profit/Loss

Qtr2'10

Qtr3'10 0

Qtr4'10

Quarter&Year

E Profit and Loss for Qtr 1 10 to Qtr 4 10 Graph 7 Estimated As shown n in table 14 4 and graph 8, 8 VNB Com mpany expec cted first pro ofit in year 20 011. Quarter Qtr 1 '11 Incom me 60 Exp pense 75 Pro ofit/Loss -15 5 Income 60

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Qtr 2 '11 Qtr 3 '11 Qtr 4 '11

60 190 230

75 160 0 160 0

-15 5 30 70

60 190 230

Table 14 Estimated Profit P and Lo oss for Qtr 1 11 to Qtr 4 11 ($ in th housands)

250 00 20 150

P&LQtr1'11toQtr r4'11

$inthousands

Income 00 10 50 0 Qtr1'11 50 Qtr r2'11 Q 3'11 Qtr Qtr4'11 Exp pense Pro ofit/Loss

Quarter&Year Y

Graph 8 Estimated E Profit and Loss for Qtr 3 11 to Qtr 2 12

6.6 SWO OT Assessment The SWO OT analysis performed using u market t survey. In following f tab ble 15 SWO OT assessmen nt is briefly su ummarized.

44

Strengths 1. Current SAR ADC has 8 bits resolution and speed >50 MSPSs using 45nm technology. 2. Capacitor array DAC is better compare to resistor string DAC. Matching of Capacitor can be achieved better compare to resistor matching. Opportunities 1. From market and cost analysis, VNB Companys product seems marketable and cost effective. 2. In built sample and hold circuit, so there can be significant saving in chip area.

Weaknesses 1. VNB is small company, so it is difficult to grow in recession time.

Threats 1. Analog Device and National have released similar kind of ADCs. They may come up with better design.

Table 15. SWOT Assessment 7. Relevance of core courses The break-even analysis, which was covered in ENGR 202, is useful for this project. Breakeven analysis is a technique used to find out or analyze when company will make profit. The subject matter of ENGR 202 is useful to find return of investment and mainly to understand overall project life cycle. The ENGR 203s contain is helpful for project planning and scheduling using techniques like Gnatt Chart and CPM (critical path method). The topics covered in ENGR 201 are the Fourier series, time and frequency domain, and transfer function, which are useful to understand the ADC signal flow. ENGR 200W covered the formatting, how to write the report and how to present the power point.

45

8. Conclusion As discuss in the introduction, a SAR ADC is suitable for medium resolution with higher speed ranging from kSPSs to MSPSs. From the literature survey, and current market and cost survey, the future of SAR ADC using capacitor array DAC is marketable and cost-effective. As mentioned in the two analog product companies (Analog Devices and National Semiconductor) are making similar kind of ADC. Furthermore, the SAR ADC has many applications such as wireless communication, and medical Instruments.

9. Future Work Future work is to increase the resolution up to 12, 16 and 18 bits with reasonable speed. Current SAR ADC is designed using split capacitor array DAC. For future design SS capacitor array (Series Split Capacitor array) can be used. VNB Company will make products using other architectures such flash ADC or pipeline ADC.

46

Bibliography

[1] Analog Devices, I. (1995 - 2009 ). Retrieved from http://www.analog.com/en/analog-todigital-converters/ad-converters/ad7985/products/product.html. [2] 16-Bit, 2.5 MSPS, PulSAR 15.5 mW ADC in LFCSP. (2009). Retrieved from www.analog.com. [3]Device, A. (1995-2009). AD7980: 16-Bit, 1 MSPS PulSAR ADC in MSOP/QFN . Retrieved from http://www.analog.com/en/analog-to-digital-converters/adconverters/ad7980/products/product.html. [4]Kester, W. ( 2005, June). Which ADC Architecture Is Right for Your Application? Retrieved from http://www.analog.com/library/analogDialogue/archives/39-06/architecture.pdf. [5] Anonymous. (2009, June). Analog Products selection Guide. Retrieved from www.national.com. [6] Anonymous. (2009, Oct). Price & Availability. Retrieved from http://www.national.com/pf/master_DC.html. [7] S., Patel, K., & Byron. (Spring 2009). Multicore Microprocessor Interfacing (Propeller). San Jose State University. [8] Inc., M. (2006-09). How to calculate Cost of Goods. Retrieved from http://www.marketingmo.com/how-to-articles/marketing-metrics/how-to-calculate-cost-ofgoods/. [9] Inc., M. (2006-09). How to Calculate ROI Return on Investment. Retrieved from http://www.marketingmo.com/4-support-tools/how-to-calculate-roi-return-on-investment/. [10] Inc., Y. (2009). What is revenue? how do i calculate it? and how do businesses generate it? Retrieved from http://answers.yahoo.com/question/index?qid=20080513102735AAKMSuH. [11] Baker, J. R., Li, H. W., & Boyce, D. E. (1998). CMOS CIRCUIT DESIGN, LAYOUT, AND SIMULATION. New York: The Institute of Electrical and Eletronics Engineers, Inc [12] BP Ginsburg, A. C. (2007). 500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC. IEEE Journal of Solid State Circuits . [13] Incorporated, T. I. (2009, AUGUST ). 16-, 14-, 12-Bit, Six-Channel, Simultaneous Sampling. Retrieved from http://focus.ti.com/lit/ds/symlink/ads8558.pdf.
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[14 ] Moscovici, A. (2001). High Speed A/D Converters. Kluwer Academic Publishers. [15] Maxim Integrated Product. (2009). Retrieved from http://para.maximic.com/en/search.mvp?fam=fast_adc&hs=1. [16] GlobalSpec. (1999-2009 ). Specialty Data Acquisition and Convertor Chips. Retrieved from http://semiconductors.globalspec.com/SpecSearch/Suppliers/Semiconductors/Analog_Mixed_Si gnals/Data_Acquisition_Chips/Specialty_Data_Acquisition_Converter_Chips. [17] Blanchard, B. S., & Fabrycky, W. J. (2006). Systems engineering and Analysis. New Jersey: Prentice Hall.

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AppendixA
CMOSSwitchRon
ToestimatetheRonresistanceofCMOSswitchfollowingcircuitasshowninfigure3isused.TheDc operatingconditionissimulatedandresultsaretabulatedintable1.

Figure1.CMOSSwitchRonSchematic Current 1uA VinV NMOSRon PMOSRon CMOSRon

0.00E+00 3.4150E+03 1.6910E+11 3.4150E+03 1.00E01 3.6280E+03 4.9170E+09 3.6280E+03 2.00E01 3.9870E+03 1.5030E+08 3.9869E+03 3.00E01 4.7050E+03 5.3350E+06 4.7009E+03 4.00E01 6.6680E+03 2.9910E+05 6.5226E+03 5.00E01 1.5610E+04 4.1520E+04 1.1345E+04 6.00E01 1.0230E+05 1.5260E+04 1.3279E+04

49

7.00E01 1.8580E+06 9.4920E+03 9.4438E+03 8.00E01 5.1810E+07 7.3410E+03 7.3400E+03 9.00E01 1.6300E+09 6.2470E+03 6.2470E+03 1.00E+00 5.3440E+10 5.5860E+03 5.5860E+03 Table1RonResistanceofCMOSswitch

MOScharacteristics NMOSCharacteristics
Thefigure2isschematicforcircuitsimulation,andtheoutputcharacteristicsofNMOSsareplottedin figure3.Thedrainstosourcecurrentsarealmostconstantwhentransistorsareinsaturationregion(for currentslowerthan30uA).Forhighercurrents,thelengthmodulationeffectissignificant.

Figure2.Circuitforsimulatingoutputcharacteristics

50

 Figure3.OutputcharacteristicsofNMOStransistor

PMOSCharacteristics
Thefigure4isschematicforcircuitsimulation,andtheoutputcharacteristicsofPMOSsareplottedin figure5.

Figure4.SchematictomeasureoutputcharacteristicsofPMOS

51

 Figure5.OutputCharacteristicsofPMOStransistor

Transconductanceparameter
Kn(transconductanceparameterforNMOS)andKp(transconductanceparameterforPmos)are

calculatedfromperformingcircuitsimulationasshowninfollowingfigure4.Thegraphical presentationisshowningraph1andgraph2.TheKnisapproximately148uA/V2andKpis approximately78uA/V2for45CMOStechnology.

Figure6.SchematictofindKnandKpforNMOSandPMOSrespectively 52

300 250 200 K n 150 100 50 0 45 90

KnvsL
Kn(w=67.5nm) Kn(w=135nm) Kn(w=202.5nm) Kn(w=270nm) 135 Lnm 180

Graph1.KnvsL(lengthinnm)fordifferentvalueofW(widthinnm)forNMOS

120 100 80 K p 60 40 20 0 45 90

KpvsL

Kp(W=67.5nm) Kp(w=135nm) Kp(w=202.5nm) Kp(w=270nm)

135 Lnm

180

Graph2KpvsL(lengthinnm)fordifferentvalueofW(widthinnm)forPMOS 53

AppendixB

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70