IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO.

2, FEBRUARY 2003

87

Origin of the Threshold Voltage Instability in SiO2/HfO2 Dual Layer Gate Dielectrics
A. Kerber, Student Member, IEEE, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, Senior Member, IEEE, H. E. Maes, Fellow, IEEE, and U. Schwalke, Member, IEEE
AbstractThe magnitude of the VT instability in conventional MOSFETs and MOS capacitors with SiO2 /HfO2 dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitancetime traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO2 /HfO2 interface and in the bulk of the HfO2 layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the VT instability in terms of structural defects as follows. 1) A defect band in the HfO2 layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO2 /HfO2 interface by tunneling. Index TermsCharge trapping, HfO2 .

the charge loss, alternative fast sensing techniques are required. In this letter, a variant of the charge-pumping technique (amplitude sweep) is introduced, which is well suited to capture the complex transient behavior of the V instability in highgate stacks. The method provides quantitative information on the time and voltage dependence of the transient charging phenomena responsible for the V instability. Rather than measuring the V shift, the trapped charge, which causes it, is directly measured. A physical model is proposed, which explains all qualitative aspects of the electrical results. A high density of preexisting defects is observed and the existence of a defect band in the high- layer is postulated, providing deeper insight into the origin of the V instability. By speculating on the origin of the defect band, possible methods to improve the V stability are proposed. II. EXPERIMENTAL The n-channel FETs used in this study were fabricated using a conventional self-aligned transistor flow [2]. Prior to HfO deposition, a surface clean was done using SC1/SC2 or an O -based chemistry. These cleaning processes result in a 1-nm-thick chemically grown SiO layer which is used as a starting surface for the HfO deposition by atomic layer chemical vapor deposition (ALCVD). HfO films were deposited in an ASM Pulsar 2000 reactor using HfCl and H O as sources for hafnium and oxygen. Equivalent oxide thickness (EOT) values of 1.7, 1.9, and 2.3 nm were extracted [6] for the gate stacks with 3-, 4-, and 6-nm-thick HfO . Stacks with and without post deposition annealing (PDA) in N prior to the poly-Si gate deposition were compared. The dopant activation anneal was varied from 850 C for 30 s to 1000 C for 10 s. In addition, planar MOS capacitors were fabricated on n- and p-type Si substrates using field oxide isolation and similar processing conditions. Irrespective of the processing condition, comparable electrical results were obtained for FETs and MOS capacitors. Typical results are presented below. III. RESULTS AND DISCUSSION The V instability of n-channel FETs was first investigated by combining measurements after constant voltage stress (CVS) on the gate, as summarized in Fig. 1(a). In this figure, the V instability of different HfO gate stacks is compared with a SiO reference by plotting the stress-induced V shift as a function of the Si field at stress condition

I. INTRODUCTION HE aggressive scaling of CMOS devices is driving SiO -based gate dielectrics to its physical limits, as stated in the International Technology Roadmap for Semiconductors (ITRS) [1]. Currently, hafnium-based dielectrics are being heavily investigated as a replacement for SiO gate insulator [2], [3]. However, besides difficulties with the initial V control, the V stability during operation remains a key integration challenge for their use in future CMOS technologies [4], [5]. For conventional gate stacks, stress and sense experiments are commonly used to evaluate the V stability. As will be shown in this letter, the V instability in many high- gate stacks cannot be assessed reliably by this method because of strong charge de-trapping after a stress. Therefore, in most publications, the V instability in high- gate stacks is qualitatively discussed in terms of capacitancevoltage ( ) hysteresis and stretchout. No attempts have been made to quantify it accurately and to address its root cause. Because of
Manuscript received November 11, 2002. This work was supported in part by ASM America, Inc., and in part by International Sematech. The review of this letter was arranged by Editor C.-P. Chang. A. Kerber is with Infineon Technologies, D-81541 Munich, Germany, with the Institut fr Halbleitertechnik, Technische Universitt Darmstadt, D-64289 Darmstadt, Germany, and also with International Sematech, IMEC, B-3001 Leuven, Belgium (e-mail: Andreas.Kerber@imec.be). E. Cartier is with the IBM Research Division, Yorktown Heights, NY 10598 USA and also with International Sematech, IMEC, B-3001 Leuven, Belgium. L. Pantisano, R. Degraeve, T. Kauerauf, G. Groeseneken, and H. E. Maes are with IMEC, B-3001 Leuven, Belgium. Y. Kim and A. Hou are with International Sematech, Austin, TX 78741 USA. U. Schwalke is with the Institut fr Halbleitertechnik, Technische Universitt Darmstadt, D-64289 Darmstadt, Germany. Digital Object Identifier 10.1109/LED.2003.808844

0741-3106/03$17.00 2003 IEEE

88

IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 2, FEBRUARY 2003

Fig. 2. Normalized C t traces of SiO =HfO gate stacks on n- and p-type Si substrate. A C t trace for SiO is given as a reference.

Fig. 1. (a) Stress-induced V shifts versus maximum Si field for various SiO =HfO gate stacks for stress time of 1 s. A 4.5-nm SiO reference is shown for comparison. (b) Multiple I V traces for a selected gate stack from (a) using measurement sequence as indicated in the figure.

and for a stress time of 1 s. As expected, for SiO no measurable V shifts were observed for Si fields smaller than 4 MV/cm. For HfO -containing gate stacks, positive shifts in the order of 3050 mV were routinely measured already at operation conditions and for short stress times, indicating strong negative charge buildup. The data in Fig. 1(a) also shows that the V instability is not substantially reduced by post-deposition annealing (PDA) in N or by varying the dopant activation temperature (not shown here). An important feature of the instability is illustrated in Fig. 1(b). Full recovery of the V instability is observed when the devices are biased into accumulation after stressing in inversion. This is illustrated by the three sequential traces shown in Fig. 1(b). All these results clearly demonstrate that the details of the measurement procedure strongly affect the magnitude of the V instability. The complexity of the charging instability can also be observed in the shape of traces. For capacitors on n-type Si substrates, a significant stretchout is observed in accumulation (not shown). Stretchout can only be observed if increasingly more defects are charged or discharged during the ramp measurements. When comparing the measured with a simulated curve using the NCSU CVC model [6], a trapped electrons/cm is required to charge density in the order of explain the observed stretchout at a gate bias of 1.5 V, for example. This is in qualitative agreement with the FET data shown in Fig. 1. Direct evidence for a stretchout can be obtained by capacitancetime ( ) traces as shown in Fig. 2. When ap-

plying, for example, a 1.5 V pulse to the gate of a capacitor on n-type Si, a 2% decrease in the accumulation capacitance is measured within the first few seconds. This effect is absent for the SiO reference. A capacitance decrease of this magnitude is again in qualitative agreement with a shift induced by trapped electrons/cm . (A capacitance drop is also observed for capacitors on p-type Si when applying a negative gate pulse. This effect can be attributed to the de-trapping of negative charge, as shown by the charge-pumping measurements below.) The fact that such transients can be measured on a time scale of seconds strongly suggests that the charge is trapped inside the high- layer, away from the Si substrate. In summary, the data presented in Figs. 1 and 2 and the discussion above show that the V instability is caused by a fast voltage-dependent charge exchange between the Si substrate and the gate stack. To quantify the time dependence of the charging phenomena at short times directly, a variant (amplitude sweep) of the charge-pumping (CP) technique [7] is introduced here. During an amplitude sweep, a trapezoidal pulse train of frequency is applied to the gate of a FET, ) is whereby the lower voltage level (extraction voltage, V ) is kept constant and the upper level (injection voltage, V varied. Based on the previous discussion, in such an experiment, electrons are periodically injected (from the inversion layer) , and then extracted (to the Si subinto the gate stack at V . From the time-averaged substrate current, the strate) at V number of trapped charges per cycle can be directly calculated [7]. Thus, with the amplitude sweep, the charge, which causes the V instability, is measured directly. Typical results with V, are shown in Fig. 3. The solid symbols mark V the number of pumped carriers per cycles for three different (50% duty cycle). charging/extraction times, Charge exchange with the gate dielectric is observed to start exceeds V and it increases with both V and . when V To study the de-trapping of electrons as a function of extraction voltage and , a reverse amplitude sweep can be used, where is kept constant at a high level, and V is decreased V (open symbols in Fig. 3). With decreasing (more negative) extraction bias, de-trapping is observed to strongly increase,

KERBER et al.: ORIGIN OF THE THRESHOLD VOLTAGE INSTABILITY IN SiO /HfO DUAL LAYER GATE DIELECTRICS

89

features of the presented experimental data can be explained qualitatively. A defect band located above the Si conduction band allows for efficient charging and discharging of the defects by applying positive or negative gate bias, respectively. This is illustrated in Fig. 4(a) and (c). The motion of the defect band in energy with gate bias is amplified due to the large difference of the dielectric constant in SiO and HfO . The rapid charging and discharging of the defect band makes the proposed amplitude sweep particularly useful to study the impact of the charge trapping in the high- layer on the device parameters. IV. CONCLUSION We have demonstrated that the complex charging instability of SiO HfO gate stacks fabricated with a conventional CMOS process can be captured by charge-pumping measurements because of its high time resolution and because the measurement sequence can be adapted (using an amplitude sweep) to invoke the trapping phenomena, which causes the V instability in n-channel FETs. A defect model is proposed which attributes the cause of the V instability to charge trapping in a defect band in the HfO layer. The physical origin of the defect band may be related to oxygen vacancies [9], chlorine impurities or water-related defects, such as OH (OH ) groups, introduced by to the precursor chemistry. In order to successfully integrate SiO HfO gate stacks into a future CMOS technology, the defects in the HfO layer need to be cured. Varying the deposition process, the deposition temperature and possibly the post-deposition treatment may result in better V stability. ACKNOWLEDGMENT The authors would like to acknowledge the support of the IMEC high- team. REFERENCES
[1] International Technology Roadmap for Semiconductors. (2001). Semiconductor Industry Assoc., San Jose, CA. [Online]. Available: http://public.itrs.net [2] Y. Kim et al., Conventional n-channel MOSFET devices using single layer HfO and ZrO as high-k gate dielectrics with polysilicon gate electrode, in IEDM Tech. Dig., 2001, pp. 455458. [3] C. Hobbs et al., 80-nm poly-Si gate CMOS with HfO gate dielectric, in IEDM Tech. Dig., 2001, pp. 651654. [4] E. P. Gusev et al., Ultrathin high-K gate stacks for advanced CMOS devices, in IEDM Tech. Dig., 2001, pp. 451454. [5] E. Cartier, Emerging challenges in the development of high-" gate dielectrics for CMOS applications, in AVS 3rd Int. Conf. Microelectronics and Interfaces, 2002, pp. 119122. [6] J. R. Hauser and K. Ahmed, Characterization of ultra-thin oxides using electrical C V and I V measurements, in AIP Conf. Proc. 449, 1998, pp. 235239. [7] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, A reliable approach to charge-pumping measurements in MOS transistors, IEEE Trans. Electron Devices, vol. ED-31, pp. 4253, Jan. 1984. [8] G. Van den Bosch, G. Groeseneken, and H. E. Maes, On the geometric component of charge-pumping current in MOSFETs, IEEE Electron Device Lett., vol. 14, pp. 107109, Mar. 1993. [9] R. M. Fleming et al., Defect dominated charge transport in amorphous Ta O thin films, J. Appl. Phys., vol. 88, no. 2, pp. 850862, 2000.

Fig. 3. Charge-pumping characteristics measured on n-channel MOSFET with a 3-nm HfO layer deposited on O cleaned Si surface and PDA in N at 600 C for 1 min. The conventional base level sweep (inset) is compared with the amplitude sweep using constant base level.

Fig. 4. Schematic energy-band diagram of a SiO =HfO /poly-Si gate stack containing a defect band in the HfO layer at flatband condition, shown in (b). For (a) negative and (c) positive gate bias, the defects located near the SiO interfacial layer move rapidly with respect to the Fermi-level in the Si substrate.

eventually resulting in complete charge recovery. From Fig. 3, it can be seen directly, that gate leakage does not contribute to the charge-pumping signal. No charge is measured for the quasi-dc V . The geometrical component [8] conditions of V was found to be insignificant for the devices and measurement conditions used (fall and rise times of 100 ns). cm Using conventional charge pumping, only interface states are measured (see inset of Fig. 3). Therefore, the charge measured with the amplitude sweep cannot be located at the SiSiO interface. The strong dependence on charging/discharging time also supports the notion that the defects are located deeper inside the gate stack. During all these measurements, no evidence for defect generation was observed. The measured effects are entirely due to the charging and discharging of preexisting defects. It can be speculated that the defects are located in the HfO layer, distributed in energy and space, and can be accessed from the Si substrate by tunneling through the interfacial SiO layer. If a defect band in the HfO layer, as sketched in Fig. 4(b), is present and located above the Si conduction band, all the basic