Académique Documents
Professionnel Documents
Culture Documents
Level:
Fundamental to Intermediate
Prerequisites:
Basic digital design knowledge
Skills Gained:
Advanced Digital Design, Timing Analysis, State Machines, Memory Devices, RISC & CISC architecture
CPLD and FPGA Architecture, ASIC Design Flow
Basics of Synthesis, HDL for Synthesis and Advanced Synthesis Concepts
Verilog Language for Hardware Design and Logic Synthesis, Design Flow with Verilog
The File-IO and PLI concepts
Functional Verification Flow & Terminologies, Verilog Testbench for Simulation
An Introduction to System C/C/C++ based Hardware Modeling
A mini Project for Testbench Modeling with C & Verilog
Design & Verification Methodology with System Verilog
Understanding the complete Project Execution Cycles