Ans 1(a) BJT is called bipolar device because current in this is carried b both electrons and holes and

in case of FET current is only carried by either holes or electrons S No 1 FET It is a voltage controlled device i.e. voltage at gate or drain terminal controls the amount of current flowing through the device Its input resistance is very high and is the order of several mega ohms It has negative temperature coefficient It does not suffer from minority carrier storage effects and therefore has higher switching speeds It is smaller in Size BJT It is a current controlled device i.e. base current controls the amount of collector current

Its input resistance is very low as compared o FET and is of the order of Kilo ohms It has positive temperature coefficient It suffers from minority carrier storage effects and therefore has lower switching speed and cut off frequencies than that ff FET It is bigger in Size

3 4

There could be more differences. There should be at least 4 Differences to get 5 marks

Ans1 (b) Operation JFET-working Operation of JFET

Operation of JFET Let us consider an N-channel JFET for discussing its operation. (i) When neither any bias is applied to the gate (i.e. when V GS = 0) nor any voltage to the drain w.r.t. source (i.e. when VDS = 0), the depletion regions around the P-N junctions , are of equal thickness and symmetrical. (ii) When positive voltage is applied to the drain terminal D w.r.t. source terminal S without connecting gate terminal G to supply, as illustrated in fig. 9.4, the electrons (which are the majority carriers) flow from terminal S to terminal D whereas conventional drain current I D flows through the channel from D to S. Due to flow of this current, there is uniform voltage drop across the channel resistance as we move from terminal D to terminal S. This voltage drop reverse biases the diode. The gate is more negative with respect to those points in the channel which are nearer to D than to S. Hence, depletion layers penetrate more deeply into the channel at points lying closer to D than to S. Thus wedge-shaped depletion regions are formed, as shown in figure. when Vds is applied. The size of the depletion layer formed determines -the width of the channel and hence the magnitude of current ID flowing through the channel. layers gets reduced causing decrease in resistance and , therefore, increase in drain current I D. (The gate-source voltage VGS at which drain current ID is cut-off completely (pinched off) is

called the pinch-off voltage Vp. It is also to be noted that the amount of reverse bias is not the same throughout the length of the P-N junction. When the drain current flows through the channel, there is a voltage drop along its length. The result is that the reverse bias at the drain end is more than that at the source end making the width of depletion layer more at the drain. To see how the width of the channel varies with the variation in gate As the width of the depletion layer is penetrated both sides of it will touch each other then the flow o current will stop then that voltage is called Cut off Voltage. CHARACTERISTICS OF JFETS There are two types of static characteristics viz (1) Output or drain characteristic and (2) Transfer characteristic.

JFET Parameters :-

Drain Resistance (rd):- From Drain Characteristics, the important parameter of JFET, is drain resistance rd, & can be calculated from figure Drain resistance rd is the are resistance b/w drain & source terminal when JFET is operating in saturation region it is the reciprocal of the & lape of the drain characteristics in saturation region

rd Since characteristics in the saturation region is almost flart, rd in not easily. rd range from about 50kr .. Several hundred kr. rd is usually the O/P resistance of JFET, it may also be expressed as O/P admittance

Transconductance: - Transconductance gm , is the change in drain gate do source v/g with the drain to source v/g constant .

for given change in

VDS = Const

unit m A/V Or ms s Siemens

-vas

ID

Amplification Factor (

Amplification factor

Open loop Op-Amp Configuration:No connection b/w o/p & o/p & op-amp works as a very high gain amplifier. Following are the three open loop op-amp configuration:(a) (b) (c) Non inverting amplifier Inverting amplifier Differential amplifier +v

(a)Non Inverting Amplifier:In Non inverting amplifier, I/P is applied at the non-inverting terminal of the op-amp &inverting terminal is grouched o/p of non-inverting amplifier is in phase with the I/P We know that for an Op-amp ground A

Open loop gain

but from the fig &

O/p is A times larger than I/P & is in phase with the e/p. (b) Inverting Amplifiers:- I/P is applied at the inverting terminal & the non-inverting terminal is grounded. O/P of inverting amp is out of phase with I/p

We know that

.. source resistance Rin is neglected than

(c)

O/P is A times greater or larger than the I/P & is in opposite phase . Differential Amplifier:I/P are applied at .eaverting & non Inverting amplifier. Since difference b/w the two input signal is amplifier, the Configuration is ealled the differential amplifier. A

..

Two sources resistance are neglected than

From above equation it is obvious that the o/p is A times of dieefence b/w two I/p v/g .The polarity of I/p diff.v/g.

OP Amp as an Adder or Summer :Adder is a .whose o/p is equal .. the sem of applied I/p v/ges. Let three V/gs are applied to the inverting I/p of op Amp.

Assuming that op-amp is ideal, we have

Since gain of op-Amp is Therefore Vid Vid =0

Now current ia is given as

Similarly ib Applying Kcl at Mode A we have

but

is zero because i/p impedance cg ideal op-amp is infinite so

Ans 1(d) Marks

An Operational amplifier is a directly coupled very high gain amplifier generally consisting of one or more differential amplifiers. An Operational amplifier can amplify signals having frequency ranging from 0 Hz to 1MHz i.e. it can be used to amplify both ac and dc .It is basically a multi stage amplifier which consists of large no of transistors. Properties of Ideal Op amp PARAMETER IDEALIZED CHARACTERISTIC

Voltage Gain, (A)

Infinite - The main function of an operational amplifier is to amplify the input signal and the more open loop gain it has the better, so for an ideal amplifier the gain will be infinite. Infinite - Input impedance is assumed to be infinite to

Input impedance, (Zin)

prevent any current flowing from the source supply into the amplifiers input circuitry. Output impedance, (Zout) Zero - The output impedance of the ideal operational amplifier is assumed to be zero so that it can supply as much current as necessary to the load. Infinite - An ideal operational amplifier has an infinite Frequency Response and can amplify any frequency signal so it is assumed to have an infinite bandwidth. Zero - The amplifiers output will be zero when the voltage difference between the inverting and non-inverting inputs is zero. Infinite An ideal operational amplifier has an infinite Common Mode Rejection ratio Infinite An ideal operational amplifier has an infinite Slew rate

Bandwidth, (BW)

Offset Voltage, (Vio)

CMRR Slew Rate

Ans1 (e) i) CMRR : common-mode Rejection Ratio As stated before, an ideal differential amplifier only amplifies the voltage difference between its two inputs. If the two inputs of a differential amplifier were to be shorted together (thus ensuring zero potential difference between them), there should be no change in output voltage for any amount of voltage applied between those two shorted inputs and ground: Voltage that is common between either of the inputs and ground, as "Vcommon-mode" is in this case, is called common-mode voltage. As we vary this common voltage, the perfect differential amplifier's output voltage should hold absolutely steady (no change in output for any arbitrary change in common-mode input). This translates to a common-mode voltagegain of zero.

The operational amplifier, being a differential amplifier with high differential gain, would ideally have zero common-mode gain as well. In real life, however, this is not easily attained. Thus, common-mode voltages will invariably have some effect on the op-amp's output The performance of a real op-amp in this regard is most commonly measured in terms of its differential voltage gain (how much it amplifies the difference between two input voltages) versus its common-mode voltage gain (how much it amplifies a common-mode voltage). The ratio of the former to the latter is called the common-mode rejection ratio, abbreviated as

An ideal op-amp, with zero common-mode gain would have an infinite CMRR. Real opamps have high CMRRs, the ubiquitous 741 having something around 70 dB, which works out to a little over 3,000 in terms of a ratio. (ii) Slew Rate Slew rate is defined as the maximum rate of change of output voltage per unit of time under large signal conditions and is expressed in volts / secs.

(iii) Input offset voltage Input offset voltage is defined as the voltage that must be applied between the two input terminals of an OPAMP to null or zero the output . (iv) Input offset Current: The input offset current Iio is the difference between the currents into inverting and noninverting terminals of a balanced amplifier. Iio = | IB1 - IB2 | The Iio for the 741C is 200nA maximum. As the matching between two input terminals is improved, the difference between IB1 and IB2 becomes smaller, i.e. the Iio value decreases further. For a precision OPAMP 741C, Iio is 6 nA (v) Input Bias Current: The input bias current IB is the average of the current entering the input terminals of a balanced amplifier i.e.

SECTION B Ans 2

As its name suggests, the depletion-enhancement MOSFET (DE-MOSFET)-was developed to be used in either or both the depletion and enhancement modes. Construction of a DEMOSFET.

Construction of DEMOSFET Figure shows the construction of an N-channel depletion MOSFET. It consists of a highly doped P-type substrate into which two blocks of heavily doped N-type material are diffused forming the source and drain. An N-channel is formed by diffusion between the source and drain. The type of impurity for the channel is the same as for the source and drain. Now a thin layer of SiO 2 dielectric is grown over the entire surface and holes are cut through the SiO2 (silicon-dioxide) layer to make contact with the N-type blocks (Source and Drain). Metal is deposited through the holes to provide drain and source terminals, and on the surface area between drain and source, a metal plate is deposited. This layer constitutes the gate. Si0 2 layer results in an extremely high input impedance of the order of 1010 to 1015 Q for this area. The chip area of a MOSFET is typically 0.003 um2 or less which is about only 5% of the area required by a BJT. A P-channel DE-MOSFET is constructed like an N-channel DE-MOSFET, starting with an N-type substrate and diffusing P-type drain and source blocks and connecting them internally by a P-doped channel region. Operation of DEMOSFET.

DEMOSFET-Operation DE-MOSFET can be operated with either a positive or a negative gate. When gate is positive with respect to the source it operates in the enhancementor E-mode and when the gate is negative with respect to the source, as illustrated in figure, it operates in depletion-mode. When the drain is made positive with respect to source, a drain current will flow, even with zero gate potential and the MOSFET is said to be operating in E-mode. In this mode of operation gate attracts the negative charge carriers from the P-substrate to the N-channel and thus reduces the channel resistance and increases the drain-current. The more positive the gate is made, the more drain current flows. On the other hand when the gate is made negative with respect to the substrate, the gate repels some of the negative charge carriers out of the N-channel. This creates a depletion region in the channel, as illustrated in figure, and, therefore, increases the channel resistance and reduces the drain current. The more negative the gate, the less the drain current. In this mode of operation the device is referred to as a depletion-mode MOSFET. Here too much negative gate voltage can pinch-off the channel. Thus operation is similar to that of JFET. Characteristics of DEMOSFET. (i) Drain characteristics

Typical drain characteristics, for various levels of gate-source voltage, of an N-channel MOSFET are shown in figure. The upper curves are for positive V GS and the lower curves are for negative VGS. The bottom drain curve is for VGS = V GS(OFF). For a specified drain-source voltage VDS, VGS (OFF) is the gate-source voltage at which drain current reduces to a certain specified negligibly small value, as shown in figure. This voltage corresponds to the pinch-off voltage Vp of JFET. For VGS between VGS (0FF) and zero, the device operates in depletion-mode while for VGS exceeding zero the device operates in enhancement mode. These drain curves again display an ohmic region, a constant-current source region and a cut-off region. MOSFET has two major applications: a constant current source and a voltage variable resistor. (i) DEMOSFET-transfer characteristics

The transfer (or transconductance) characteristic for an N-channel DE-MOSFET is shown in figure. IDSS is the drain current with a shorted gate. Since the curve extends to the right of the origin, IDSS is no longer the maximum possible drain current.

Mathematically, the curve is still part of a parabola and the same square-law relation exists as with a JFET. In fact, the depletion-mode MOSFET has a drain current given by the same transconductance equation as before, equation . Furthermore, it has the same equivalent circuits as a JFET. Because of this, the analysis of a depletion-mode MOSFET circuit is almost identical to that of a JFET circuit. The only difference is the analysis for a positive gate, but even here the same basic formulas are used to determine the drain current ID, gate-source voltage VGS etc. The foregoing discussion is applicable in principle also to the P-channel DE-MOSFET. For such a device the sign of all currents and voltages in the characteristics must be reversed. Schematic Symbols of DEMOSFET.

DEMOSFET-Schematic symbols Figure shows the schematic symbol for a DE-MOSFET. Just to the right of the gate is the thin vertical line representing the channel. The drain lead comes out from the top of the channel and the source lead connects to the bottom. The arrow is on the P-substrate and points to the Nmaterial. In some applications, a voltage can be applied to the substrate for added control of drain current. For this reason, some DE-MOSFETs have four terminal leads. But in most applications, the substrate is connected to the source. Usually the substrate is connected to the source internally by the manufacturer. This results in a three terminal device whose schematic symbol is shown in figure. Schematic symbol for a three terminal P-channel DE-MOSFET device is shown in figure. The schematic symbol of a P-channel DE-MOSFET is similar to that of an N-channel DE-MOSFET, except that the arrow points outward.

Ans 3 Voltage Follower (Unity Gain Buffer) If we made the feedback resistor, Rf = 0 then the circuit will have a fixed gain of "1" and would be classed as a Voltage Follower and this type of Non-inverting amplifier circuit is sometimes called a Voltage follower with gain. As the input signal is connected directly to the non-inverting input of the amplifier the output signal is not inverted resulting in the output voltage being equal to the input voltage, Vout = Vin. This then makes the Voltage Follower circuit ideal as a Unity Gain Buffer circuit because of its isolation properties as impedance or circuit isolation is more important than amplification. The input impedance of the voltage follower circuit is very high, typically above 1M as it is equal to that of the operational amplifiers input, since an ideal op-amp condition is assumed.

In this circuit, Rin has increased to infinity and Rf reduced to zero, the feedback is 100% and Vout is exactly equal to Vin giving it a fixed gain of 1 or unity. As the input voltage Vin is applied to the non-inverting input the gain of the amplifier is given as:

Since no current flows into the non-inverting input terminal the input impedance is infinite and also no current flows through the feedback loop so any value of resistance may be placed in the feedback loop without affecting the characteristics of the circuit as no voltage is dissipated across it, zero

current, zero voltage, zero power drop. However in most real unity gain buffer circuits a low value (typically 1k) resistor is required to reduce any offset input leakage currents, and also if the operational amplifier is of a current feedback type. Summing Amplifier The Summing Amplifier is a very flexible circuit based upon the standard Inverting Operational Amplifier configuration. We saw previously in the Inverting Amplifier tutorial that the Inverting Amplifier has a single input signal applied to the Inverting input terminal. If we add another input resistor equal in value to the original input resistor, Rin we end up with another operational amplifier circuit called a Summing Amplifier, "Summing Inverter" or even a "Voltage Adder" circuit as shown below. Summing Amplifier Circuit

The output voltage, (Vout) now becomes proportional to the sum of the input voltages, V1, V2, V3 etc. Then we can modify the original equation for the inverting amplifier to take account of these new inputs thus:

However, if all the input impedances, (Rin) are equal in value the final equation for the output voltage is given as:

We now have an operational amplifier circuit that will amplify each individual input voltage and produce an output voltage signal that is proportional to the algebraic "SUM" of the three individual input voltages V1, V2 and V3. We can also add more inputs if required as each individual input "see's" their respective resistance, Rin as the only input impedance. This is because the input signals are effectively isolated from each other by the "virtual earth" node at the inverting input of the op-amp. A direct voltage addition can also be obtained when all the resistances are of equal value and Rf is equal to Rin. A Scaling Summing Amplifier can be made if the individual input resistors are "NOT" equal. Then the equation would have to be modified to:

We can also rearrange the formula to make the feedback resistor RF the subject and the output voltage is found from

Allowing the output voltage to be easily calculated if more input resistors are connected to the amplifiers input. The input impedance of each individual channel is the value of their respective input resistors, ie, R1, R2, R3 ... etc. The Summing Amplifier is a very flexible circuit indeed, enabling us to effectively "Add" or "Sum" together several individual input signals. If the inputs resistors, R1, R2, R3 etc, are all equal a unity gain inverting adder can be made. However, if the input resistors are of different values a "scaling summing amplifier" is produced which gives a weighted sum of the input signals.

Ans 4

The negative sign in the equation indicates an inversion of the output signal with respect to the input as it is 180o out of phase. This is due to the feedback being negative in value. Non-inverting Amplifier The second basic configuration of an operational amplifier circuit is that of a Non-inverting Amplifier. In this configuration, the input voltage signal, (Vin) is applied directly to the Non-inverting (+) input terminal which means that the output gain of the amplifier becomes "Positive" in value in contrast to the "Inverting Amplifier" circuit we saw in the last tutorial and whose output gain is negative in value. Feedback control of the non-inverting amplifier is achieved by applying a small part of the output voltage signal back to the inverting (-) input terminal via a Rf - R2 voltage divider network, again producing negative feedback. This produces a Non-inverting Amplifier circuit with very good stability, a very high input impedance, Rin approaching infinity (as no current flows into the positive input terminal) and a low output impedance, Rout as shown below.

Non-inverting Amplifier

In the previous Inverting Amplifier tutorial, we said that "no current flows into the input" of the amplifier and that "V1 equals V2". This was because the junction of the input and feedback signal (V1) are at the same potential in other words the junction is a "Virtual Earth" summing point. Because of this virtual earth node the resistors, Rf and R2 form a simple voltage divider network across the amplifier and the voltage gain of the circuit is determined by the ratios of R2 and Rf as shown below. Equivalent Voltage Divider Network

Then using the formula to calculate the output voltage of a potential divider network, we can calculate the output Voltage Gain of the Non-inverting Amplifier as:

Then the closed loop voltage gain of a Non-inverting Amplifier is given as:

We can see that the overall gain of a Non-Inverting Amplifier is greater but never less than 1 (unity), is positive and is determined by the ratio of the values of Rf and R2. If the feedback resistor Rf is zero the gain will be equal to 1 (unity), and if resistor R2 is zero the gain will approach infinity, but in practice it will be limited to the operational amplifiers open-loop differential gain, (Ao). Differentiator and Integrator Operational Amplifier Circuits