DESIGN OF PHASE LOCKED LOOP

Program:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pll is Port ( datain : in std_logic; clock : in std_logic; clrdcd : in std_logic; dcd : out std_logic; rx_clock : out std_logic; -- raw data input -- 64 bit clock -- clear dcd when 8 ones are detected -- data carrier detect output -- recovered rx clock

dataout : out std_logic);-- received data output end pll;

architecture Behavioral of pll is signal counter : std_logic_vector(4 downto 0):= "00000"; -- counter 0...31 signal dcd_cntr : std_logic_vector(7 downto 0):= "00000000"; -- counter 0...255 signal edge : std_logic; --- edge detector output : data decision changed signal dly_data : std_logic; -- delayed data for edge detector

signal q1 : std_logic; -- late clock signal qe : std_logic; -- early clock signal enable : std_logic; -- gets toggled every clock or when clock has to be adjusted signal increment : std_logic := '0'; signal decrement : std_logic := '0'; signal clear_dcd : std_logic := '0'; signal reset_dcd : std_logic := '0'; begin --- recovered rx clock for following stages rx_clock <= counter(4); process(clock, clrdcd, reset_dcd) begin if(clock'event and clock = '1') then clear_dcd <= reset_dcd or clrdcd; end if; end process; --- clock in new data process(clock, datain) begin if(clock'event and clock = '1') then dataout <= datain; end if;

end process; -- rx clock counter process(clock, enable, clrdcd) begin if(clock'event and clock = '1') then if(enable = '1') then counter <= counter + '1'; -- increase counter else counter <= counter; end if; end if; end process; -- set early and late clocks process(counter) begin if(counter = "10000" or counter = "01111") then q1 <= '0'; qe <= '0'; elsif (counter(4) = '1') then --- late clock when counter > 32 q1 <= '1'; qe <= '0'; else

q1 <= '0'; qe <= '1'; end if; end process; -- adjust rx clock process(clock, enable, clrdcd) begin

--- early clock when counter < 31

if(clock'event and clock = '1') then --- increment clock when edge detect during early clock if(qe = '1' and edge = '1') then increment <= '1'; end if; --- decrement clock when edge detect during late clock if(qe = '1' and edge = '1') then decrement <= '1'; end if; --- clear after one step increment if (enable = '1') then if (increment = '1') then increment <= '0'; enable <= '1'; else

enable <= '0'; end if; else --- clear after one step decrement if (decrement = '1') then decrement <= '0'; enable <= '0'; else enable <= '1'; end if; end if; end if; end process; -- dcd detection process(clock, edge, counter, clear_dcd) begin if(clear_dcd = '1') then dcd_cntr <= (others => '0'); dcd <= '0'; reset_dcd <= '0'; elsif(counter(4)'event and counter(4) = '0') then if(edge = '0') then -- sample at rising edge, if no data change increase counter

if(dcd_cntr = 255) then dcd <= '1'; -- assert dcd if dcd counter is at max dcd_cntr <= dcd_cntr; else dcd <= '0'; dcd_cntr <= dcd_cntr + '1'; end if; else reset_dcd <= '1'; end if; end if; end process; --- edge detector, input data has changed process(clock, datain) begin if(clock'event and clock ='1') then edge <= dly_data xor datain; dly_data <= datain; end if; end process; end Behavioral;