50

IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOI.. 24, NO.

1. FEBRUARY 1989

A Built-In Hamming Code ECC Circuit for DRAMS

Absfrucf-This paper describes a built-in Hamming code error checking and correcting (ECC) technique for dynamic RAMs. This ECC technique checks multiple cell data simultaneously and allows fast column access. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a lCMbit DRAM with 20-percent chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical (HV) parity code ECC technique.

n l

I. INTRODUCTION

IGHLY integrated dynamic RAMs require compact memory cell arrays to maintain compatibility with previous generations and to keep healthy production yield. That causes insufficient storage capacitance for immunity from alpha-particle-induced soft errors. To solve this problem, several built-in error checking and correcting (ECC) circuits have been proposed. A 256-kbit DRAM with a built-in Hamming code ECC circuit is commercially available [l],and recently an experimental 16-Mbit DRAM with a built-in horizontal-vertical (HV) parity code ECC circuit has been reported [2]. The built-in HV parity code ECC circuit can reduce the alpha-particle-induced soft error rate and enhance the c h p yield with a small increase in access time and chip area [3]. Built-in ECC circuits have employed either the HV parity code or the Hamming code. Both codes can correct only a single error data in one ECC data group. Thus an ECC circuit must correct the error before two data bits in an ECC data group become erroneous by the soft error. The HV parity code ECC circuit checks a single data bit [3] or several data bits [4] in a single ECC operation cycle. On the other hand, the Hamming code ECC circuit checks all data bits of an ECC data group simultaneously. Therefore the Hamming code ECC circuit has a higher error-correcting frequency than that of the HV parity code ECC circuit. Thus the Hamming code ECC provides higher reliability. There are two schemes in realizing built-in ECC circuits. One is to form an ECC data group with data extracted
Manuscript received April 12, 1988; revised September 12, 1988. The authors are with the LSI Research and Development Laboratory. Mitsubish Electric Corporation, Itami. Hyogo 664, Japan. IEEE Log Number 8825488.

(a) (b) Fig. 1. (a). (b) Built-in ECC circuit schemes

from subarrays (Fig. l(a)). In this scheme, data bus area which conveys the memory cell data to the ECC circuits increases significantly as the data bit length increases. Thus the 256-kbit DRAM with a Hamming code ECC circuit uses a short ECC code with eight data bits and four check bits [l], causing rather large additional chip area due to check bit cells. The other scheme involves forming an HV parity ECC data group with data associated with an identical word line in a subarray (Fig. l(b)). In this scheme, the parity checker, which is located next to the memory cell array, checks the parities of the horizontal group and vertical group to which the selected data belongs. This parity checker is able to reduce the chip area increase and access-time increase because long data bus lines are not necessary. However, the ECC operation of the latter scheme follows the selection of the memory cell data by the column decoder. Thus the ECC operation time, whch exceeds the time that is required for the readout data amplification, adds to the column access time. As the speed of the computer system improves, a fast column access mode such as page mode is introduced. In page mode, all data bit cells on the same word line can be accessed rapidly by column address, because row address decoding and sensing operation are not necessary. Thus the access-time penalty of 5 ns [3] is not ignorable compared with the column address access time of 25 ns of a DRAM without ECC [ 5 ] .

0018-9200/89/0200-0050$01.00 01989 IEEE

FIJRUTANI et

ul.:

BUILT-IN HAMMING CODE ECC CIRCUIT FOR DRAMS

51

~ 1l 0 l1 o1 l0 l1 o 1 0 l o )

XV

c1

H= 01 1 1 0 0 0 1 [ooooi 1 1 i

x=
J

x2

c = c3

c2

S=H*X@C

Fig. 2 . A new Hamming code ECC scheme.

the ECC data group. The column decoder selects one data out of the ECC data group. In READ operation, the readout data are checked by comparing the syndrome with the output of the error syndrome generator. The output of the error syndrome generator is the same as the syndrome which points out the readout data. Thus, if the syndrome is the same as the output of the error syndrome generator, the readout data are found to be erroneous. In WRITE operation, the selected memory cell data and the check bit data associated with the selected cell data are renewed. The error syndrome generator also designates the check bits to be renewed. The ECC circuit patrols all of the memory cells in refresh cycles, by selecting all word lines successively. When an error is detected, the address converter transforms the syndrome into the address signal of the column decoder. The erroneous memory cell data are selected by the column decoder and inverted by the correcting circuit. 111. CIRCUIT DESIGN In designing the practical built-in ECC, the selector-line merged syndrome generator [3] is one of the most important techniques. Besides this technique there are several factors, inherent in the Hamming code ECC technique, to be considered.

A . Parity Check Matrix

The Hamming code ECC technique checks the data which compose a Hamming code simultaneously. Thus all of the data are required to generate the syndrome. The parity check matrix H of the Hamming code (Fig. 2) has row vectors whose nonzero elements cluster. Thus this parity check matrix has the difficulty that the transmission-type XOR circuits must be laid out with the pitch of a sense amplifier. This is very difficult in high-density DRAMS. Fig. 4 shows the improved parity check matrix and the layout of the transmission-type XOR circuits. By rearranging the column vectors so that every two adjacent column vectors have complementary values, the layout pitch of transmission-type XOR circuits becomes the pitch of two sense amplifiers. B. Error Syndrome Generutor The Hamming code ECC technique with m data bits and k check bits checks the data by calculating the syndrome

Fig. 3.

Block diagram of an ECC circuit

In this article, a new type of Hamming code ECC technique, which satisfies the requirements of high reliability and fast column access mode, will be described. In this ECC technique an ECC data group is formed with memory cells associated with the same word line that can be checked simultaneously.

CODEECC TECHNIQUE 11. A NEWHAMMING Fig. 2 shows the basic concept of this Hamming code ECC technique. In this figure a Hamming code is formed with eight data bits and four check bits. Those 12 cells are selected by the same word line. A single error bit in these 12 memory cells can be detected by calculating the syndrome S according to the parity check matrix H. The syndrome S points out an error bit location. For example, if the syndrome S is the ith column vector of the parity check matrix H , the data bit X I is found to be erroneous, and if the syndrome S is zero vector, the data bit Xi's are all correct. Fig. 3 shows the block diagram of this ECC circuit. The transmission-type XOR circuits generate the syndrome of

S=H*X+C (11 where S = ( S I , . ., . S,) is the syndrome, H is the parity check matrix, X = ( X I ; . ., X,,) is the data bit data, and C = (Cl;. . , C A ) is the check bit data. If data bits X are all correct, the syndrome S becomes 0, and if X , is erroneous, the syndrome S is the ith column vector of H. The output of the error syndrome generator E = (E,;. ., E,) is the

52

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.

24.

NO.

1. FEBRUARY 1989

MATCH

... .
PREAMP LATCH -El

- Ek

WDE

~i~

Dout

Fig. 5. Block diagram of 1/0 control circuits

1010101010101010 1001100110010110 O~IOIOOIOIIOO~OI 0101011010100101 0101010101011010

H=

i th column vector of H , when the memory cell data X , are selected by the column address signals. Thus the error of data bit X , can be detected when the syndrome S is the same as the output of error syndrome generator E. When the data X , are to be renewed in the WRITE operation, check bit data C must be changed to
C+E

ark
L-J

(2)

where E is the output of error syndrome generator, if a) b)

X , is correct and inverted in this WRITE cycle, or X , is not correct and not inverted in this WRITE cycle.

Fig. 6.

Block diagram of the column decodcr

The output of the error syndrome generator is used to detect the error of the selected data and to designate the check bits to be inverted. Fig. 5 shows the block diagram of the 1 / 0 control circuits. The signal MATCH is the output of the comparator which compares the syndrome with the output of the error syndrome generator. In the READ cycle, the selected cell data are inverted by the XOR circuit according to the signal MATCH. In the WRITE cycle, check bit data are amplified and held in the latch circuits. Then the tri-state buffers rewrite the complementary values of the latched data into the check bit cells, according to the AND signals of error syndrome E and the signal CHANGE. The signal CHANGE becomes H when check bits must be changed, that is, when MATCH = 1 and the input data are the same as the selected cell data, or when MATCH= 0 and the input data are different from the selected cell data.

C. Column Decoder

To minimize the increase of chip size, it is desirable to share the column decoder and the syndrome decoder. Fig. 6 shows the decoding scheme of the column decoder. The column decoder is composed of an upper address decoder and a lower address decoder. The upper address decoder selects an ECC data group, and the lower address decoder selects a cell to be accessed. In this figure y, Z,, and W, denote predecoded address signals. In the WRITE cycle, all W, signals and the selected Z , signal become L and the selected y signal becomes H, while in the READ cycle or refresh cycle the selected Z , signal becomes L and all W, signals and the selected signal becomes H. In the error correction operation of the refresh cycle, the address converter transforms the syndrome signal into the predecoded address signals of the column decoder.

FURUTANI

et U/.:BUILT-IN HAMMING

CODE ECC CIRCIJIT FOR DRAM'S

53

....
DECODER BUFFER

and the address converter. That is not significant because the correcting operation occurs in the refresh cycle.

D. Architecture
The operating time of transmission-type XOR circuits increases rapidly as the number of stages increases. Therefore the appropriate length of data bits must be chosen, because the number of XOR circuits is half of the data bit length plus one. Fig. 8 shows a block diagram of the memory cell array. The memory cells selected by a word line are divided into plural Hamming code data groups to minimize the operating time of the XOR circuits. When a word line activates one row of the memory cell array, the syndrome of every Hamming code data group is generated by the transmission-type XOR circuits. Thus the syndrome for every ECC data group on the same word line is generated before the operation of the column decoder. The upper column address decoder selects the syndrome of the Hamming code data group to which selected memory cells belong, and activates the lower decoder. The error syndrome generator and address converter are basically ROM circuits, whose size is proportional to the data bit length of an ECC code. Thus the size of the syndrome generator and the address converter is reduced by using smaller data bit length. The speed of transmission-type XOR circuits dominates the operating time of the ECC circuits. The two-tier transmission-type XOR circuits are important for fast ECC operation [ 3 ] , [6]. Fig. 9 shows the pattern layout of the two-tier XOR circuits with a 4-poly 2-A1 DRAM process.

PREDECODER

Ai

Fig. 7. Block diagram of the address converter

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UPPER ADD.

Sk LOWER
ADD.

Fig. 8. Block diagram of parity checker.

IV. PERFORMANCE ESTIMATION

The built-in ECC circuits reduce the alpha-particleinduced soft error rate in return for the chip size increase and access-time penalty. In this section, the performances of the Hamming code ECC technique and the HV parity code ECC technique are estimated.
A. Chip Size Increase and Access-Time Penalty

Field

Metal

Main Bit Linb 0

2 Sonse Amp.

I
Fig. 9. Layout of two-tier XOR circuits.

Fig. 7 shows a block diagram of the address converter. In READ or WRITE cycles the outputs of the predecoder are transmitted to the column decoder. In the correcting cycle, the transformed signals of the syndrome are transmitted to the column decoder. The column address decoding time is the sum of the operation time of the predecoder and the column decoder, while the syndrome decoding time is the sum of the operating time of the address converter and the column decoder. Thus the difference between the two operating times is the operating time of the predecoder

Fig. 10 is a memory cell array of a DRAM with main-subbit-line structure [2]. This structure is adequate for the built-in ECC circuit, because a large number of memory cells can share the built-in ECC circuit. This figure assumes that a memory cell array is divided into four subarrays. Each subarray has 1-kbit word lines and 2-kbit main sense amplifiers. Fig. 11 shows the estimated increase in chip area. Table I shows the assumed size of circuit elements in this estimation. In this table. p is the total number of columns including data bits and parity bits, q is the number of columns for one ECC data group, and d is the pitch of sub bit lines, as shown in Fig. 8. With the HV parity code ECC circuit, chip overhead is reduced as the data bit length increases, because almost all of the additional chip area is occupied by parity bit cells.

54

IEEE JOURNAL OF SOLID-STATL CIRCUITS, VOL.

24. NO. 1. FEBRUARY 19x9

1 2 t

16

32

64

128 256 512 1024 2048

DATA BIT LENGTH

Fig. 12. Operating time characteristics of parity checker

Fig. 10. Schematic of a DRAM with built-in ECC circuit

z a W a a

40

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4
0 20I

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64

128 256 5 1 2 1 0 2 4 2 0 4 8

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DATA BIT LENGTH

Fig. 11. Comparison of chip overhead.

TABLE I ESTIMATED SIZEOF ECC CIRCUITS

Memory cell CMOS Sense amp. Column Decoder
XOR c i r c u i t

REFRESH
, .

2.Zd X lOOd X

d 4d

20

40

60

80 XOR

Fig. 13. Timing diagram or main bit lines and length is 1ZX.)

circuit. (Data bit

150d X 4 p d
40d X 8d

Address converter
Error s y n d r o m e dec.

3OOd X 44d 300d X 4qd

With the Hamming code ECC circuit, as the data bit length increases, additional area occupied by the error syndrome generator and the address converter increases, while the ratio of the number of check bits to the number of the data bits decreases. Thus there is an optimum point in the data bit length where the chip overhead becomes minimum. The optimum data bit length for a DRAM in Fig. 10 is about 256 with about 20-percent increase of the chip area. Fig. 12 shows the simulated results of operation time of the transmission-type XOR circuits with two-tier configuration. The number of XOR circuits is proportional to the data bit length with the Hamming code, while with the HV parity code the number of XOR circuits is proportional to

the square root of the data bit length. Thus the operating time increases rapidly as the data bit length increases, if the Hamming code is employed. Therefore data bit length of 128 is appropriate for a DRAM with the Hamming code ECC of Fig. 10, considering the chip overhead and the operating time of the parity checker. Although the operating time of the parity checker in the Hamming code ECC is longer than that of the HV parity code ECC, the access time is not degraded, because the operation of the parity checker can precede the operation of the column decoder. Fig. 13 shows simulated waveforms of the Hamming code ECC circuit. The transmission-type XOR circuits check all data bits on a word line immediately after the operation of the main sense amplifier. Thus the column access time in the page mode is not affected by the ECC operation. In the WRITE cycle, selected cell data and check bit data are renewed after READ operation. Thus the WRITE operation takes a longer operation rate than the READ operation.

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al.: BUILT-IN

HAMMING CODE ECC CIRCUIT FOR DRAMS

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Fig. 14 shows the estimated soft error rate. When there are some defects in the chip, the Hamming code ECC circuit and HV parity code ECC circuit have almost the same soft error rate. This is because both of the ECC techniques have only single-error-bit correction capability. For a device without defects the Hamming code ECC circuit has a soft error rate about 100 times smaller than that of the HV parity code ECC circuit. Thus, to make the best use of the Hamming code ECC, the redundancy technique [7] is still important.

WITHOUT DEFECT

V. CONCLUSIONS
HAMMING CODE

32

64

128 256 5 1 2

DATA BIT LENGTH

Fig. 14. Estimated soft error rate

B. Soft-Error-Rate Reduction The main purpose of employing a built-in ECC circuit is to reduce the soft error rate. The ECC circuit checks the memory cell in the refresh cycle. Error-correcting period ro is to = N / m .tref

By forming the Hamming code with cells that are selected by an identical word line, the Hamming code ECC can be implemented with less than 20-percent chip overhead and less access-time penalty. By combining the redundancy technique, the Hamming code ECC has a soft error rate about 100 times smaller than that of HV parity code ECC. The Hamming code ECC is suitable for the fast column access mode because one row of memory cells is checked at a time when they are selected by the word line.

(3)

ACKNOWLEDGMENT The authors wish to thank Dr. K. Shibayama, Dr. T. Nakano, and Dr. M. Yamada for their advice and encouragernent.

where N 2 is the total number of memory cells, m is the number of memory cells which are checked in one refresh cycle, and rr,, is the refresh cycle time. For the Hamming code ECC circuit m becomes the number of data bits, while for the basic HV parity code ECC circuit m becomes 1. The correcting period of the Hamming code ECC circuit is shorter than that of the HV parity code ECC. Soft error rate A,,= with an error-correcting period to is given by the following equation [3]:

REFERENCES
(11 Micron Technology Inc., Boise. ID. MT1256/MT4064 data sheet, 1984. [2] T. Mano er ul., Circuit technologies for 16M-bit DRAMs, in ISSCC Dig. Tech. Pupers, Feb. 1987, pp. 22-23. [3] J. Yamada. Selector-line merged built-in ECC technique for DRAMs, I E E E J . Solid-Srure Circuits. vol. SC-22. pp. 868-873, Oct. 1987. [4] T. Yamada et ul., A 4-Mbit DRAM with 16-bit concurrent ECC, I E E E J . Solid-Sture Circuirs, vol. 23, pp. 20-26, Feb. 1988. [SI S. Shozo er al., A l,-,Mbit CMOS DRAM with fast page mode and static column mode, IEEE J . Solid-Stute Circum, vol. SC-20. pp. 903-908. Oct. 1985. [6] H. L. Davis, A 70-11s word-wide 1-Mbit ROM with on-chip errorcorrection circuits, I E E E J . Solid-Srure Circuits. vol. SC-20. pp. 958-963, Oct. 1985. [7] S. E. Schuster, Multiple word/bit line redundancy for semiconductor memories, I E E E J . Solid-Sture Circuirs, vol. SC-13, pp. 693-703. Oct. 1978.

A,,,

( 1+ m,/m,)N2MSo

. ( ( 1- d + rs(ml + m,)MSoto/2)

(4)

where m , and m , are the data bit and parity bit length, M is alpha-particle flux density, So is the effective cell area, and rs denotes the percentage of the ECC data group without hard error bit. When a device contains defective memory cells and alpha flux density is small, the soft error rate A e c c becomes approximately

A,,,=

(1-r,)(l+m2/m,)N2MSo

(5)
KiSohiro Furutani was born in Osaka, Japan, on October 6, 1960 He received the B S and M S. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 1983 and 1985, respectively He joined the LSI Research and Development Laboratory. Mitsubishi Electric Corporation, Itami. Hyogo, Japan, in 1985 Since then he has been engaged in the design of MOS dynamic memories. Mr. Furutani is a member of the Institute of Electronics, Information and Communication Engineers of Japan.

that is, the soft error rate with the ECC operation becomes the soft error rate without the ECC operation multiplied by the defect density. When a device is free of defects, the soft error rate is

A,,,

(1+ m 2 / m , ) N 2 M 2 S ~ ( m +lm , ) t 0 / 2

(6)

and proportional to the error-correcting period code length m , m,.

r,

and the

56

Kamtami Arimoto (MXX) uas born in Wakayama. Japan, on March 9. 1957 He receked the B.S. and M.S. degrees in electric engineering from Osaka Univerhity. Osaka, Japan. in 1979 and 19x1. respectively. He joined the LSI Research and Development Laboratory. Mitsubishi Electric Corporation. Itami. Hyogo. Japan. in 19x1 Since then he has been engaged in the design of VLSI MOS dynamic RAMs. His current interest is design development and characterization of devices for advanced memory applications. M r Arimoto is a member of the Institute of Electronics. Information and Communicatic In Engineers of Japan.

In 1980 he joined the LSI Research and Development Laboratory. Mitsubishi Electric Corporation, Itami. Hyogo, Japan. Since then he has been engaged in the design of MOS dynamic memories and ASIC RAMs. His current research interests include associative memories and parallel distributed processing systems. Mr Kobayashi is a member of the lnstitute of Electronics, Information and Communication Engineers of Japan.

Hiroshi Mi!anioto (MXX) uah born in Shiga. Japan, on July 27. 1955. He rcccived the B.S. degree in electric engineering from the Univcrsitv of Osaka Prefecture. Osaka, Japan. in lY79. and the M.S. degree in engineering of physical electronics froin the Tokyo Institute of Technology. Tokyo. Japan. in 19x1. He joined the LSI Research and De\elopment Laboratory. Mitsubishi Electric Corporation. Itami. Hyogo, Japan. in April 19x1. Since then he has been engaged in the design of NMOS and CMOS dynamic memories. Mr. Miyamoto is a member of the Institute of Electronica. Jnforrnation and Communication Engineers of Japan.

i +

Ken-ichi Yawda \\as born in Osaka. Japan. on March 1. 1061. He rccei\cd the B.S. degree in physics from Kobe Universit). Kobe. Japan. in 1984. He joined the LSI Research and Dewlopnient Laborator?. Mitsubishi Electric Corporation. Itami. Hyogo. Japan. in April 1984. Sincc then he has becn eneaecd in the deLcloDnient of VLSI MOS d\narnic RAM\
I

Toshifurni Kobayashi (M88) u a s born in Okayama. Japan. on August 14. 1955. He received the B.S. and M.S. degrees in electronic engineering f r o m Okayama Unikersity. Okayanla. Japan. in 1978 and 19x0. rcspectively.

Koichiro Marhiho (MXX) mac born in Shizuoka. Japan, on J u h 19. 1952 He recaked the B S and M S degrees in phksm from the Uni\er%t\ of Toklo. Tokyo. Japan. in 1975 and 1977. re\peiti\ely. and the Ph D degree in electrical engineering from O d a Umbersit\. Osaka. Japan. in 1 Y X X He joined the LSI Research and DeLelopment Laboratorv. Mit\ubishi Electric Corporation. $ P Itami. Hhogo. Japan. in April 1977 Since 1Y7X he has worked on the design and development of MOS n~emorie\ including 64-kbit, 256-kbit. and 4-Mblt DRAMs. and 256-kbit dual-port DRAMs He ir currcntlL intere\ted in memon management and cache controller units, neural networks. reduced in\truition \et computer\, and artificial intelligence