IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO.

3, MARCH 2010

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Transient Simulation of Microwave SiC MESFETs With Improved Trap Models

Hans Hjelmgren, Member, IEEE, Fredrik Allerstam, Kristoffer Andersson, Member, IEEE, Per-ke Nilsson, and Niklas Rorsman

AbstractMeasured and simulated transient characteristics of a SiC metalsemiconductor eld-effect transistor are compared. Self-heating, gate tunneling, substrate, and surface traps are taken into account in the simulations. By explicitly lling surface traps at the vicinity of the gate during pinchoff, close correspondence between simulated and measured gate lags is achieved. Index TermsCharge carrier processes, MESFET power ampliers, microwave transistor, silicon carbide, technology computer-aided design (TCAD).

I. I NTRODUCTION HE SiC MESFET technology is a candidate for highpower microwave applications [1][4]. Its wide bandgap and high thermal conductivity offer several advantages compared to Si- and GaAs-based technologies. The inuence of surface traps on device performance has been investigated by different types of deposited and grown oxides [5]. Oxide interfaces with a high trap density resulted in devices with degraded large-signal performance. These observations indicate that surface traps affect the device characteristics and performance and must be accounted for in the simulation of the SiC MESFET. Improvements in large-signal performance by the use of eld plates (FPs) indicate that the gate lag is at least partly correlated to the electric eld strength at the drain side of the gate. The purpose of this brief is to implement a physically sound technology computer-aided design (TCAD) model of a SiC MESFET suitable for large-signal simulations in a commercial simulator. For a detailed description of the physical models, we refer to the Synopsys Sentaurus Device Manual [6] and previous calibration against measured dc and ac characteristics [7]. II. D EVICE S TRUCTURE AND M ODEL PARAMETERS The device epitaxial includes a high-purity semi-insulating (HPSI) 4H-SiC substrate, a p-buffer (5 1015 cm3 ), an

Fig. 1. an FP.

Schematic of a SiC MESFET structure, including a buried gate and

n-channel (2.8 1017 cm3 ), and a heavily n-doped cap layer (2 1019 cm3 ) for ohmic contacts (Fig. 1). A detailed description of the processing can be found elsewhere [5], [8]. The nominal recess depth of 80 nm in the MESFET fabrication was reduced to 74 nm in the simulation to obtain the right dc for low drain currents (low heating), which is well within process variations [5]. This modication also compensates for other uncertainties (e.g., doping concentration and epitaxial layer thickness). Pulsed I V curves were measured with a dynamic I V analyzer (Accent D225) [9] on transistors with two 50-m-wide parallel gate ngers. Electrothermal effects like self-heating are modeled by coupling the heat transport equation to the drift-diffusion equations, assuming that all generated heat dissipates through the bottom of the device. The effective thermal resistance Rth at the bottom was set to 2.00 103 cm2 K/W to get the right degradation of the dc for high currents (large heating). The thermal capacitivity of SiC is set to 2.216 J K1 cm3 [10], and the temperature dependence of the thermal conductivity is modeled as (T ) = 1 . 0.00140 T 0.176 (1)

Manuscript received November 11, 2009. First published February 2, 2010; current version published February 24, 2010. This work was supported by the Swedish Governmental Agency of Innovation Systems (VINNOVA), Swedish Energy Agency, Chalmers University of Technology, Ericsson AB, Furuno Electric Company, Ltd., Inneon AG, Norse Semiconductor Laboratories AB, Norstel AB, NXP Semiconductors BV, and Saab AB, under the Microwave Wide Bandgap Technology project. The review of this brief was arranged by Editor C. McAndrew. The authors are with the Microwave Electronics Laboratory, Chalmers University of Technology, 412 96 Gteborg, Sweden (e-mail: hans.hjelmgren@ chalmers.se). Digital Object Identier 10.1109/TED.2009.2039679

Bulk traps are dened in the HPSI substrate (black region in Fig. 1), resulting in a semi-insulating substrate containing 2.6 1015 cm3 deep electron traps [7]. The capture cross section + ) (CCS) for the deep donor level due to carbon vacancies (VC 15 2 cm [11]. Surface traps are added along was set to 3 10 the SiC/SiO2 interfaces marked with thick black arrows. Measured surface trap characteristics for two different oxides are listed in Table I [5]. All energy levels are discrete, and the thermal velocity is calculated from vth = 1.9 107 T /300 cm/s [14], where T is the local lattice temperature.

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TABLE I S URFACE ACCEPTOR T RAPS AT THE SiC/SiO2 I NTERFACE [5], [12], [13]

Fig. 3. Simulated gate lags without and with ITP compared to measurements. Simulations with ITP are plotted for two different CCS for NITs. Measured and simulated dc values are included for comparison.

Fig. 2. Simulated and measured drain lags. Measured and simulated dc values are included for comparison.

Schottky barrier tunneling (SBT) current is included by activating the nonlocal tunneling model [6], calculating the tunneling probabilities from the WentzelKramersBrillouin approximation with a tunneling mass of 0.66 me . Out of three supported tunneling models, this is the most versatile tunneling model. The entire barrier prole between the points of tunneling is taken into account, thus making it a nonlocal model. The SBT gives rise to a small number of electrons within the depletion region that might get captured at surface traps. Electrons in the gate metal may also reach surface traps by means of surface conduction [15], [16]. Since the emission time of trapped electrons is rather long, even a small current is sufcient to ll a large number of surface traps. However, only traps in close proximity to the gate are accessed by direct tunneling from the gate. We propose that traps further away from the gate be populated through trap-assisted tunneling (TAT) (hopping conduction) along the surface. Since the TAT models supported by the software are not suitable for our structure where the oxide/semiconductor interface is orthogonal to the metal/semiconductor interface, we simulated the effect of TAT by explicitly lling the traps on the drain side within 0.30 m from the gate (corresponding to the depletion width in pinchoff) before launching a transient gate lag simulation. This will be referred to as initial trap populating (ITP). III. R ESULTS AND D ISCUSSION Simulated and measured transients are shown in Figs. 2 and 3. The drain and gate voltages were stepped from three different quiescent points (Vgsq , Vdsq ) to one specic nal voltage (Vgs = 0 V, Vds = 20 V), while the drain current was measured versus time. The drain lag was measured by starting with the device turned off, i.e., Vgsq = Vdsq = 0 V, while the gate lag measurement started from pinchoff, Vgsq = 13 V, Vdsq = 20 V. To get the dc, we also performed a measurement without changing the terminal voltages, i.e., Vgsq = 0 V, Vdsq = 20 V.

The simulated drain lag in Fig. 2 is constant up to 10 ns. The initial current reduction after 100 ns is caused by electron + ) underneath the gate. trapping in deep substrate traps (VC The corresponding build-up of a negative space charge blocks the leakage current through the substrate. The large reduction in drain current after 1 s is where the self-heating starts to degrade the electron mobility. The remaining simulated drain lag after 10 s is also related to the lling of substrate traps. Fig. 4 shows simulated contour plots of the space charge density at four different times during a drain lag simulation. Immediately after the drain voltage step, very few electrons are trapped in the substrate [Fig. 4(a)]. Substrate traps just underneath the gate are lled after 1 s [Fig. 4(b)], but substrate traps toward the drain are still unoccupied after 1 s [Fig. 4(c)]. It is the same kind of traps, but the lling current is much smaller since the leakage current is blocked by the negative space charge underneath the gate. Eventually, substrate traps toward the drain get lled [Fig. 4(d)], and the corresponding negative space charge depletes the channel from below, thus increasing the drain access resistance. Without an efcient lling current, the lling of traps toward the drain becomes an extremely slow process. In a real device, optically generated carriers should speed up this process. It is not fully understood why the measured drain lag after 10 s is higher than simulated. It can be caused by a higher boron concentration, a less effective p-buffer, or even the lling of surface traps. Although the inclusion of SBT resulted in a substantial increase (a factor of 104 ) of surface trapped electrons within the depletion region during pinchoff, without ITP, simulated gate lag is still far from measured (Fig. 3). The current reduction due to thermal degradation of the mobility is clearly seen, but the effect of surface traps is negligible. Including ITP gives an excellent correspondence of measured and simulated drain currents. The agreement is further improved by decreasing the CCS for near-interface traps (NITs) from 1 1019 to 1 1020 cm2 , which is within published results [17]. Fig. 5 shows contour plots of the electron density at three different times during a gate lag simulation. Fig. 5(a) shows the electron distribution immediately after the gate voltage step, when the bulk of the channel is still depleted. At the right corner of the gate, there are a small number of gate tunneling electrons. The distribution of surface trapped electrons after 1 s is still close to that in pinchoff, and the virtual gate narrows the

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HJELMGREN et al.: TRANSIENT SIMULATION OF MICROWAVE SiC MESFETs WITH IMPROVED TRAP MODELS

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Fig. 4. Contour plots of the space charge density for a drain lag simulation. (a) Directly after the device is turned on (1 ps). (b) After 1 s. (c) After 1 s. (d) After reaching stationary conditions. The contour plots are for = 1 1015 , 2 1015 , and 3 1015 cm3 .

Fig. 6. Comparison of measured (symbols) and simulated (lines) SR versus FP length for passivations A (black) and B (gray). Passivation B is simulated for four different initial NIT populations at pinchoff.

Fig. 5. Contour plots of the electron density n for a gate lag simulation. (a) Directly after the device is turned on (1 ps). (b) After a while (1 s). (c) After reaching stationary conditions (10 min). The contour plots are for n = 109 , 1010 , . . . , 1019 cm3 .

electron ow to the right of the gate [Fig. 5(b)]. Depending on the CCS, near-interface trapped electrons are released after 110 s, but it takes 1015 min to clear deep interface traps (DITs) and reach the stationary conditions in Fig. 5(c). Apart from introducing ITP and reducing the CCS of NITs, we have not modied any other parameter to improve the agreement with measured drain and gate lags. The gate recess depth dgr and thermal resistance Rth mentioned above were calibrated against dc characteristics. The slump ratio (SR) in Fig. 6 is determined from the ratio between the drain currents for Vgs = 0 and Vds = 10 V pulsing from two different quiescent points, with a pulse length of 0.5 s and a duty cycle of 1 ms, i.e., SR = Id (Vgs = 0, Vds = 10)
Vgsq =13,Vdsq =20 Vgsq =Vdsq =0

The numerator of (2) is determined from a gate lag simulation with ITP. Measured SRs are slightly better than simulations with 100% ITP. Assuming 80% ITP for NITs (the slower DITs are still 100% lled) in sample A, the agreement is good up to a 350-nm FP. This initial improvement with FP length is due to less trapped electrons outside the explicitly lled interface. However, for still longer FPs, the simulated SR saturates, while the measured continues to increase. By assuming that ITP for NITs decreases with FP length (due to a reduced lateral electric eld and, consequently, a lower trap lling current), it is possible to obtain good agreement for all lengths (Fig. 6). IV. C ONCLUSION The inclusion of bulk traps in the HPSI substrate has resulted in good agreement with measured drain lags. The lling of substrate traps is a rather intricate problem where partly lled regions delay the lling of deeper still-empty traps. To simulate any gate lag in a SiC MESFET with surface acceptors situated close to the conduction band, there has to be a trap lling current during pinchoff. The reverse-biased metal gate is the most likely source for this trap lling current. Due to the rather

Id (Vgs = 0, Vds = 10)

(2)

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long emission time of trapped electrons, they will stay trapped for some time after the transistor is turned on, thus giving rise to a virtual gate that causes gate lag. Furthermore, by reducing the occupation of NITs for long FP devices during pinchoff, it is possible to obtain good agreement between measured and simulated SR versus eld plate length. R EFERENCES
[1] M. Franco and A. Katz, Class-E silicon carbide VHF power amplier, in Proc. IEEE MTT-S Int. Microw. Symp., Jun. 2007, pp. 1922. [2] Y.-S. Lee and T.-H. Jeong, A high-efciency class-E power amplier using SiC MESFET, Microw. Opt. Technol. Lett., vol. 49, no. 6, pp. 1447 1449, Jun. 2007. [3] L. Risso, A. Armoni, and L. Petachi, A 225400 MHz WiMAX 20 W SiC power amplier, in Proc. 2nd Eur. Microw. Integr. Circuit Conf., Oct. 2007, pp. 493496. [4] M. Sdow, K. Andersson, N. Billstrm, J. Grahn, H. Hjelmgren, J. Nilsson, P.-. Nilsson, J. Sthl, H. Zirath, and N. Rorsman, An SiC MESFET-based MMIC process, IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 40724078, Dec. 2006. [5] P.-A. Nilsson, F. Allerstam, M. Sdow, K. Andersson, H. Hjelmgren, E. . Sveinbjrnsson, and N. Rorsman, Inuence of eld plates and surface traps on microwave Silicon carbide MESFETs, IEEE Trans. Electron Devices, vol. 55, no. 8, pp. 18751879, Aug. 2008. [6] Sentaurus Device User Guide, Synopsys, Mountain View, CA, Sep. 2008. ver. A-2008.09. [7] H. Hjelmgren, K. Andersson, J. Eriksson, P.-. Nilsson, M. Sdow, and N. Rorsman, Electro-thermal simulations of a microwave 4H-SiC MESFET on high purity semi-insulating substrate, Solid State Electron., vol. 51, no. 8, pp. 11441152, Aug. 2007. [8] K. Andersson, M. Sudow, P. A. Nilsson, E. Sveinbjornsson, H. Hjelmgren, J. Nilsson, J. Stahl, H. Zirath, and N. Rorsman, Fabrication and characterization of eld-plated buried-gate SiC MESFETs, IEEE Electron Device Lett., vol. 27, no. 7, pp. 573575, Jul. 2006. [9] P. Baylis, II and L. P. Dunleavy, Performing and analyzing pulsed current-voltage measurements, High Freq. Electron., vol. 3, no. 5, pp. 6469, May 2004. [10] L. Hitova, R. Yakimova, E. P. Trifonova, A. Lenchev, and E. Janzn, Heat capacity of 4H-SiC determined by differential scanning calorimetry, J. Electrochem. Soc., vol. 147, no. 9, pp. 35463547, Sep. 2000. [11] F. Nava, G. Bertuccio, A. Cavallini, and E. Vittone, Silicon carbide and its use as a radiation detector material, Meas. Sci. Technol., vol. 19, no. 10, pp. 125, 2008. [12] H. . lafsson, F. Allerstam, and E. . Sveinbjrnsson, On shallow interface states in n-type 4H-SiC Metal-Oxide-Semiconductor structures, Mater. Sci. Forum, vol. 389393, pp. 10051008, 2002. [13] F. Allerstam and E. . Sveinbjrnsson, A study of deep energy-level traps at the 4H- SiC/SiO2 interface and their passivation by hydrogen, Mater. Sci. Forum, vol. 600603, pp. 755758, 2009. [14] Y. A. Goldberg, M. Levinshtein, and S. L. Rumyantsev, Properties of Advanced Semiconductor Materials: GaN, AIN, InN, BN, SiC, SiGe. New York: Wiley, 2001. [15] C. Codreanu, M. Avram, V. Obreja, C. Voitincu, and I. Codreanu, Interface states and related surface currents in SiC junctions, in Proc. IEEE Int. CAS, 2003, vol. 2, pp. 297300. [16] R. Mahapatra, A. K. Chakraborty, N. Poolamai, A. Horsfall, S. Chattopadhyay, N. G. Wright, K. S. Coleman, P. G. Coleman, and C. P. Burrows, Leakage current and charge trapping behavior in TiO2 /SiO2 high- gate dielectric stack on 4H-SiC substrate, J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 25, no. 1, pp. 217223, 2007. [17] X. D. Chen, S. Dhar, T. Isaacs-Smith, J. R. Williams, L. C. Feldman, and P. M. Mooney, Electron capture and emission properties of interface states in thermally oxidized and NO-annealed SiO2 /4H-SiC, J. Appl. Phys., vol. 103, no. 3, pp. 033 701-1033 701-7, Feb. 2008. of TCAD.

Hans Hjelmgren (M91) received the Ph.D. degree in electrical engineering from Chalmers University of Technology, Gteborg, Sweden, in 1991. His thesis work dealt with numerical simulation of hot electrons in GaAs devices. After one year as a Postdoc with the University of Massachusetts, Amherst, he was with Ericsson Microelectronics, Stockholm, Sweden, for seven years, working on silicon technologies. He is currently an Associate Professor with Chalmers University of Technology. His main interest is different aspects

Fredrik Allerstam received the M.Sc. and Ph.D. degrees in electrical engineering from Chalmers University of Technology, Gteborg, Sweden, in 2003 and 2008, respectively. He is currently with the Microwave Electronics Laboratory, Chalmers University of Technology. His research interests are in passivation materials for SiC and GaN devices.

Kristoffer Andersson (S03M06) received the M.Sc. and Ph.D. degrees in electrical engineering from Chalmers University of Technology, Gteborg, Sweden, in 2001 and 2006, respectively. He is currently an Assistant Professor with Chalmers University of Technology. His research interests are in the area of characterization and modeling of wide-bandgap transistors.

Per-ke Nilsson received the Ph.D. degree in physics from Chalmers University of Technology, Gteborg, Sweden, in 1993. His thesis work dealt with SQUIDs in high-Tc superconductors. After a year as a Postdoctoral Fellow with the University of California, Berkeley, he returned to Sweden to work with silicon-carbide power devices at ABB and IMC. He has also worked with tunable lasers in InP at ADC, Sweden. In 2002, he returned to Chalmers University of Technology. His current research involves wide- and narrow-bandgap devices and monolithic microwave integrated circuits.

Niklas Rorsman received the M.Sc. degree in engineering physics and the Ph.D. degree in electrical engineering from Chalmers University of Technology, Gteborg, Sweden, in 1988 and 1995, respectively. His thesis work dealt with the development of InPbased HEMT and MMIC materials and processes, and modeling of HEMTs. From 1996 to 1998, he was with Ericsson Microwave Systems, Mlndal, Sweden, where he was involved in the modeling of IIIV devices and MMIC design. In 1998 he returned to Chalmers University of Technology as a Project Leader for a WBG device project. His current research involves processing and characterization of WBG devices and MMICs.

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