Sigma Delta DAC

Description A Sigma Delta DAC which converts a 16 bit word input stream at a low frequency e.g. 44 kHz to a single bit output stream at a higher frequency (maximum 2 MHz). This block could take the 16 bit output stream from e.g. a fft/ifft engine and create a single bit representation of this signal to be used for feeding a H-bridge driving a speaker (after a proper discrete low pass filter). Of course the 16 bit input could be a stored sound sample. The representation (or at least a mode) of the 16 bit words is compatible with the output of one of the existing discrete components which transform a SPDIF output (digital output from a CD player) to a 16 bit stream. Crystal Semiconductor has developed a chip which converts the digital output of a CD to 16 bit data words (which can be reached using an SPI interface). Evaluation of this block has been done in FPGA.

Interface

Features
Single bit Sigma Delta modulated DAC output and the inverted output 16 bit output gathered in one package for easy data logging during test 2nd order and 3rd order modulator loop Programmable OSR, setting the last data rate multiplication factor in the interpolation filter L2 Programmable delay on the single bit outputs to compensate for skew between the two complementary outputs

For further information please contact

Gert Jrgensen gj@delta.dk Bjarne Andersen gba@delta.dk

Verified in FPGA

DELTA Venlighedsvej 4 2970 Hrsholm Denmark Tel. +45 72 19 40 40 asic@delta.dk asic.madebydelta.com

1177.1

Signal description Signal name

VddD VssD System clock Reset Enable Input word (15:0) Output delay setting (2:0) Should not be implemented in 1st version Loop order Multiplication setting (1:0)

Direction
Power Power Input Input Input Input Input Digital supply voltage Digital ground 2 MHz system clock

Description

Reset all registers in the filter Starts conversion Setting the adjustable delay between the outp and outn single bit output to minimise the current consumption in e.g. a following Hbridge due to getting minimum skew between the two outputs 0: 2nd order loop used in the modulator, default 1: 3rd order loop used in the modulator 00: L0=2, L1=2, L2=8 01: L0=2, L1=2, L2=16 default 10: L0=2, L1=2, L2=32 11: L0=2, L1=2, L2=64 00: Not signed input 01: Signed input, default 10: Input compatible to output from SPDIF->16 bit stream converter 11: Not used 0: Default, input->interpolation filter and output comes from the noise shaping loop 1: Interpolation test mode, input->interpolation filter and output (package) comes from the interpolation filter 0: Default, input->interpolation filter and output comes from the noise shaping loop 1: Noise shaping loop test mode, input->noise shaping loop filter and output (package) comes from the noise shaping loop filter Single bit not inverted output Single bit inverted output 16 single bit output gathered in one package for easy data communication during test High when a package is filled and ready for transmission A 50% duty cycle clock for the transmission of packages

Input Input

Input mode (1:0)

Input

Interpolation mode

Input

Noise shaping loop mode

Input

Bit stream outp Bit stream outn Bit package (15:0) Package ready Package clock

Output Output Output Output Output

DELTA Venlighedsvej 4 2970 Hrsholm Denmark Tel. +45 72 19 40 40 asic@delta.dk asic.madebydelta.com

Schematic block diagram

The design of the Sigma Delta DAC can be split into two main components which can be evaluated separately. Interpolation filter Noise shaping loop
Block diagram of a Sigma Delta DAC

No Input stream word size fN Input data rate L Oversampling ratio OSR Block diagram of the interpolation filter

No Input stream word size fN Input data rate L Oversampling ratio OSR = L0L1L2

fX Intermediate data rate frequency LX Data rate multiplication factor X=0,1,2

DELTA Venlighedsvej 4 2970 Hrsholm Denmark Tel. +45 72 19 40 40 asic@delta.dk asic.madebydelta.com

Electrical characteristics Parameter

Supply voltage

Condition
Normal operation Reduced lifetime Operative but not within specification fsample=fsystem Vdd=[2.7 V;3.6 V] T=[-50C; 90C] -

Min
2.7 2.5 32 32

Type

Max
3.6 3.8

Unit
V V V MHz kHz A

System frequency Input sample rate Over sample rate Supply current Input voltage range Output voltage swing Digital inputs - High level - Low level Delay SNR

44.1 64

96 256

Vss Vss + 0.1 ?

Vdd 1 Vdd 0.1

V V V V s dB

? Vdd=[2.7 V;3.6 V] T=[-50C; 90C] - Input: 1 kHz sine Input: 1 kHz sine full swing at 16 bit fsystem=fsample=2 MHz Vdd=[2.7 V;3.6 V] T=[-50C; 90C]

DELTA Venlighedsvej 4 2970 Hrsholm Denmark Tel. +45 72 19 40 40 asic@delta.dk asic.madebydelta.com