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Diagonal 8mm (Type 1/2) CCD Image Sensor for EIA Black-and-White Video Cameras
Description
The ICX248AL is an interline CCD solid-state 20 pin DIP (Cer-DIP)
image sensor suitable for EIA black-and-white video
cameras with a diagonal 8mm (Type 1/2) system.
Sensitivity, smear, D-range, S/N and other
characteristics from visible light area to near infrared
light area, have been greatly improved compared
with the ICX038DLA through the adoption of EXview
HAD CCD TM technology.
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This chip features a field period readout system and
an electronic shutter with variable charge-storage time.
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Pin 1
This chip is compatible with and can replace the 2
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ICX038DLA.
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Features V
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(+12dB compared with the ICX038DLA, λ = 945nm) 12
• High sensitivity 3
H 40
(+9dB compared with the ICX038DLA, without IR cut filter) Pin 11
• Low smear (–15dB compared with the ICX038DLA)
• High D range (+2dB compared with the ICX038DLA) Optical black position
• High S/N (Top View)
• High resolution and low dark current
• Excellent antiblooming characteristics
• Continuous variable-speed shutter
• Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V)
• Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V)
• Horizontal register: 5V drive
Device Structure
• Interline CCD image sensor
• Image size: Diagonal 8mm (Type 1/2)
• Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels
• Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels
• Chip size: 7.95mm (H) × 6.45mm (V)
• Unit cell size: 8.4µm (H) × 9.8µm (V)
• Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction: Front 12 pixels, rear 2 pixels
• Number of dummy bits: Horizontal 22
Vertical 1 (even fields only)
• Substrate material: Silicon
TM
∗ EXview HAD CCD is a trademark of Sony Corporation EXview HAD CCD is a CCD that drastically improves light efficiency by including
near infrared light region as a basic structure of HAD (Hole-Accnmulation Diode) sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98728A99
ICX248AL
GND
VOUT
GND
φSUB
VDD
Vφ4
Vφ1
Vφ2
Vφ3
VL
10 9 8 7 6 5 4 3 2 1
Vertical Register
Note)
Horizontal Register
Note) : Photo sensor
11 12 13 14 15 16 17 18 19 20
GND
Hφ1
VDSUB
RD
Hφ2
VSS
φRG
GND
NC
VGG
Pin Description
–2–
ICX248AL
–3–
ICX248AL
∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used. (When CXD1267AN is used.)
∗2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
∗3 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used. (When CXD1267AN is used.)
∗4 Connect to GND or leave open.
∗5 The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a special
code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated voltage.
The adjustment precision is ±3%. However, this setting value has not significance when used in substrate
bias internal generation mode.
VSUB code E f G h J K L m N P Q R S T U V W
Optimal setting 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0
<Example> "L" → VSUB = 9.0V
DC Characteristics
Item Symbol Min. Typ. Max. Unit Remarks
Output circuit supply current IDD 5.0 10.0 mA
–4–
ICX248AL
Waveform
Item Symbol Min. Typ. Max. Unit Remarks
diagram
Readout clock voltage VVT 14.55 15.0 15.45 V 1
VVH1, VVH2 –0.05 0 0.05 V 2 VVH = (VVH1 + VVH2)/2
VVH3, VVH4 –0.2 0 0.05 V 2
VVL1, VVL2,
–9.6 –9.0 –8.5 V 2 VVL = (VVL3 + VVL4)/2
VVL3, VVL4
VφV 8.3 9.0 9.65 Vp-p 2 VφV = VVHn – VVLn (n = 1 to 4)
| VVH1 – VVH2 | 0.1 V 2
Vertical transfer clock
voltage VVH3 – VVH –0.25 0.1 V 2
VVH4 – VVH –0.25 0.1 V 2
VVHH 0.5 V 2 High-level coupling
VVHL 0.5 V 2 High-level coupling
VVLH 0.5 V 2 Low-level coupling
VVLL 0.5 V 2 Low-level coupling
∗1 Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven
with the following specifications.
Waveform
Item Symbol Min. Typ. Max. Unit Remarks
diagram
–5–
ICX248AL
Vφ1 Vφ2
CφV12
R1 R2
Hφ1 Hφ2
CφV1 CφV2 CφHH
CφV41 CφV23
CφH1 CφH2
RGND
CφV4 CφV3
R4 R3
CφV34
Vφ4 Vφ3
Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit
–6–
ICX248AL
II II
φM
φM
2
10%
0% 0V
tr twh tf
Vφ1 Vφ3
VVHL VVHL
VVHL
VVHL VVH3
VVLL VVLL
VVL VVL
Vφ2 Vφ4
VVHL
VVH2 VVHL VVHL VVHL
VVH4
VVLH VVLH
VVL2
VVLL VVLL
VVL VVL
VVL4
–7–
ICX248AL
tr twh tf
90%
VφH twl
10%
VHL
tr twh tf
VRGH
twl
Point A
VφRG
RG waveform
VRGL + 0.5V
VRGLH
VRGL
VRGLL
Hφ1 waveform
+2.5V
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
–8–
ICX248AL
100%
90%
φM
VφSUB φM
2
10%
VSUB 0%
tr twh tf
Hφ 20 20 15 19 15 19 ns
Horizontal
imaging
During parallel- Hφ1 5.38 0.01 0.01
serial µs
conversion Hφ2 5.38 0.01 0.01
During drain
Substrate clock φSUB 1.5 1.8 0.5 0.5 µs
charge
∗1 When vertical transfer clock driver CXD1267AN is used.
∗2 tf ≥ tr – 2ns.
two
Item Symbol Unit Remarks
Min. Typ. Max.
Horizontal transfer clock Hφ1, Hφ2 16 20 ns ∗3
∗3 The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
–9–
ICX248AL
768 (H)
14 14
12
V
10
H H
8 8 494 (V)
Zone 0, I 10
Zone II, II'
V
Ignored region
10
Effective pixel region
– 10 –
ICX248AL
Measurement conditions
1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions. (When used with substrate bias external adjustment, set the substrate voltage to the
value indicated on the device and connect VDSUB pin to GND or leare it open.)
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black (OB) level is used as the reference for the signal output, and the value measured at point [∗A] in the
drive circuit example is used.
1. Sensitivity
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/500s, measure the signal output (Vs) at the center of the screen and substitute the value into the
following formula.
500
S = Vs × [mV]
60
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with the
average value of the signal output, 200mV, measure the minimum value of the signal output.
3. Smear
Set to standard imaging condition II. Adjust the luminous intensity to 500 times the intensity with the
average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is
executed by the electronic shutter at the respective H blankings, measure the maximum value (VSm [mV])
of the signal output and substitute the value into the following formula.
VSm 1 1
Sm = × × × 100 [%] (1/10V method conversion value)
200 500 10
– 11 –
ICX248AL
5. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
7. Flicker
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal
output is 200mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then
substitute the value into the following formula.
8. Lag
Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.
FLD
V1
Light
Strobe light
timing
– 12 –
Drive Circuit 1 (substrate bias internal generation mode)
15V
100k
1 20
2 19
3 18
4 17 1/35V 1
XSUB
5 16
XV2 CXD1267AN –9V
6 15
XV1 3.3/16V
7 14
XSG1
8 13 22/16V
XV3 1M
9 12
XSG2
10 11
XV4
22/20V
3.3/20V 0.01
1 2 3 4 5 6 7 8 9 10
– 13 –
VL
Vφ1
Vφ2
Vφ3
Vφ4
VDD
φSUB
GND
VOUT
GND
ICX248AL
(BOTTOM VIEW)
VGG
Hφ2
Hφ1
NC
φRG
RD
GND
GND
Vss
VDSUB
20 19 18 17 16 15 14 13 12 11
47/
Hφ1 6.3V
390
0.01
100
[∗A]
CCD OUT
0.01 3.9k
RG
ICX248AL
Drive Circuit 2 (substrate bias external adjustment mode)
15V
0.1 15k
1 20 56k 270k
47k
2 19 1/35V
3 18 1/35V 100k 27k 15k
0.1 39k
4 17 1/35V 0.1
XSUB
5 16
XV2 CXD1267AN –9V
6 15 3.3/16V
XV1
7 14
XSG1
8 13 22/16V
XV3 1M
9 12
XSG2
10 11
XV4
VL
Vφ1
Vφ2
Vφ3
Vφ4
VDD
φSUB
GND
GND
VOUT
ICX248AL
– 14 –
(BOTTOM VIEW)
GND
Vss
VDSUB
VGG
Hφ2
Hφ1
NC
φRG
RD
GND
20 19 18 17 16 15 14 13 12 11
47/
Hφ1 6.3V
390
0.01
100
[∗A]
CCD OUT
0.01 3.9k
RG
ICX248AL
ICX248AL
1.0
0.9
0.8
0.7
Relative Response
0.6
0.5
0.4
0.3
0.2
0.1
0
400 500 600 700 800 900 1000
V1
2.5
V2
Odd Field
V3
V4
1.6 2.5 2.5 2.5
33.5
0.2
V1
V2
Even Field
V3
V4
unit: µs
– 15 –
Drive Timing Chart (Vertical Sync)
FLD
VD
BLK
HD
1
4
3
5
2
10
20
15
270
275
520
525
265
280
260
– 16 –
V1
V2
V3
V4
HD
BLK
H1
H2
3
5
2
1
2
2
1
3
3
2
5
1
1
3
20
40
10
10
20
10
22
30
20
768
760
– 17 –
RG
V1
V2
V3
V4
SUB
ICX248AL
ICX248AL
Notes on Handling
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation,
use either an elastic load, such as a spring plate, or an adhesive.
– 18 –
ICX248AL
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not
to perform the following actions as this may cause cracks.
• Applying repeated bending stress to the outer leads.
• Heating the outer leads for an extended period with a soldering iron.
• Rapidly cooling or heating the package.
• Applying any load or impact to a limited portion of the low melting point glass using tweezers or other
sharp tools.
• Prying at the upper or lower ceramic using the low melting point glass as a fulcrum.
Note that the same cautions also apply when removing soldered products from boards.
e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-
acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives.
(reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition
exceeding the normal using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) This CCD image sensor has sensitivity in the near infrared area. Its focus may not match in the same
condition under visible light /near infrared light because of aberration.
– 19 –
Package Outline Unit: mm
0° to 9°
20 11 11 20
~
C (R0.7) φ1.4
1.4
15.24
15.1 ± 0.3
(4.0)
11.55
V
7.55
3
~
H
0.55
0.25
B'
14.6 3 1. “A” is the center of the effective image area.
3.4 ± 0.3
0.7
~ 2. The two points “B” of the package are the horizontal reference.
0.4
The point “B'” of the package is the vertical reference.
– 20 –
3. The bottom “C” of the package is the height reference.
4. The center of the effective image area, relative to “B” and “B'” is
0.83
(H, V) = (9.0, 7.55) ± 0.15mm.
1.778 0.46
1.27
5. The rotation angle of the effective image area relative to H and V is ± 1°.
0.4 0.8
4.0 ± 0.3
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm.
0.3 M
7. The tilt of the effective image area relative to the bottom “C” is less than 60µm.
8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
PACKAGE STRUCTURE
9. The notch and the hole on the bottom must not be used for reference of fixing.
PACKAGE MATERIAL Cer-DIP