Research Lab II

Fabrication and characterization of organic field-effect transistors

Contact persons: Paul Mundt Room 156, Tel: 06151/ 16-6331 mundt@e-mat.tu-darmstadt.de Emanuelle Reis Simas Room 158, Tel.: 06151/ 16-6689 simas@e-mat.tu-darmstadt.de Meeting point: in front of room 158 Elmar Kersting Room 151, Tel: 06151/ 16-6358 kersting@e-mat.tu-darmstadt.de Andrea Gassmann Room 158, Tel.: 06151/ 16-6689 gassmann@e-mat.tu-darmstadt.de

1. Introduction In the last decade organic field-effect transistors (OFETs) have attracted a lot of interest due to their potential applications in the field of low cost and/or large area flexible electronic devices. One of the most investigated organic semiconductors for organic transistors is pentacene. The performance of pentacene-based transistors is greatly influenced by the morphology and the quality of the pentacene thin film and the trap states at the interface between pentacene and the gate insulator. In this practical course pentacene thin film transistors are fabricated and their electrical characteristics are measured. A surface treatment of the gate dielectric is carried out to modify the surface properties essentially codetermining the channel conductivity. 2. Organic semiconductors Organic semiconductors are carbon-based molecules that allow for the injection and transport of charge carriers. Due to their conjugated -electron system they feature an optical energy gap in the range of about 2-3 eV, spanning the energy spectrum from the near ultraviolet to the near infrared energy range. Organic semiconductors can be classified into two material classes: small molecules and polymers. While the electronic properties of both materials are more or less the same, they differ with respect to their processability. Small molecules are typically deposited by physical vapor deposition while evaporation of polymers leads to their decomposition. This is the result of their high molecular weight. That is why polymers are mostly processed from solution using usually spin coating or drop casting or common printing techniques. In a conjugated -system the carbon atoms are sp2-hybridized. The sp2-hybrid orbitals of neighboring C-atoms form - (bonding) and *-molecular states (anti-bonding), while the

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overlapping residual pz-orbitals lead to the formation of rather weakly bound - (bonding) and *-bonds (anti-bonding). The former result in strong sigma bonding while the latter form rather weak -bonds. Due to the weak exchange energy of the pz-orbitals the p-states split weakly and thus also the ,*-states determining the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO). In ideal small molecules electrons in -orbitals are delocalized over the entire mesomeric system. Yet, the conjugation length can be shortened due to impurities and molecular imperfections. Due to small intermolecular interactions the energetic splitting occurring during the formation of an organic solid is low, leading to a band width of less than 300 meV. Thus, the energetic distance between HOMO and LUMO in a molecular solid is very similar to the energetic splitting between the - and *-orbitals in a molecule. In each case the -electrons are responsible for the electronic properties of the respective organic semiconductor. Figure 1 sums up the evolution of energetic levels for a molecule build from C-atoms and for a molecular solid.

Figure 1 Schematic illustration of the energy diagram of an atom (left), a molecule (middle) and a molecular solid (right).

2.1. Charge carrier transport Due to their relatively high energy gap the intrinsic charge carrier density in organic semiconductors is very low (only about 1 cm-). Therefore, charge carrier transport has to be supported by excess charge carriers injected into the organic semiconductor from electrodes. These charge carriers are localized on individual molecules leading to an electronic polarization of the neighboring molecules. Depending on the distance between the molecules the degree of polarization can be different. Consequently, depending on the related polarization the energetic positions of the HOMO and LUMO states compared to the electronic states of an uncharged molecule change. Assuming a statistical distribution of the intermolecular interactions the polarization energies are also distributed statistically leading to a Gaussian distribution of the HOMO and LUMO states. This so-called Gaussian density of states (DOS) distribution is schematically depicted in Figure 2. In organic molecular crystals where the localization of an excess charge carrier on a molecule prevails, the charge carrier transport is a hopping process from one molecule to another. In principle, hopping transport can be described as successive tunneling processes. In the inset of

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Figure 2 three possible hopping occurrences are illustrated according to the Miller-Abrahams model in order to visualize the transport of electrons along the LUMO levels in an organic solid. For transitions 1 (isoenergetic tunneling) and 2 (energy dissipation after the isoenergetic tunneling), no thermal activation is necessary prior to the tunneling process. Such a thermal activation, however, is needed for transition 3, where a hop upwards in energy is required for the transport.

Figure 2 Distribution of the transport states in a molecular solid. Three different hopping transitions are illustrated in the inset. Only for transition 3 activation energy is required prior to the tunneling process.

The charge carrier transport in molecular crystals as well as in disordered molecular solids is dominated by a hopping transport for temperatures > 150 K. A good structural order of the solid, as it is found in molecular crystals, is beneficial for charge carrier transport. In particular for organic field-effect transistors the overlap of the -orbitals has to take place in the direction of charge carrier transport in order to lead to an increase in charge carrier mobility. The charge carrier mobility depends also on the amount of charges contributing to the hopping process: The higher the density of states is filled, the easier the charge carriers can hop from one HOMO or LUMO level to the next HOMO or LUMO level and the higher is the charge carrier mobility. 2.2. Charge carrier traps Energetic states in the energy gap above the HOMO or below the LUMO transport levels act as charge carrier trap states. Once a charge carrier is localized on these states it no longer contributes to charge carrier transport unless it is thermally activated to escape its trap. Nevertheless, trapped charge carriers influence other charge carriers by their electric field. The distribution of trap states can range from monoenergetic states to a random trap distribution. The origins of semiconductor trap states are of morphological or chemical nature. Morphological traps are usually due to grain boundaries or a local order / disorder of the molecular solid. On the other hand, chemical traps result from neutral doping or impurities in the organic semiconductor as well as from defects in the monomer units or chain irregularities. Furthermore, functional groups containing oxygen can significantly influence the charge carrier transport by the localization of negative charge [A. Kadashchuk et al., Journal of Applied Physics 98, 2 (2005)].

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3. The organic field-effect transistor 3.1. Operational principle and possible transistor geometries The organic field-effect transistor is a type of thin film transistor (TFT) that differs from the standard FET structure by its operational principle as well as by its processability. Inorganic FETs are widespread in today's electronic applications since their structure is compatible with common thin film techniques such as physical or chemical vapor deposition as well as solution-based processes such as dip or spin coating. Therefore, one of the main advantages of FETs is that they are not limited to a specific substrate. The working principle of an OFET is based on the field-effect that is schematically shown in Figure 3(a) for a metal-insulator-semiconductor (MIS)-diode. By applying a gate voltage VG mobile charge carriers, either thermally generated or injected from the source / drain electrodes, are accumulated at the insulator / semiconductor interface to compensate VG. This accumulation of charge carriers at the interface is called field-effect.

Figure 3 (a) MIS-diode with hole accumulation at the semiconductor / dielectric layer interface. (b) Bottom-contact bottom-gate transistor in hole accumulation (negative voltages applied).

As a result, the total amount of accumulated charge n and therefore the conductivity at the insulator / semiconductor interface can be controlled by the applied gate potential. The conductivity is defined as = ne with the charge carrier mobility and the elemental charge e. The dependency of the conductivity on the applied gate voltage is exploited in the transistor by dividing the upper electrode into two electrodes: They are called source and drain contact and define the transistor channel in between them. The setup of the resulting field-effect transistor is illustrated in Figure 3(b). A current can flow through the transistor channel by applying a voltage VD between the source and drain electrodes as long as the conductivity of the semiconductor layer is sufficiently high. Depending on the sign of the applied voltages either electrons or holes are accumulated in the transistor channel. Organic field-effect transistors represent an interesting extension to the transistor family. This is due to the promise of cheap role-to-role processability or the implementation of transistors on plastic substrates for applications such as flexible displays or RFID (radio frequency identification) tags. In Figure 4 (a) and (b) two typical standard OFET designs are illustrated: Figure 4 (a) depicts a top-gate configuration comprising bottom source / drain contacts, while in Figure 4 (b) a bottom-gate configuration with bottom source / drain contacts is illustrated. Both top- and bottom-gate configurations are also commonly implemented with a respective top or bottom source / drain architecture (not shown). The resulting typical four transistor structure combinations can be chosen in dependence of the application or material requirements.

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Figure 4 Possible device structures: (a) bottom contact top-gate and (b) bottom-gate bottom-contact transistor.

3.2. Current-voltage characteristics of an OFET The so called drain current ID flowing in the channel between the source and drain electrode in dependence on the applied voltages is defined by the Shockley equations:

Eq. 1
with W channel width, mobility, C VG areal capacitance, gate voltage, L VD channel length, drain voltage

In a FET the current transport occurs in the channel developing at the insulator / semiconductor interface. This channel is spatially limited to the charge carrier accumulation zone typically extending over the first few monolayers of the organic semiconductor. According to the Shockley equations the drain current depends both on the gate voltage as well as the drain voltage. Therefore, ID can be plotted as a function of the drain voltage at constant gate voltage (output characteristics) or as a function of the gate voltage at constant drain voltage (transfer characteristics). Ideal transistor characteristics are schematically illustrated in Figure 5.

Figure 5 Ideal output and transfer characteristics of a unipolar transistor.

In the output characteristics the drain current increases linearly at small drain voltages |VD| |VG| (linear regime) and is saturated at voltages |VD| > |VG| (saturation regime) as depicted in Figure 6 (a) and (b). In the transfer characteristics the drain current is increasing quadratically with the gate voltage for |VG| < |VD| and linearly for |VG| |VD|.

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Figure 6 Schematic illustration of the charge carrier accumulation in the (a) linear and (b) saturation regime of an OFET.

The above-mentioned considerations ignored trap states in the transistor channel or at the dielectric / semiconductor interface which may localize charge carriers otherwise available for current transport. Furthermore, it was neglected that mobile charge carriers might already be available in the transistor channel at zero gate bias. To account for these effects resulting in an effective gate voltage, a threshold voltage Vth is introduced into the Shockley equations:

Eq. 2 3.3. Effects of the dielectric / semiconductor interface on transistor performance In field-effect transistors charge carrier transport takes place at the dielectric / semiconductor interface within the first monolayers. Thus, electronic interface states may influence the charge carrier transport distinctly. For example it has been discovered that certain functional groups present at the dielectric surface hinder or even fully inhibit electron transport as they act as electron traps. The most prominent example of this effect is hydroxyl groups that are also present on SiO2 surfaces. Figure 7 illustrates the electron trapping mechanism of hydroxyl groups as proposed by Chua et al. [L. L. Chua et al., Nature 434, 7030 (2005)]. It is suggested that the trapping of an electron occurs alongside the dissociation of a hydrogen atom leading to the formation of a negatively charged oxygen ion at the dielectric interface. While hydroxyl groups act as electron traps they do not seem to influence the charge carrier transport of holes.

Figure 7 Electron trapping mechanism of hydroxyl groups as suggested by Chua and coworkers [L. L. Chua et al., Nature 434, 7030 (2005)].

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To overcome this problem and allow for electron transport a surface treatment to functionalize the hydroxyl groups (see chapter 4.2) or a second dielectric layer to cover them can be applied. Another advantage of surface treatments is that they can influence the thin film formation of the organic semiconductor and therefore impact the charge carrier transport properties. Further parameters like the pressure during the deposition, the growth rate and the temperature have also an effect on the development and as result the properties of the thin film. Figure 8 shows scanning electron micrographs of pentacene (a small molecule semiconductor) thin films deposited on differently treated substrates at different temperatures and different deposition rates. Depending on the deposition parameters and the treatment, the crystallite size and consequently the charge carrier mobility changed. SiO2 OTS-SiO2

Figure 8 Scanning electron micrographs of pentacene thin films deposited by organic vapor phase deposition onto (left) pure SiO2 and (right) SiO2 pre-treated with octadecyltrichlorosilane (OTS). Substrate temperature, deposition pressure, deposition rate, and resulting saturation hole mobilities are given [M. Shtein et al., Appl. Phys. Lett. 81, 2 (2002)].

3.4. Determination of the charge carrier mobility and the threshold voltage For OFETs two possibilities to calculate the charge carrier mobility based on the Shockley equations use either the output characteristics or the transfer characteristics. a) Calculation of mobility from the output characteristics The mobility is defined from the linear region (|VD| << |VG|) in the output characteristics according to equation 3:

Eq. 3

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In order to calculate the charge carrier mobility the drain current is plotted versus the gate voltage at a constant drain voltage from the linear region. In the ideal case, meaning that the mobility is not dependent on VG, the slope m of the resulting curve is proportional to the mobility. b) Calculation of mobility and threshold voltage from the transfer characteristics From the transfer characteristic both the threshold voltage and the mobility can be extracted if the square root of ID is plotted versus VG. The result is a monotonously increasing curve that increases first exponentially and then linearly. According to equation 4 the slope in the linear regime is proportional to the mobility. As is derived for voltages |VD| > |VG-Vth| it is called saturation mobility.

Eq. 4 Plotting the square root of ID versus VG also the threshold voltage can be determined. It is the axis intercept of the fitting curve for the linear regime. 4. Experimental 4.1. The substrates In the practical course the employed substrates consist of n-doped silicon serving as the gate electrode with a 230 nm thick thermally oxidized SiO2 dielectric layer on top (dielectric constant of SiO2 = 3.9). Already pre-structured interdigitated source / drain electrodes are available. The contact structure consists of a 30 nm thick gold layer deposited on a 10 nm thick ITO (indium tin oxide) adhesion layer and defines transistors with a channel length L of 20 / 10 / 5 / 2.5 m and a channel width of 10 mm, respectively. The structure is shown exemplarily in Figure 11. Employing these substrates the preparation of working devices is very easy, as only the organic semiconductor is left to be deposited.

(a)

(b)

Figure 11 (a) Schematic contact structure of the employed substrates that have already pre-structured source / drain electrodes. The resulting transistor exhibits L = 20 m and W = 10 mm. (b) Microscope picture of the transistor channel.

4.2. The organic semiconductor pentacene The acene pentacene is one of the most investigated organic semiconductors in organic transistors. Its chemical structure consists of a planar arrangement of five benzene rings as
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depicted in Figure 12 (a). Figure 12 (b) illustrates schematically the energy diagram of pentacene. The electron affinity EA of 2.9 eV and the ionization energy IP of 5.0 eV define an energy gap of 2.1 eV [J. Simon et al., Molecular semiconductors, Springer Verlag, 1985]. Pentacene can be processed via physical vapor deposition under high vacuum. The morphology and the electronic properties of the resulting layer are dependent on the surface of the used substrate or dielectric, the purity of the material and deposition parameters like evaporation rate, substrate temperature and pressure.

Figure 12 (a) Chemical structure and (b) energy diagram of pentacene.

In polycrystalline pentacene transistors a hole mobility of up to 1 cm2/Vs can be achieved at optimized deposition conditions [C. D Dimitrakopoulos at al., Advanced Materials 14, 2 (2002)]. This mobility is competitive to the charge carrier mobility in amorphous silicon. Therefore, pentacene is an interesting candidate for the application in organic circuits. In order to influence the pentacene growth on the dielectric layer and to reduce the traps at the SiO2 / semiconductor interface, the hydrophilic surface of SiO2 is modified by a surface treatment with a surfactant. In this practical HMDS (hexamethyldisilazane) (chemical structure illustrated in Figure 13 (a)) will be used. It forms a self-assembled monolayer (SAM) with alkyl chains towards the channel to modify the surface energy of the SiO2 gate insulator (see Figure 13 (b)) and decrease the traps induced by SiOH groups [H. Ohnuki at al., Thin Solid Films 516, 2747(2008)]. A HMDS-modification of SiO2 is a cheap and simple surface treatment method to investigate its impact on OFET performance.

H3C Si H3C
(a)

N Si

CH3 CH3 CH3

(b)

CH3

Figure 13 (a) Chemical structure of HMDS (hexamethyldisilazane) and (b) SiO2 surface that has been modified by a HMDS treatment; Me- denotes the methyl group.

4.3. How to build the OFETs As the used layers in a transistor are rather thin (ca. 50 nm) it is important to clean the substrates very carefully. The first step is cleaning two substrates twice in an ultrasonic bath for 15 min in acetone and isopropanol. Between these cleaning steps the substrates are washed with distilled water and dried with nitrogen, respectively. To make the SiO2 surface more hydrophilic and to remove organic adsorbates left on the surface the substrates are exposed to a 15 min

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ozone treatment. One of the two substrates is then treated with HMDS. For this, drip 3-4 drops of the liquid HMDS under the fume hood with a pipette on the ozone-treated substrate. After 30 s the substrate is dried with nitrogen. To deposit the semiconducting layer the substrates are first embedded in a sample holder and then inserted into the evaporation chamber by a shuttle system. At a pressure of ca. 10 -7 mbar a 50 nm thick pentacene layer is deposited via physical vapor deposition with a rate of 2 /s. In Figure 14 the resulting transistor setup is illustrated. As the devices are sensitive to oxygen and water they have to be measured in an inert atmosphere. Thus, the OFETs are transferred into a nitrogen filled glove box.

Figure 14 Transistor structure of the prepared devices.

4.4. How to characterize the OFETs a. Output and transfer characteristics Measure the output and the transfer characteristics for a HMDS treated and an untreated transistor with a channel length of 20 m. Apply for the output characteristics a constant voltage VG of 0 V / -20 V / -40 V / -60 V and vary VD between 0-60 V. For the transfer characteristics apply a constant voltage VD of 0 V / -20 V / -40 V / -60 V and vary VG between 0-60 V. b. Conditioning Measure the transfer curve (VD = -60 V, VG = 0-60 V) of a HMDS treated and an untreated transistor (curve 1). Condition the transistor by measuring a second transfer characteristic at VD = -60 V and VG = +100-60 V (curve 2). Measure the transfer curve at VD = -60 V and VG = 0-60 V of a HMDS treated and an untreated transistor again (curve 3). 5. Analysis of the measured data: The protocol Introduce the OFET by briefly (!) describing its operation principle. Output and transfer characteristics Plot the output and transfer characteristics for an untreated and an HMDS-treated OFET (four graphs). Mark the linear and the saturation regime for the different output curves. Discuss why the drain currents recorded for the same measurement conditions, i.e. the same set of VD and VG, are different for the untreated and the HMDS-treated transistors. What are the highest measured gate currents IG? Make sure that IG is not in the range of the drain currents ID before you proceed with the data analysis. (1) Charge carrier mobility Calculate the hole mobility of the HMDS treated transistor: a) Use the transfer curve (forward sweep) for VD = -60 V and fit ID1/2 in the saturation regime. b) Use the output characteristics (forward sweeps). Sketch the curves needed for the calculation, show the fitting curves and explain how you calculated the mobility. Discuss why the calculated mobilities differ from each other.
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(2) Conditioning of OFETs Plot the measured transfer curves 1 and 3 of the conditioned untreated and HMDS-treated OFETs. Calculate the respective threshold voltages from the forward sweeps, respectively. Compare the values before and after the conditioning and discuss the difference. What could be the reason for the observed threshold voltage shift? (3) Charge carrier density in the channel a) Calculate the accumulated charge carrier density in the transistor channel due to the fieldeffect for VG = |-60 V| and VG = |-20 V| and discuss the difference. Assume VD to be zero. Which parameters have to be changed to increase the charge carrier density at the same voltage VG in the transistor? Based on these requirements which gate dielectrics can be used in OFETs? Name two possible materials. b) Estimate the intrinsic charge carrier density in pentacene (i) from the off-current of the transfer characteristic measured during the conditioning experiment (curve 1, OFET with untreated SiO2-dielectric) utilizing the equation for a drift current. Assume that the field-effect mobility calculated in (2) also holds in the low carrier density regime. (ii) taking the energy gap of the semiconductor into account. Assume an effective density of states of 1021 cm-3 and a temperature of 300 K. Give an explanation why these values differ. c) Explain how the areal capacitance of a device with a bilayer dielectric (layer 1: d1 and 1 and layer 2: d2 and 2) is calculated. 6. Questions to be answered before (!) the experiment What does HOMO and LUMO mean and how do they develop? Why do organic semiconductors show such low charge carrier mobility compared to inorganic semiconductors? Name and sketch possible transistor structures. Which contact materials are expected to provide a good charge carrier injection? Sketch a typical output and a typical transfer curve of a transistor. What do we learn from the transistor curves? Name the Shockley equations. Why is the threshold voltage introduced? What determines the accumulated charge carrier density in the channel? How is the capacitance C defined? Calculate the areal capacitance for the transistor that will be prepared in the practical course.

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