University of Pannonia

Dept. Of Electrical Engineering and Information Systems

Laboratory 3: VGA controller implementation (solution)

using Xilinx EDK/SDK 10.1 SP3 Instructor: Zsolt Vrshzi, PhD.
Lab1material This Intro exempt per Department of Commerce license exception TSU
2011 Xilinx, Inc. All Rights Reserved

Xilinx Literatures
Xilinx University Program:
http://www.xilinx.com/university/

Xilinx Embedded Development Kit

http://www.xilinx.com/support/documentation/dt_edk.ht m

Xilinx TFT-LCD IP core:

http://www.xilinx.com/support/documentation/ip_docum entation/xps_tft.pdf

VGA controller (background):

Digilent Nexys-2 board Reference Manual http://www.digilentinc.com/Data/Products/NEXYS2/ Nexys2_rm.pdf
12a- 2 Lab1 Intro

MicroBlaze System
Task: Add XPS TFT Controller to your embedded system design (based on Lab 2)
BRAM LMB BRAM Cntlr Instruction MicroBlaze MDM
LEDs

LMB BRAM Cntlr Data UART TFT

VGA interface

GPIO GPIO GPIO PLB Bus EMC CNTLR

PSBs DIP

SRAM Flash

You will add the Xilinx TFT Controller instances and connect them to the VGA connector on the board

XPS TFT Controller

See xps_tft.pdf for details. VGA output ports

(3. DVI interface is included in the design if the parameter C_TFT_INTERFACE = 1.) *4. VGA interface is included in the design if the parameter C_TFT_INTERFACE = 0 is set.

XPS TFT Controller

Features Connects as 64-bit master on PLB V4.6 bus of 64 or 128 bits data width Connects as a 32-bit Slave on the DCR V2.9 bus or PLBV4.6 bus of 32, 64 and 128 bits data width Supports DCR daisy chain protocol (not used in this design) Parameterizable TFT interface for 18-bit VGA (or 24-bit DVI) Supports 25 Mhz TFT clock for display resolution of 640480 pixels at 60 Hz refresh rate Supports configuration of external Chrontel DVI video output chip (not used in this design)
Chrontel Transmitter Chip can be programmed through I2C interface

Supports separate clock (asynchronous) domain for PLB interface and TFT interface

EDK Design Flow

Add a XPS TFT Controller peripheral into the design (based on Lab 2)
Step 1: Copy and open the previous Project (BSB) Step 2: Add and Connect TFT Peripheral to the System Step 3: Configure the TFT Peripheral(s) Step 4: Make External TFT Peripheral Connections Step 5: Analyze the MHS file and generate Bitstream

Step 6: Add Software Application and Compile in SDK

Step 7: Verify the Design in Hardware

Step 1-2-3
Copy all contents of the Lab2 folder into the Lab3. Start XPS/EDK. Open Lab3 project From IP Catalog view add an IO Modules XPS TFT v.1.00.a peripheral

0x90000000

Double click, or mouse right + select Add IP

User Tab all settings are default except for the following Unselect the TFT Interface Base Address of the PLB Attached Video Memory: = 0x90000000 (map to Micron SRAM base address) System Tab Set manually or generate addresses properly Base Address: 0x90000000 16 MB! High Address: 0x9000ffff (Map to the whole Micron SRAM memory capacity)

Step 3

Bus Interface Tab: Rename IP core xps_tft_0 tft_controller Select mb_plb both for MPLB and SPLB ports (OR click on brown circles in bus connections, alternatively) Addresses Tab: Check the address parameters of the tft_controller NOTE: addresses does not overlap to each other and can be generated automatically (also try it!)

Step 3
Double click on the clock_generator_0
In ports view select CLKOUT1 Required frequency (for TFT controller): 25,000,000 Hz Buffered: TRUE Connected to: New Connection
Check SYS_TFT_Clk (clock_generator_0_CLKOUT1 added) Click on Validate Clocks

Note

The 25 MHz DCM clock is connected to the TFT VGA clock (640x480@60Hz)

If CLKOUT1 port of the clock_generator_0 instance is not displayed on the System Assembly View Ports tab then you must refresh the GUI.

Step 3
Make external the selected 6 signals as below: *TFT_VGA_B: 2-bit Blue ch.
*TFT_VGA_G: 3-bit Green ch TFT_VGA_R: 3-bit Red ch
* See Nexys2_rm.pdf for details.

**TFT_DE: Data Enable TFT_VSYNC: Vertical Synchronization TFT_HSYNC: Horizontal Synchronization signal
** See xps_tft.pdf for details.

Step 3 internal signals

Padding 6-bit [5:0] R, G, and B color components with 0s. Remark: R, G are 3-bit wide, while B is 2-bit
Use the concatenation (&) operation with the given number of binary value 0b0

Padded with 0s > 6 bits of R/G/B components (VGA controller output)

Step 4 external ports

Change the range of the TFT_VGA_R / G / and B_pins as follows:

Tie tft_controller_TFT_DE_pin to 1, therefore select net_vcc (it always enables data out):

Step 4 Edit system.ucf

Give some new pin constraints about color channels, and synchronization ports Click on the system.ucf file under the Project tab Copy the #VGA section of the Nexys2_<500/1200>General.ucf provided by Digilent Inc into the system.ucf. Important: Rename pin names according to the source below in order to match with external ports name of the elaborated Embedded System!

### Additional signals for TFT controller NET NET NET NET NET NET NET NET tft_controller_TFT_VGA_R_pin<3> LOC = R9; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0 tft_controller_TFT_VGA_R_pin<4> LOC = T8; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1 tft_controller_TFT_VGA_R_pin<5> LOC = R8; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2 tft_controller_TFT_VGA_G_pin<3> LOC = N8; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0 tft_controller_TFT_VGA_G_pin<4> LOC = P8; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1 tft_controller_TFT_VGA_G_pin<5> LOC = P6; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2 tft_controller_TFT_VGA_B_pin<4> LOC = U5; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1 tft_controller_TFT_VGA_B_pin<5> LOC = U4; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2

NET TFT_VSYNC_pin LOC = U3 | PULLUP; NET TFT_HSYNC_pin LOC = T4 | PULLUP;

Step 5
Run Generate Netlist
Running synthesis process (XST) Elaborating IPs (check all components in MHS file) create HDL wrappers of the embedded BSB Finally generate HW netlist <Project_name>.ngc (e.g. system.ngc file)

Run Generate Bitstream

Implement Design (MAP->PLACE->ROUTE proc).
System.ncd is generated

Generate bitstream file for dowloading it to the FPGA with <Project_name>.bit (e.g. system.bit)

Note: Check Report file (system.par) for resource utilization

Questions
Open the system.mhs file, study its contents, and answer the following questions
Number of external ports: ___________________ Number of external ports that are output (O): ___________________ Number of external ports that are input (I): ___________________ Num. of external ports that are bidirectional (IO): ___________________ Number of clock ports: ___________________ Freq: _________ Number of reset ports: ___________________ Polarity: _________

Questions
List the instances to which the dcm_clk_s is connected: ________________________________________ _____ List the instances connected to the mb_plb bus: ________________________________________ ______ List the instances connected to the clock_generator_0_CLKOUT1 bus: ________________________________________

Questions
Draw the address map of the system, providing instance names:

Questions

Check Report files (system.par) or log messages in Consol window after the placement process step):
_____ out of _____ out of _____ out of _____ out of 250 _____ _____ _____ 17,344 17,344 8,672 22% 11% 19% 29%

Logic Utilization: Number of Slice Flip Flops: Number of 4 input LUTs: Logic Distribution: Number of occupied Slis: Number of External IOBs Number of External Input IOBs Number of External Output IOBs Number of External Bidir IOBs

Number Number Number Number Number Number Number

of of of of of of of

BSCANs _____ out of 1 100% BUFGMUXs _____ out of 24 8% DCMs _____ out of 8 12% MULT18X18SIOs _____ out of 28 RAMB16s _____ out of 28 71% Slices _____ out of 8672 29% SLICEMs _____ out of 4336 6%

10%

Xilinx SDK 10.1

SDK 10.1 Step 1.)

Run Xilinx Platform Studio EDK Select workplace / XPS Project directory (under LAB 3)

Select Application Wizard

Create a new SDK Application project

Add project name

Add project name: VGATest and processor instance microBlaze_0

Add project type

Project type: Xilinx MicroBlaze Executable Configurations: Debug / Release / Profile

VGATest main.c
Simple VGATest main.c application created Note: Automatic build is set by default (if you want to change: Project Build Automatically is not checked) SW platform will be created (generated from .MSS file)

SW platform
microblaze_0_sw_platform (right click -> generate Libraries and BSP or LIBGen icon) Archives: .a (binary) Microblaze_0
Code Include*
See xparameters.h (generated from .MHS)

Lib LibSrc

DipTest SW application
VGATest {microblaze_0_sw_platform} Binaries (.elf) Debug (.elf) main.c Additional headers and sources

GPIO drivers and applications

C:\Xilinx\10.1\EDK\sw\XilinxProcessorIPLib\drive rs\
tft_v1_00_a: TFT LCD v1.00.a driver functions (lowand high-level driver functions [cpp, h])
/Build: OS dependent Makefiles /Data:.tcl + .mdd (driver descriptors) /Doc: API in html form (see index.html) /Examples: simple example applications (use drivers)
e.g. xtft_example.c functions

/Src: sources of low-, and higher-level drivers

xtft.h, .c

gpio_header.h
Declares XTft_DrawSolidBox () function for prototyping Declares TftExample () function for prototyping Dependencies:
#include #include #include #include #include #include <stdio.h> <xio.h> "xbasic_types.h" "xstatus.h" "xparameters.h" "xtft.h" See driver\example\xtft_example.c for further details!

Step 2.) Generate Linker Script

If necessary, set all sections of the .elf file into the internal BRAM memory
Select [ilmb_cntlr_dlmb_cntlr] -> Generate

SDK: Custom program segments (compile sw application)

.text the executable code .rodata any read-only data used in the execution of the code .data where read-write variables and pointers are stored .bss a part of the data segment containing statically-allocated variables .heap where dynamically allocated memory is located .stack where function-CALL parameters and other temporary data is stored

Step 3.) Build SW application

After building the VGATest software application the size of the generated, downloadable VGATest.elf file as follows:
************** Determining Size of ELF File ************** mb-size VGATest.elf text data bss 9694 1472 1104

dec 12270

hexfilename 2feeVGATest.elf

Build complete for project VGATest OK. It is (12 270 bytes of total program code) fitted to the 32KByte BRAM internal memory.

Step 4. Terminal Program

Set the following parameters properly (see the parameters of xps_uartlite in the .mhs file!)
Com port: COMX Baud Rate: 9600 Data Bits: 8 Stop Bits: 1 Parity Bit: None Flow control: none

Step 5. Method a.) Programming the FPGA via Xilinx Impact

Select Device Configuration menu -> Bitstream settings
Select compiled DipTest.elf file for running MicroBlaze sw codes

Connect the Xilinx JTAG-Platform USB cable to Nexys-2 boards JTAG interface Select Device Configuration menu -> Program FPGA
Bitstream (system.bit) BRAM Memory Map (.bmm) + VGATest.elf -> D:\FPGA\BEAGYAZOTT_RENDSZEREK\10_1\03_LAB\SDK\ SDK_projects\implementation\download_sdk.bit

Step 5. Method b.) Programming the FPGA via Digilent Adept

Instead of using the Xilinx iMpact, we use Digilent Adept Suite! programmer provided by DigilentInc (vendor of the FPGA board). Browse your SDK_project\implementation\ directory for download_sdk.bit bitstream file. Use and set properly the terminal program (e.g. Windows Hyperterminal, Teraterm Pro, or Putty etc.) At the final step Program the FPGA! At now the Lab 3 is completed in SDK 10.1 SP3

Question
What is the size of .elf program, and the different
program sections? Which is the base_address and high_address (or address size) of the push button TFT_LCD peripheral? Which header .h file contains the MicroBlaze system parameters for various peripherals?

Lab2 Intro
2011 Xilinx, Inc. All Rights Reserved

For Academic Use Only