Journal of ELECTRONIC MATERIALS, Vol. 33, No.

8, 2004

Regular Issue Paper

Germanium-on-Insulator Substrates by Wafer Bonding

CLARENCE J. TRACY,1,4 PETER FEJES,1 N. DAVID THEODORE,1 PAPU MANIAR,2 ERIC JOHNSON,2 ALBERT J. LAMM,3 ANTHONY M. PALER,3 IGOR J. MALIK,3 and PHILIP ONG3
1.Advanced Products Research and Development Laboratory, Motorola Semiconductor Products Sector, Tempe, AZ 85284. 2.Microelectronics and Physical Sciences Laboratory, Motorola Labs, Tempe, AZ 85284. 3.Silicon Genesis Corporation, San Jose, CA 95134. 4.E-mail: c.tracy@motorola.com

Single-crystal Ge-on-insulator (GOI) substrates, made by bonding a hydrogenimplanted Ge substrate to a thermally oxidized, silicon handle wafer, are studied for properties relevant to device fabrication. The stages of the layer transfer process are examined through transmission electron microscopy (TEM) from the initial hydrogen implant through the nal Ge lm polish. The completed GOI substrate is characterized for lm uniformity, surface quality, contamination, stress, defectivity, and thermal robustness using a variety of techniques and found to be acceptable for initial device processing. Key words: GOI, wafer bonding, Ge substrate

INTRODUCTION The degradation in performance of silicon metaloxide semiconductor (MOS) devices with scaling caused by fundamental material limitations is forcing the semiconductor industry to consider extraordinary measures. Changes in structure (various forms of double-gated devices), alteration of material properties in the channel region (SiGe alloys or strained silicon), and replacement of silicon altogether (digital GaAs based on a new GaAs gate dielectric) are all being considered. In view of the challenges of introducing any of the preceding technologies into full manufacturing, other options that reuse much of the silicon infrastructure and processing knowledge are attractive. Pure Ge is one such possibility. The availability of good quality, bulk Ge wafers as large as 200 mm, driven by the solar cell industry for space applications, combined with signicantly larger mobilities for both electrons and holes when compared to silicon are two immediate positives. Junctions are easily formed by implanting and annealing the usual elements (B, P, As, etc.) with solid solubilities that are reasonable. Germanides made with familiar materials readily form to enable contact metallization. However, Ge suffers from a potentially fatal aw increased leakage because of the lower bandgap
(Received December 9, 2003; accepted April 20, 2004) 886

which now appears possible to overcome in part through the use of Ge-on-insulator (GOI) substrates that up to now have not been commonly available. Relaxed silicon-GOI substrates with Ge percentages as high as 25% have been demonstrated and are intended to be used for heteroepitaxial growth of device material layers.1 Germanium layers have been transferred directly onto silicon using the hydrogen-induced splitting process for photovoltaic applications.2 The Ge p-channel, MOS eld-effect transistors (FETs) have been built on GOI substrates made through a bond and etch-back process, but little characterization is described of the substrate itself and etch-back processes typically are limited to thicker lms.3 The rst industrially manufactured, 150-mmdiameter GOI wafers are now available in limited quantities. It is critical both to understand the details of the process by which they are made and the quality of the end result before attempting to build evaluation devices. The former enables the continuous improvement of these substrates while the latter is a requirement before inserting this material into a wafer processing line. In this paper, we report on both aspects. GOI WAFER PROCESSING The basic process steps46 from Silicon Genesis patented technology (San Jose, CA) for fabricating

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Fig. 1. Schematic process ow for layer transfer formation of GOI materials.

150-mm-diameter GOI substrates are illustrated schematically in Fig. 1. These steps are (1) formation of a strained-layer cleave plane by hydrogen implantation; (2) thermal oxidation of a handle silicon wafer to form the buried oxide (BOX) layer; (3) plasma-activated bonding of the Ge donor and Si handle wafers;7,8 (4) room-temperature separation of the wafers within the cleave plane, leaving the Ge device layer attached to the BOX/handle wafer; and (5) optional postcleave processing to thin the Ge layer, reduce surface roughness, and remove ionimplant recoil damage. The transmission electron microscopy (TEM) micrographs in Fig. 2 show the Ge substrate at various stages of this fabrication process. The Ge donor wafer is implanted with hydrogen ions of a prescribed energy to reach a specic depth to establish the cleaving plane and thickness of the transferred lm (Fig. 2a). After an appropriate clean,9,10 the Ge is then plasma-activated and bonded to the oxidized silicon handle as an initial step in the low-temperature bonding process. The bonded pair then receives a low-temperature bond treatment to optimize the bond strength. Finally, the Ge wafer is mechanically separated at room temperature from the oxidized silicon handle as the thin Ge layer is transferred. This controlled cleaving is a low stress-layer transfer process that

proceeds from a separation initiation at the edge groove of the bonded wafer pair. This initiation causes a transverse cleave propagation that moves quickly through the engineered cleave plane in a controlled manner.4 The resulting surface of the ascleaved, transferred Ge lm exhibits a signicant roughness on the order of 200 root mean square (RMS). Some residual damage from the implant is still visible (Fig. 2c). The process can include an additional step, such as chemical-mechanical polishing (CMP), to reduce surface roughness, remove the implant damage, and thin the Ge layer to the desired thickness (Fig. 2c and d). Polishing of these GOI samples after cleaving was done through a Ge wafer supplier.11 The cross-sectional transmission electron microscopy (XTEM) results show microstructural changes in the Ge as it is implanted, bonded, cleaved, and CMP smooth-polished. In the asimplanted Ge, a band of implant damage is visible. As-implanted ions penetrate the Ge and implant cascades form, resulting in the presence of interstitials and vacancies in the material. During the implantation process, these point defects can diffuse and then coalesce to form point-defect clusters. Strain around the clusters results in localized contrast in the TEM micrographs. A band of such clusters results in the implant damage band seen in Fig. 2a. Upon exposure to thermal treatment, the pointdefect clusters can grow as seen by the general coarsening of features in the damage region and a roughening near the top of the implant region (Fig. 2b). The defects tend to cluster together in a tight band at the approximate depth and location of the band of point-defect clusters that were seen in the as-implanted sample (Fig. 2a). Occasionally, a dislocation threads upward toward the surface of the wafer. However, the density of such defects is reduced toward the surface of the wafer. Following this step, the wafer is cleaved using the compressivestress implant layer as a guiding plane controlling the fracture propagation. In Fig. 2c, we see the microstructure of the Ge-onSiO2 after the donor wafer has been cleaved off.

Fig. 2. The XTEM bright-eld images of substrates at various sequential stages in the process of making GOI wafers. The diffraction conditions for these images were close to the 220 Bragg condition. The XTEM of implanted Ge (a) with no thermal treatment, (b) with thermal treatment equivalent to bonding cycle, (c) after bonding to silicon dioxide on silicon and the cleave process, and (d) the XTEM of Ge lm after transfer, cleave, and CMP smoothing.

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Signicant surface roughness is evident. This roughness arises from the fact that the cleavage locations (in the implanted Ge) depend on the Ge material properties and H-induced stress distributions. Occasionally, a threading dislocation is seen in the Ge layer (e.g., Fig. 2c). This is consistent with the occasional presence of such threading dislocations in the Ge above the implant damage seen in the thermally treated Ge (Fig. 2b). After the Ge lm has undergone CMP, the surface roughness has decreased substantially (Fig. 2d). The speckled contrast in the TEM micrograph (Fig. 2d) suggests the presence of point-defect clusters in the implant- and cleave-processed Ge. It is not entirely clear, at this time, whether these defects are intrinsic to the processed Ge or if these arise during TEM specimen preparation. However, Ge etch-rate studies do suggest a likely presence of such defects in the H-implanted and cleaved Ge layers. The following characterization results have largely been done on unannealed samples, whereas it is becoming evident that GOI wafers may benet from a nal high-temperature heat treatment. GOI WAFER CHARACTERIZATION The characteristics of the incoming GOI substrates can be divided into three categories: (1) macroscopic properties, including thickness uniformity, roughness, stress, visual defects, and surface contamination; (2) material defects; and (3) processing robustness. Optical microscope inspection of a recent lot of six wafers was used to look for and measure the density of large defects. Most commonly observed is a small circular feature usually less than 20 m in diameter, as shown in Fig. 3. Closer microscope inspections indicate these are voids where the Ge lm is missing, and based on the color, the full thickness BOX layer is exposed. This is conrmed by scanning electron microscopy (SEM) evaluations and Auger analysis of the surface within the void, which nds only silicon and oxygen signals. Approx-

Table I. Optical Reectometry Ge Film-Thickness Measurements Sample 1 2 3 4 5 6 Mean (nm) 75.6 90.5 93.8 102.6 136.2 159.1 Max (nm) 86.9 97.3 101.8 108.9 142.4 172.2 Min (nm) 57.5 77.9 87.8 91.6 126.5 150.4 Std. Dev. (%) 10.3 5.5 3.4 3.3 2.5 3.3

Fig. 3. Optical micrograph showing typical void defect in GOI substrate.

imately 25 cm2 of each wafer is scanned, and the defects manually counted, which yields a defect density of ranging from 2.2 defects/cm2 to 4 defects/cm2, depending on the wafer. While this is still unacceptable for very large-scale integration manufacturing, it is a dramatic improvement from the 200 void defects/cm2 observed on the rst GOI material lots of a few months ago and does not prevent proceeding with device feasibility development. The Ge lm thickness and thickness uniformity data in Table I were measured using spectroscopic reectometry on a commercially available tool mapping 46 points/wafer. The targeted thicknesses were intentionally varied over the lot, resulting in mean values for the thickest sample at 159 nm and the thinnest at 76 nm. The thickness range for any given wafer is on the order of 20 nm and so becomes an increasingly signicant percentage variation for the thinnest samples. This thickness control and variation is sufcient for some devices and applications but will need improvement for others (e.g., fully depleted MOSFETs) where the Ge lm will need to be a few tens of nanometers. Atomic force microscopy (AFM) was used to evaluate the roughness of the GOI surface in comparison to the bulk Ge epi-ready substrates that are commercially available. Figure 4 compares AFMgenerated images and lists both the Rq (RMS) and Zr (range) values for bulk Ge and GOI substrates of two different Ge-lm thicknesses. The surface roughness of all three samples is similar with Rq and Zr values of 0.25 nm and 7 nm, respectively. For comparison, a silicon wafer measured under the same conditions has Rq and Zr values of 0.07 nm and 0.67 nm, respectively, and is signicantly smoother than any of the Ge material. A second point to note is that the thicker GOI sample shows a signicant density of pit-like defects and a correspondingly slightly larger Zr. The density of this type of defect, as determined by examining AFM images for six wafers with Ge thicknesses greater than 150 nm, is estimated to be 2 107/cm2, whereas none of this type of defect were seen on images of ve wafers with Ge thicknesses of approximately 100 nm or less. Examination of XTEM images of unpolished GOI specimens, focusing on defects that could come to within 100 nm of the surface of the implanted sample, yields an estimated defect

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Fig. 4. The AFM images (5 m 5 m scan area) of (a) a bulk Ge wafer, (b) a GOI wafer with 158-nm Ge thickness, and (c) a GOI wafer with 76-nm Ge thickness.

density in the 1 1071 108/cm2 range. The defects do not appear to be threading dislocations; rather, they appear to be platelets on inclined {111} planes. This means that the defect density would vary quite sharply as we thin the sample down to 100 nm, 90 nm, or 80 nm (substantially lower defects) as opposed to 110 nm, 150 nm, etc. (higher defects). Thus, it is believed that the AFM detected pits are related to these platelets, emphasizing the need to remove enough Ge during the smoothing process to remove the defects created by the specic hydrogen-implant conditions used on these samples. Raman spectroscopy was performed on two GOI samples and compared to a bulk Ge wafer with the same doping (Sb, approximately 2 1017 cm3 ) as a reference to measure lm stress and give an indication of crystallinity. The frequency and full-width at half-maximum (FWHM) are listed in Table II for the Raman peak around 300 cm1 corresponding to the longitudinal optical phonon in Ge. The bulk reference sample has a peak frequency corresponding to unstrained Ge and a peak width reecting good crystallinity. The two GOI lms show no signicant
Table II. Raman Peak Frequency and FWHM for Ge Bulk and GOI Samples Phonon Frequency (cm1) 299.73 299.60 299.74 Peak FWHM (cm1) 2.95 0.05 3.02 0.05 3.06 0.05

Samples Ge (bulk reference wafer) GOI sample 1 GOI sample 2

frequency shift and, therefore, are almost stress free (20 MPa either tensile or compressive), but the slight consistent increase in the Raman peak width suggests that the crystallinity is poorer than the bulk sample. To conrm the low stress levels present in the Ge lm, x-ray triple-axis diffraction (004) 2- scans were used to determine the lattice constant in absolute units. At room temperature, the vertical lattice constant c of Ge in GOI is measured as 0.5657 nm, which is in good agreement with the literature value of 0.5658 nm for bulk Ge. Total reection x-ray uorescence (TXRF) analysis to measure metal contamination on the surface of a single, 150-mm-diameter polished GOI wafer was performed in the typical manner,12 examining 10-mm-diameter areas at three locations along a radius line, and the results are reported in Table III. High levels of Ca and Zn are observed in spectra from all locations of the wafer, whereas Cr, Fe, Ni, and Cu are observed at lower levels in some locations. In addition to the data in Table III, a Si signal is observed, but initially, it was not clear whether this signal is due to contamination from some Si-containing component of the polishing compound or if it is due to the exposed silicon oxide at the bonding interface in a few small void defects. A TXRF analysis done on a bulk Ge wafer processed through the same polishing process again revealed high levels of Si, indicating that at least some of this contamination is likely due to the CMP module. The 2003 International Technology Roadmap for Semiconductors13 sets surface metallic contamination limits for future starting substrates

Table III. The TXRF Results at Three Sites on a GOI Wafer* Site
1 2 3 S 700 50 1,020 70 370 30 Cl 185 17 140 15 70 12 K 10 11 11 Ca 670 40 1,300 80 1,440 90 Ti 4 4 4 Cr 8.3 1.3 7.7 1.3 5 1.2 Mn 1.9 2 2 Fe 2.5 1.2 1.8 4.7 1.5 Ni 3.5 1.5 42 1.7 Cu 8.5 2 4 1.8 7.7 2 Zn 230 14 270 16 230 14 Ar 55 9 53 9 34 8

*Units of 1010 atoms/cm2.

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at 1 1010 atoms cm2, somewhat below the measured levels. However, at this stage of development, the actual impact of specic contaminants on the yield of Ge MOS devices is not known. A second consideration is meeting the cross-contamination protocol limits of a silicon pilot line where shared development of Ge technology is to be done. None of the observed contamination levels are sufciently alarming to prevent processing of these substrates in a pilot line, but they do point out the need for reducing metal contamination at the CMP vendor and development of appropriate clean sequences for Ge surfaces. Material defects in the GOI lm are studied using two methods. First, etch rates of the lm are used as an uncalibrated indication of the damage level with the assumption that such will enhance the etch rate. Second, plan-view TEM images in addition to the cross section described earlier provide increased sensitivity to lower defect densities because of the greater sample area. As discussed later, both methods indicate degraded crystalline quality as was also suggested by the increased Raman peak width. Etch-rate studies in room temperature (2025C) 1:10 H2O2:H2O comparing bulk single-crystal Ge wafers, sputtered polycrystalline Ge lms, and GOI substrates showed surprising differences. Whereas both bulk and polycrystalline Ge etched at rates between 20 nm/min and 30 nm/min, GOI material etched at rates between 100 nm/min and 129 nm/min. The AFM measurements of the Rq (RMS) roughness of the bulk single-crystal wafer after 10 min of etching showed no change, but with just 30 sec of etching, the Rq for the GOI sample more than doubled. These results indicate that the Ge lm of the GOI substrate is signicantly damaged during the manufacturing process. Plan-view TEM samples were prepared of the Ge lm on a GOI sample after CMP. After mechanically polishing the piece of wafer from the backside to remove the bulk of the substrate, the remaining material was thinned to electron transparency by focused ion-beam thinning. We estimate that we are viewing approximately the top 100 nm of the Ge lm. Figure 5 shows three types of defects that are observed. First, there are small dislocation loops with diameters 200 nm. Most of these loops are circular, with a few having irregular shapes. There is no variation of contrast with depth that is normally seen with inclined dislocations; so these loops are assumed to be roughly parallel with the (001) plane of the wafer surface. These defects are observed at a density of approximately 4 107 cm2. Because of the regularity of these residual defects, it is thought that what is being observed may be strain around the defect edges in the Ge lm. The second type of defect observed is seen as sections of dislocation loops inclined to the (001) plane of the wafer surface. These dislocation loops are generally much larger than 200 nm and are

Fig. 5. Plan-view bright-eld TEM image with the 220 Bragg condition satised of the Ge lm showing the three types of defects found in this lm. A: small round loops in the (001) plane of the wafer surface. These are assumed to be hydrogen platelets. B: Dislocation loops at an angle to the (001) plane of the wafer surface. C: Surface features, probably pits in the Ge surface.

probably the same dislocations that have been identied in XTEM as threading dislocation loops. Their density is measured as 3 107 cm2. The third type of defect observed in the plan-view TEM sample consists of patches that may appear either dark or light in the bright-eld images. They have diameters 300 nm and exhibit no strain eld associated with them. They are most likely surface features, possibly pits in the Ge surface, as have been detected by AFM and that will appear either dark or bright, depending on the exact diffracting conditions. Finally, the thermal robustness of the GOI material, an essential question before attempting device processing, was examined. Activation studies for phosphorus implanted into Ge show that anneal temperatures in excess of 600C may be required.14 The low melting temperature of Ge (937C) and the signicant difference between the linear coefcients of thermal expansion at 300 K for Ge (5.8 106 C1) and silicon (2.6 106 C1), therefore, raise concerns.15 The previously discussed Raman data conrms that, at room temperature, the Ge is not strained, but upon heating, it will go into compressive stress, and at high enough temperatures, it is expected to relax by creating material defects. Then, upon cooling, it will go into tensile strain and potentially additional defects may be created. To initially examine this issue, small specimens cut from a GOI wafer were annealed on a hot stage in high vacuum at set point temperatures of 725C, 815C, and 960C for about 1 h followed by optical, AFM, and SEM inspections as appropriate. Actual sample temperatures are believed to be 1525C lower than

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sults conrm that the thermal processing concerns are real but only if temperatures approach 800C or higher. CONCLUSIONS The 150-mm GOI substrates consisting of about a 100-nm Ge lm on a thermally oxidized, silicon handle wafer are now commercially available in small quantities and with sufcient quality to allow device development studies to begin. Analysis of various properties as-received and following high-temperature processing cycles indicate that these substrates do not pose a risk to a modern pilot line beyond that associated with the processing of the Ge material itself. Surface smoothness and metal contamination are acceptable for building devices to enable understanding the technical and business value of using Ge for some future applications. However, there are several issues that must be addressed if these wafers are to be ultimately used in manufacturing. Macroscopic defect densities are high, and Raman, TEM, and etch-rate data indicate that crystalline quality of the Ge lm is degraded. Surface contamination with some metals is higher than considered acceptable for silicon substrates, and the unusual presence of silicon contamination on the Ge surface may be important for certain processes. Additionally, the variation in Ge lm thickness across the substrate after the polishing process is too great to allow the ultrathin layers essential for some of the more interesting future devices. Finally, these problems have to be solved not only for 150-mm wafers but also for 200-mm and 300-mm wafers. On a positive note, none of these issues appear to be a showstopper and reuse of the knowledge learned in building standard silicon-on-insulator substrates should accelerate progress.

Fig. 6. Plan-view TEM of the GOI wafer annealed at 725C for 1 h. A bright-eld image with the 220 Bragg condition satised. No defects were seen. The dark bands visible in the micrograph are bend contours and thickness fringes.

the set point and further calibrations are in progress. Figure 6 presents a plan-view TEM micrograph obtained from a GOI wafer annealed at 725C for 1 h. No extended defects were observed. Figure 7 shows AFM images for the 815C annealed sample and the unannealed control and clearly indicates the appearance of defects. The well-dened surface steps are believed to be due to slip within the Ge crystal because with temperature both the material ductility and the mechanical stress induced by the constraining silicon substrate increase. The results appear similar to those described in the literature for bulk Ge substrates.16 No change was observed for the 725C annealed sample, whereas drastic changes in the lm were apparent in the optical microscope inspection of the 960C sample. The re-

Fig. 7. The AFM images (5 m 5 m scan area) of the GOI surface: (a) not annealed and (b) annealed at 815C.

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ACKNOWLEDGEMENTS The authors acknowledge the support of the Motorola Microelectronics and Physical Sciences Process and Characterization Laboratories and the Motorola APRDL Physical Analysis Laboratory (Tempe, AZ). Special thanks go to Diana Convey for the AFM analysis and Dr. Ran Liu for the Raman spectroscopy studies. REFERENCES
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