Code No: R5220404 1

II B.Tech. II Semester(R05) Supplementary Examinations, April/May 2009

SWITCHING THEORY AND LOGIC DESIGN
(Electronics & Communication Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE questions
All questions carry equal marks
?????

1. (a) Perform the following additions using the 2’s complement method:
i. 1101+1110.
ii. +63 and +37.
(b) Generate Hamming code for the given 11-bit message 10001110101 and rewrite the entire
message with Hamming code.
(c) What is a Gray code? Why is it important?
2. (a) Simplify the following Boolean expressions:
i. ABC + AB + BC.
ii. A[B + C(AB + AC)].
(b) Derive the complements of the expressions given below.
i. AB(C̄D + B̄C)
ii. (A+B)(B+C)(A+C)
3. Using the Quine-Mc Cluskey method of tabular reduction, minimize the given combinational
single output function. f (w, x, y, z) = Σm (0, 1, 5, 7, 8, 10, 14, 15).
4. (a) Design a 32-to-1 MUX using 8-to-1 multiplexers.
(b) How does a priority encoder differ from ordinary encoder.
(c) What is a parity bit? Design a parity generator circuit to add odd parity bit to a 7-bit
word.
5. (a) How does the architecture of PLA differ from ROM and PAL.
(b) Tabulate the PLA programming table for the four Boolean functions listed below and
minimize the no. of product terms.
A(x, y, z) = Σ(1, 2, 4, 6), B(x, y, z) = Σ(0, 1, 6, 7), C(x, y, z) = Σ(2, 6), D(x, y, z) = Σ(1, 2, 3, 5, 7).
6. (a) Explain the steps involved in the design of synchronous sequential circuits.
(b) Design a serial binary adder using D-Flip Flop.
7. For the machine shown in the table below obtain
(a) The corresponding reduced machine table in standard form.
(b) Find a minimum length that distinguishes state A from state B.
PS x=0 NS,Z
x=1
A B,1 H,1
B F,1 D,1
C D,0 E,1
D C,0 F,1
E D,1 C,1
F C,1 C,1
G C,1 D,1
H C,0 A,1
8. Construct an ASM block that has 3 input variables (A,B,C), 4 output (W,X,Y,Z) and 2 exit
paths. For this block, output Z is always 1, and W is 1 if A & B are both 1. If C=1 & A=0,
Y=1 and exit path 1 is taken. If C=0 or A=1, X=1 and exit path 2 is taken. Realize the above
using one Flip Flop per state.

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Code No: R5220404 2
II B.Tech. II Semester(R05) Supplementary Examinations, April/May 2009
SWITCHING THEORY AND LOGIC DESIGN
(Electronics & Communication Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE questions
All questions carry equal marks
?????

1. (a) The state of a 12-bit register is 010110010111. What are its contents if it represents?
i. Three decimal digits in BCD.
ii. Three decimal digits in Express-3 code.
iii. Three decimal digits in 2421 code.
(b) Convert the following hexadecimal number to octal, decimal and binary.
i. F3A7C2.
ii. 2AC5.
2. (a) i. Given AB + ĀB = C, Show that ĀC + ĀC = B.
ii. Simplify (A + B)(Ā + C)(B̄ + D)(C + D̄).
(b) Express B̄C + B̄D + ĀC + AD̄ in its minimum sum of products and minimum product of
sums.
3. (a) For the given function f (A, B, C, D) = ΠM (1, 2, 3, 8, 9, 10, 11, 14) + Σd (7, 15), obtain min-
imal SOP function using K-map.
(b) Determine Canonical POS form for the function T (x, y, z) = x(y 0 + z).
4. (a) Design 64 line output demultiplexer using lower order demultiplexer such as 4 to 16 and
2 to 4 demux.
(b) Realize a 3-bit odd-parity generator circuit using only 2-input EX-OR gates.
5. (a) Design a BCD to excess-3 code converter using:
i. ROM.
ii. PAL.
(b) Show how a 4 x 16 decoder can be constructed with two 3 x 8 decoders.
6. (a) Draw the circuit diagram of J-K Flip-Flop with NAND gates with positive edge triggering
and explain its operation with the help of truth table: How race around condition is
eliminated?
(b) Realize D-latch using R-S latch. How it is different from D-FF? Draw the circuit using
NAND gates & explain.
7. (a) Distinguish between Melay and Moore Machines.
(b) Find the equivalence partition and a corresponding reduced machine in standard form.
PS x=0 NS,Z
x=1
A B,0 E,0
B E,0 D,0
C D,1 A,0
D C,1 E,0
E B,0 D,0
F C,1 C,1
G C,1 D,1
H C,0 A,1
8. Draw the ASM chart of binary multiplier and design the control circuit using each of the
following methods.
(a) JK Flip Flop and gates.
(b) D Flip Flop & decoder.

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Code No: R5220404 3
II B.Tech. II Semester(R05) Supplementary Examinations, April/May 2009
SWITCHING THEORY AND LOGIC DESIGN
(Electronics & Communication Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE questions
All questions carry equal marks
?????

1. (a) Write a short note on weighted and nonweighted codes.

(b) Subtract the following numbers using 2’s complement method: +62-(+29).
(c) Express the following decimals in Gray code and Excess-3 code form
i. 457.
ii. 3421.
2. (a) Simplify the following Boolean expression:
i. AB̄ + ABC + A(B + AB̄)
ii. (A + B)(ĀC̄ + C)(B̄ + AC)
(b) Draw a logic circuit for the following function using NOR gates. (A+B)(B+C)(A+C).
(c) What is meant by duality in Boolean Algebra.
3. (a) Obtain minimal SOP expression for the following function and implement the same using
NAND gates. f (A, B, C, D) = Σ(0, 2, 3, 5, 7, 8, 13) + Σd (1, 6, 12)
(b) Explain the concepts of mixed logic with necessary diagrams.
4. (a) Design the logic diagram of a circuit for addition/subtraction. Use control variable w and a
circuit that functions as a full adder when w=0 and as a full-subtractor when w=1.
(b) What is meant by a decoder? Explain it with a block diagram. Draw the logic diagram of
2-to-4 decoder with an ENABLE input using NAND gates.
5. (a) Explain the difference between the performance of asynchronous and synchronous counters.
(b) Design a 4-bit binary synchronous counter with D-Flip Flops.
(c) What is meant by edge triggering? What is the difference in the operation of edge triggered
and master-slave Flip Flops.
6. (a) What is a shift register? Explain the working of serial in-serial out shift register with logic
diagram and wave forms.
(b) Design a sequence generator to generate the sequence 111101.
7. (a) Compare fundamental and pulse mode asynchronous sequential circuits.
(b) Minimize the following incompletely specified machine.
PS x=0 NS,Z
x=1
q1 d,0 q2 , 0
q2 q1 ,1 d,d
q3 q6 ,d q1 ,1
q4 d,1 q5 ,1
q5 q3 ,0 q4 ,d
q6 q4 ,d q3 ,1
8. (a) Design a digital system with three 4-bit register A,B and C to perform the following opera-
tions by ASM chart.
i. Transfer two binary numbers to A and B when start signal is enabled.
ii. If A < B, Shift left the contents of A and transfer result to C.
iii. If A > B, Shift right the contents of A & transfer result to C.
iv. If A = B, transfer the number to register C unchanged.
(b) Realize the above using JK Flip Flops.

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Code No: R5220404 4
II B.Tech. II Semester(R05) Supplementary Examinations, April/May 2009
SWITCHING THEORY AND LOGIC DESIGN
(Electronics & Communication Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE questions
All questions carry equal marks
?????

1. (a) Find the Gray code equivalent of Octal number 527.

(b) The message below has been coded in the 7-bit Hamming code and transmitted through
noisy channel. Decode the message assuming that at most a single error has occurred in
each code word, 1001001, 0111001, 1110110, 0011011.
(c) Explain the rules for binary subtraction using the 1’s and 2’s complement methods.
2. (a) Express the function Y = A + B̄C in
i. Canonical SOP and
ii. Canonical POS form.
(b) If ĀB + C D̄ = 0, then prove that AB + C̄(Ā + D̄)=AB + BD + BD + ĀC̄ D̄.
(c) What are universal gates? Why they are so called?
3. (a) For the given function
F(A,B,C,D,E)=Σ(0,1,2,3,4,5,9,10,16,17,18,19,20,22,25,26)+ Σd (7,11,12,13,15,23,27,28,29,30)
(b) Prove that Y=AB+BC+AC is a self dual function.
4. (a) Give the implementation of a 4-bit ripple Carry adder using half-adder(s)/full- adder(s).
(b) Explain with an example, the MUX and DEMUX can be used on data-selector and data-
distributor respectively.
5. (a) Implement the following function using PLA f(a,b,c,d)=Σm (0,1,6,8,9)
(b) Define the following terms in connection with a FF
i. Set up time.
ii. Hold time.
iii. Propagation delay time.
(c) Explain how the J-K Flip Flop can be converted as a toggle Flip Flop.
6. (a) Design a JK Flip Flop asynchronous sequential circuit with two inputs x1 and x2 and single
output Z. The output Z=1, if and only if the same input variable changes two or more times
consecutively.
(b) Describe incompletely specified state machine.
7. (a) Convert the following Melay machine into a corresponding Moore machine.
PS x=0 NS,Z
x=1
A C,0 B,0
B A,1 D,0
C B,1 A,1
D D,1 C,0
(b) Design the circuit for the above table.
8. (a) Draw the state diagram and state table of the control unit conditions given below. Draw the
equivalent unit conditions given below. Draw the equivalent ASM chart leaving the state
box empty.
i. from 00 state, if x=1, it goes to 01 state and if x=0, it remains in the same state 00.
ii. from 01 state, if y=1, it goes to 11 state and if y=0, it goes to 10 state.
iii. from 10 state, if x=1 and y=0, it remains in the same state 10 and if x=1 and y=1, it
goes to 11 state, and if x=0, it goes to 00 state.
iv. from 11 state, if x=1, y=1, it remains in the same state, and if x=0, it goes to 00 state.
(b) Design the control with multiplexers for the above problem.

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