Phase Lock Loop (PLL), Op-Amp, Ch-13 in Bio-Medical Engineering

2013
*,ANALOG- PHASE-LOCKEDLOOP [A-PLL+ ON OPERATIONAL-AMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

[My Notes on CH-13[OP-AMP]-> PHASELOCKED-LOOP[PLL] OR ANALOG-PHASELOCKED-LOOP[A-PLL]]
PHASE-LOCKED-LOOP = DIGITAL-PHASE-LOCKED-LOOP[D-PLL] + ANALOG-PHASELOCKED-LOOP[A-PLL] , its an important course for bio-medical instrumentations , MY BLOG ON BIO-MEDICAL ENGINEERING COURSES IS HERE --> www.medicalimage-processing.blogspot.com , Operational-Amplifiers Text Book--> Fundamentals-Of-Operational-Amplifiers And Linear Integrated Circuits By Howard M. Berlin And Frank C. Getz, Jr. MAXWELL MACMILLAN , INTERNATIONAL EDITIONS .
MUHAMMAD-SIKANDAR-KHAN-LODHI BIO-MEDICAL ENGINEERING GUIDE.INC 6/15/2013
[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

Table of Contents
PHASE-LOCKED-LOOP[PLL] OR ANALOG-PHASE-LOCKED-LOOP[A-PLL]:- ........................................... 4 INTRODUCTION: ........................................................................................................................................ 4 13-1 ) THE BASIC PRINCIPAL OF PLL: ........................................................................................................ 5 VOLTAGE-CONTROLLED-OSCILLATOR [VCO] : ................................................................................. 6 THE LOOP-FILTER=LOW-PASS-FILTER[LPF]: ......................................................................................... 7 BASIC-OPERATION-OF-PHASE-LOCKED-LOOP [PLL]:........................................................................ 9
[13-2 + THE FREQUENCY-SYNTHESIZER OR FREQUENCY-MULTIPLIERS: ............................................. 12 ANALOG-PHASE-LOCKED-LOOP [ A-PLL ] { 560-SERIES ] :[NEW-TOPIC]: ...................................... 14 FM-DEMODULATOR-USING-A-560B [ PLL-IC ] :- ............................................................................ 16 561B PHASE-LOCKED-LOOP OR AM-RECIVER OR FM-DE-MODULATOR :- ................................... 16 AM-RECEIVER [OR AM-DETECTOR ] WITH 561B[A-PLL]:- .......................................................... 17 AM-RECEIVER [ WITH 561B [PLL-IC]:- ............................................................................................ 17
562 PHASE-LOCKED-LOOP[PLL] AS A FREQUENCY-MULTIPLIER/OR FREQUENCY-SYNTHESIZER:- .. 19 FREQUENCY-MULTIPLIER [OR SYNTHESIZER ] :- ............................................................................ 19 NTH MODULE-COUNTER :- ............................................................................................................ 20
565-PHASE-LOCKED-LOOP(PLL) [ FSK-DEMODULATOR/FSK-DECODER ]:-.............................................. 21 Fig # 17 : .............................................................................................................................................. 22 FIG # 18 ............................................................................................................................................... 23 Fig # 19 ................................................................................................................................................ 24 APPLICATION-OF-565 (PLL):- ....................................................................................................................... 26 FIG # 20 : ............................................................................................................................................. 26 Fig # 13-15 or Fig # 21 ........................................................................................................................ 28 567-TONE-DECODER:- { AN APPLICATION OF 567 PLL }:- ....................................................................... 28 Fig # 22 ................................................................................................................................................ 29 567 BAND WIDTH VERSUS INPUT SIGNAL [ Vi ] AMPLITUDE CURVE FOR THE SELECTION-OFCAPACITOR-C2 :-................................................................................................................................... 30 Fig # 23 ................................................................................................................................................ 30 BASIC-TONE DECODER-CIRCUIT:-............................................................................................................ 31 Fig # 25 ................................................................................................................................................ 34
[www.medical-image-processing.blogspot.com
by Sikandar Khan Lodhi]
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AN-APPLICATION-FOR-THE-567-PLL:- ..................................................................................................... 35 Table 13-2 ........................................................................................................................................... 35 Fig # 26 ................................................................................................................................................ 36 Fig # 27 ................................................................................................................................................ 37 4046-CMOS-PHASE-LOCKED-LOOP [ CMOS-PLL ] :- .................................................................................... 38 Fig # 28 : ............................................................................................................................................ 39 APPLICATION-OF-4046 PLL [ CMOS PLL] :- ............................................................................................. 40 EXAMPLE-OF-CMOS ( 4046 PLL ) BASED FREQUENCY MULTIPLIER (OR SYNTHESIZER) WHICH MULTIPLY INPUT (I/P) FREQUENCY BY 10n-FACTOR [ ]:- ............................................................ 42 BASIC-OF-PHASE-LOCKED-LOOP (PLL) OR BASIC PRINCIPLE OF PHASE-LOCKED-LOOP (PLL) :- ................. 43 APPLICATION:- ........................................................................................................................................ 43 BASIC-PLL CONCEPT :- ............................................................................................................................. 43 Fig # 32 [ Basic-Phase-Locked-Loop PLL ]:........................................................................................... 45 Fig # 33 [ Phase-detector ] :- ............................................................................................................... 45 Fig # 34 [ Phase-Detector ] . ................................................................................................................ 46 Fig # 35 [ Phase-Detector ] .................................................................................................................. 47 Fig # 36 : .............................................................................................................................................. 50 THE-VOLTAGE-CONTROLLED-OSCILLATOR *VCO+ :- ............................................................................... 51 BASIC VCO OPERATION IN PLL-SYSTEM:-.......................................................................................... 52 Fig # 37 ................................................................................................................................................ 52 BASIC-PLL-OPERATION:-.............................................................................................................................. 53 Fig # 38 [ PLL is Locked ]: ..................................................................................................................... 54 Fig # 39 PLL is Un-Locked , (a) circuit Diagram ................................................................................... 55 Fig # 39 PLL is Un-Locked , (b) wave Form ......................................................................................... 56 Fig # 40 [ PLL is Locked ]:-.................................................................................................................... 57 LOCK ( or HOLD-IN ) RANGE :- .................................................................................................................... 57 CAPTURE-RANGE :- ..................................................................................................................................... 58 Fig # 41 [ Frequency Spectrum Graphical Analysis ] .......................................................................... 59 Case-1 :- .................................................................................................................................................. 60 Fig # 42 [ Case-1 ] ................................................................................................................................ 60
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CASE-2 : ................................................................................................................................................... 61 Fig # 43 [ CASE-2 ] :- ............................................................................................................................ 61 THE LM-565 PHASE-LOCKED-LOOP [PLL] :- ............................................................................................. 61 Fig # 44 [ LM-565 PLL ] INTERNAL-CIRCUIT BLOCK DIAGRAM OF LM-565 PLL : ................................. 63
PHASE-LOCKED-LOOP[PLL] OR ANALOG-PHASE-LOCKED-LOOP[A-PLL]:-
INTRODUCTION:
the Phase-locked-loop is now a very sophisticated electronic network, which will used for such following applications, 1. 2. 3. 4. 5. 6. 7. Motor-speed control, Touch-Tone[DTMF] DECODERS , MODULATION/De-Modulation[MODEM], Filtering, Frequency-scaling, Frequency-control of electronic-communication-equipment, Measuring frequency of Physiological-events such as Respiration or Heart-rate.
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13-1 ) THE BASIC PRINCIPAL OF PLL:
VCO=> voltage controlled oscillators [VCO]. i. THE PHASE-DETECTOR {MIXER OR PHASE-COMPARATOR}:-
{V0 = ERROR-VOLTAGE}
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V0= its an average [DC] o/p voltage that is proportional to the difference in frequency [ fin-f0 ] and phase-difference [ ] between [b/w] the i/p-signal [Vin] of PLL and the O/P of the VCOSIGNAL [ Vo ] with frequency [ fo ] . so {V0 = ERROR-VOLTAGE= { [ ] } }
VOLTAGE-CONTROLLED-OSCILLATOR [VCO] :
[KVCO = VCO-Conversion- gain [Hz/V] ].
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[fmin = out put frequency when [ Vin=0] ] ; [ Well we study the VCO in Ch # 12 , Op-Amp course is as a Voltage to frequency Converter, VCO convertes the controlled-voltage into a frequency [Pulsed-wave form] VCO out-put frequency fo is proportional to the magnitude of the in-put voltage of VCO; VCO conversion gain KVCO relates fo to input voltage of VCO as followed equation; [i-e] ] THE LOOP-FILTER=LOW-PASS-FILTER[LPF]:
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LPF [low pass filter] remove any noise and high frequency components from the out-put voltage Vo of the Phase-detector, resulting in an average DC control voltage, that drives the VCO. Its the primary building blog that determines the dynamic performance of the loop-covering the following factors, a. Capture and lock ranges; b. Band-width; c. Transient-response; Key-> the complete [PLL] system exhibits the characteristics of a second-order system [ Analogous to the transient behavior of a swinging pendulum or vibrating string; [ Radian-frequency-> [ [ second-order-system . [ ] ]; ]; its a decibel-response of a
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If [
], then we have a sinusoidal-oscillator;
------------------[new-topic] 1. 2. 3. BASIC-OPERATION-OF-PHASE-LOCKED-LOOP [PLL]: In operation, the Phase-Locked-Loop is in any one of the following three distinct states: Free-running-state; Capture-state. Phase-Lock-state.
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If we assume that initially the Phase-locked-Loop has no input signal, the VCO then runs at its Free-running-frequency, which is set by either an external RC-filter or LC-filter network , here the loop is said to be un-locked. When an input signal is applied to the phase-detector and the VCO frequency starts to change in a direction that reduces the frequency difference b/w the VCO-freq [fVCO ] input freq [fin ] , then the loop is said to have Acquired-capture and is now in the capture-state. The fin and fo are not equal [ ] , but in time they will be equal [ ]. In order for a Phase-Locked-Loop that is initially un-locked to respond to an input signal and then be in capture state. The frequency of the input signal must be with in a narrow frequency-range called the capture-range , which is set by the response-parameters of loop circuit , if fin is out-side this capture-range, the loop will never acquire-capture and the fo of the VCO will equal its freerunning frequency. On the other hand, if the fin is within the loops capture-range, then the VCO frequency [ fo = fVCO ] start to change in a direction that reduces the frequency difference between the VCOfrequency [ fo = fVCO ] and input frequency[fin]. The capture-range is often specified as percentage of VCO free-running frequency so, that the free running frequency is within this capture-range.
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For-example: consider a system-> [ fin{PLL}fo ] , [Capture-range=Cr ] Given:-> [ Capture-range[ Cr ] = 2 % = 0.02 = Cr ]; of a [ free-running-frequency = 1250 Hz = ffR ]; so, [ [ So, [ [ [ [ loop will Acquire-Capture. If the [ ], then the loop will Acquire-Capture, and the VCO-Frequency fo will then shift to equal that of the input frequency fin [ fo = fin ] . Otherwise, the output frequency fo of VCO will remain at 1250 Hz for those [ fin < 1225 Hz ] and [ fin > 1275 Hz ]. In general-case:] ] its for Loop will Acquire Capture . ] then the ]; ]; ]
];
When the loop Acquire capture, the fin and fo of PLL are not equal, however, the process is repeated many times going around the loop, the fin and [ fo=fVCO ] are comparedby phasedetector, its DC-output voltage is proportional tothis frequency difference, after filtering through [ LPF =low pass filter ] , this frequency-difference drives the VCO whose output frequency tries to get closer to input frequency. PHASE-LOCKED: Eventually the loop will reach the situation where the VCOs frequency fo and the loops input frequency fin are exactly equal [ fin = fo ] except for a possible phase-shift, when the input[Vin] and output [Vo] signal have exactly the same frequency, except for a given phase-shift, the loop is then said to be locked or Phase-locked. The Phase-shift, if any occers because the Vco is Asynchronous with the input-signal if there is no input signal , the VCO runs along at its own pace [ i-e, its free-running frequency ] , when the loop receives an input signal, its then Asynchronous with the VCO-signal. SETTLING-TIME: Because of the loops transient-behavior, it takes a finite Amount of time for [www.medical-image-processing.blogspot.com by Sikandar Khan Lodhi] Page 11-OF-63

the loop , once it acquires capture, to become locked, this is known as Settling-Time. In a well designed Phase-Locked-Loop-System this may be on the order of several milliseconds, hence the transition from being an unlocked loop to acquiring capture and becoming locked may appear as a virtually instantaneous-process. Once locked, the input frequency fin can change with in certain limits, and the VCOs output frequencies fo will follow this change.-> [ ]. When fin changes even slightly, the phase-detector, then senses this frequency-difference and the shifting process starts all over again until the [ ] and fin are exactly the same [ except for a possible-phase-difference ] . LOCK [ OR HOLD-IN ] RANGE :- Once locked, the input frequency range over which the VCO can track is called as Lock [or hold-in ] Range . As with the loops Capture-range, the Lock[or hold-in]Range is often specified as a percentage of VCOs free-running-frequency [ ffR ] and is always wider then the capturerange . -> [ Lock{or Hold-in} Range Capture-range ] . Once the loop has acquired capture and phase-lock, if the fin then shifts to a frequency outside the lock-range, then the loop immediately loses Phase-lock and the -> [fo = ffR(VCO) ]. [ ]; For the loop to again be Phase-Locked, the new input signal then has to be with in the loops capture-range to start the cycle all over again. ----------------------------------------
[13-2 ] THE FREQUENCY-SYNTHESIZER OR FREQUENCY-MULTIPLIERS:

A Frequency-Synthesizer [or Multipliers] is a frequency source whose output is an integer multiple of an input reference frequency. In its simplest form its nothing more than a frequency multiplier and is now an important building block in many communications systems. The basic-frequency synthesizer is formed by breaking the feed back path between the VCO and Phase-detector of the basic PLL and inserting a divide by Nth counter. Example:
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In addition, the input-signal reference is Obtained from a very stable crystal-controlled oscillator in [ 1M Hz to --> 10M Hz ] range.
TTL-Based crystal controlled frequency reference from [ 1M Hz ---to- 10M Hz ]. The VCO output frequency [ fo = N.fREF(IN) ] is Nth times greater then input reference frequency [ fREF (IN) ] . The output signal of VCO with [fo=N.[fREF[IN]] ], is then fed to divided by Nth-Counter, which produces one output pulse for every Nth inputs pulses of clock to N counter. [www.medical-image-processing.blogspot.com by Sikandar Khan Lodhi] Page 13-OF-63

The counters Modulus [N] may be either fixed or programmable through [via ] thumb-wheel switches in BCD [binary coded decimal] formate. The output frequency of counter fc is then [ fc=fo/N ]; Nth counter output frequency fc = fc = [
th
].
N -Counter Out put frequency[fc ] = fc = fREF(IN) . When the loop is Phase-locked , the frequencies of two input of phase-detector are equal, except for a possible phase-difference. In communications systems , practical-synthesizers generally have their output frequency [ fo ] in { } range [ VHF & UHF ] , however, synthesizers are capable of working with low-frequency signals in Audio-frequency range [ 20 Hz --- to 20 K hz ] . Very often, a frequency-synthesizer will be used to increase the resolution of a frequencycounter by a factor of 10 or 100 with out increasing the sampling or display up-date time. Most counters use a sampling or display up-date time of 1s . in order to obtain a resolution of one more decimal place, the frequency-counter must then be set to have a sampling or display up-datetime of 10-seconds, which will take 10time longer to display the input frequency; In this 10-seconds interval, the input signal might change frequency-slightly and give erroneous-readings. Instead of using a very stable fREF(IN) , the frequency that would otherwise be measured by frequency-counter is now fed to input of the synthesizer. The frequency counter is connected to output of VCO and reads either 10 or 100 times larger that the input signal [ fig # 7 ] , forexample : a frequency-counter measures a given signal and indicates a frequency of 974 Hz because of typical ( 1 ) count error inherent to all digital-display, the actual input frequency could be between [ 973 Hz & 975 Hz ] . To achieve a greater resolution, a ( x 10 ) synthesizer is placed between the frequency source and frequency-counter.suppose, the counter reads 9746 Hz the actual input frequency is then [ 9746 Hz/10 = 974.6 Hz ] , {Actually the frequency will be b/w 974.5Hz and 974.7 Hz } , as mentioned earlier, we could set the frequency-counter to have a sampling or display time of [ 10 second ] in order to produce the extra decimal place, but it would take ten times longer to display the fin . Using the synthesizer method , the extra time lag is eliminated. All that is necessary is mentally to divide the displayed frequency by 10 [ or 100, if need be ] to obtain the correct [ input frequency fin = fREF(IN) ]. ------------------------ ANALOG-PHASE-LOCKED-LOOP [ A-PLL ] { 560-SERIES ] :[NEW-TOPIC]: There are 560-series of PLL in which [ Vo(VCO] = SQUARE-WAVE ] in all cases of 560-series [ 560B, 561B, 562, 564, 565, 566 and 567 ) . 1. 560B-PHASE-LOCKED-LOOP [PLL] OR FM-DEMODULATOR :by Sikandar Khan Lodhi] Page 14-OF-63

560-series [ Analog-PLL ] -> [ 560B, 561B, 562, 564, 565, 566 & 567 ). The devices in 560-series are commonly referred to as Analog-Phase-locked-loops and they are differ from digital-phase-locked-loops. When locked onto an input signal , two useful output are provided, that is 1) 1st , an output voltage that is proportional to frequency of incoming signal is available at [ pin # 9 ] as the de-modulated FM output. 2) 2nd, output is square-wave output signal of the VCO. The value of external capacitor, connected between pins 2 & 3 , sets the VCO freerunning frequency According to [ ]. The 560B is used primary as an FM-De-Modulator. The VCO is adjusted by Co to the center-frequency of the FM-signal. For most applications , the pair of loop-filter capacitors [ C2 and C1 ] can be calculated as let, -> [ ]. Where [ f3(dB) ] is the desired [ 3-dB ] band-width of the De-modulated-information.
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FM-DEMODULATOR-USING-A-560B [ PLL-IC ] :-
----------FINISHED HERE ---------- 561B PHASE-LOCKED-LOOP OR AM-RECIVER OR FM-DE-MODULATOR : The 561B-PLL is identical to 560B except that it includes an additional phase-detector, which allows the device to be used as a synchronous AM-detector as well as an FM-demodulator. The demodulated FM output at [Pin # 9 ] is an output voltage that is a function of the frequency deviation of input signal. For a [ 1 % ] deviation, the output is approximately [ 0.3 v ] peak-to-peak [ 0.11 VRMS ] . As an example, a standard 10.7 M Hz IF [intermediate-frequency ] circuit has a deviation of approximately [ 75k Hz ]. The percent[%] deviation is then [ [formula for Vo-> ] consequently, the output voltage swing is ],[ for Vo-> ];
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-------------------- AM-RECEIVER [OR AM-DETECTOR ] WITH 561B[A-PLL]:-
------- AM-RECEIVER [ WITH 561B [PLL-IC]:-
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This AM-Receiver unlike other AM-Receivers requires no capacitor-Inductor tank circuit for tuning, instead, the [ 365pF = CT ] Tuning-capacitor[CT] between pin-2 and pin-3 is Adjusted to make the VCO oscillate at the carrier-frequency of station to be received. To operate, the receiver circuit requires an out-side Antenna and a good ground, in addition sufficient signal [ input] must be present at input of the phase-locked-loop[PLL], otherwise a Swishing sound may result, which is due to the frequency difference between the incoming carrier and the VCO when the loop-lock is un-stable. Another draw-back to this simple circuit is the hand-Capacitance effect as a result of nongrounded capacitive tuning of VCO, one remedy for this problem is to use a Vernier dial and an insulated shaft on the tuning capacitor. Furthermore, the circuits operation may be enhanced by using an un-tuned broad-band Amplifier ahead of the receiver to increase sensitivity while limiting input[I/P]-signal levels to less than [0.5 VRMS ] . ----------------------FINISHED-------
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562 PHASE-LOCKED-LOOP[PLL] AS A FREQUENCY-MULTIPLIER/OR FREQUENCYSYNTHESIZER: The [562-PLL] is similar to 560B, except that the internal-connection between the VCO output and the phase-detector is broken [or dis-connected ]. Thus, two external connection are provided which allow for insertion of TTL[TransistorTransistor-Logic]-counters to be placed in feed-back path for frequency-synthesis .
FREQUENCY-MULTIPLIER [OR SYNTHESIZER ] :-
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NTH MODULE-COUNTER :-
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Note: for further detail about counter circuits please read the counter chapter from DLD-III [DigitalLogic-design , part-1 and 2 ] section from my blog -> www.medical-image-processing.blogspot.ca --------------------
565-PHASE-LOCKED-LOOP(PLL) [ FSK-DEMODULATOR/FSK-DECODER ]: The 565-PLL in below figure # 17 , is perhaps the most popular device of the 560-series. Its a general-purpose device similar to 562-PLL whereas the 560B , 561B, & 562 PLL are limited to frequencies below 500k Hz . The VCO-free-running frequency is found from below formula.
];
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Fig # 17 :
[ [ ];
];
[ [
]; ]; A simplest first order (N=1) [ one pole =1 capacitor ] Loop-filter (LPF) is
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formed by C2 and an approximately ( R=3.6k Ohms ).
FIG # 18
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Fig # 19 CSO=its used to eliminate spontaneous Oscillations. C1=any value. [ ]; One popular application using ( 565-PLL ) is that of a frequency-ShiftKeying (FSK) DeModulator. FSK refer to data transmission by means of a carrier frequency that is shifted between two preset frequencies. FSK is widely used with teletype-writer (TTY) systems. Over the years , several standards have been used to set mark and space frequencies, which correspond to logic-1 and logic-0 states of the binary
[www.medical-image-processing.blogspot.com by Sikandar Khan Lodhi] Page 24-OF-63

data signal several of these frequency pairs are listed in table 13-1 below. That is COMMON-MARK [ 1 ]-SPACE* 0 + PAIRS OF FREQUENCIES:Mark-frequency [ fm ] a 1070 Hz Space-frequency [ fs ] 1270 Hz Shift
200 Hz
2025Hz
2225 Hz
200 Hz
2125 Hz c
2975 Hz
850 Hz
The frequency difference between the mark [ fm ] & space [ fs ] frequencies is called the frequency-shift [ + . Let , Mark [1 ] and space [0] frequency pairs =>{ fm-fs= f }; Mark [1 ] and space [0] pairs =>{ { = frequency-shift . }; };
{Mark-frequency = fm ; space-frequency =fs } When transmitting (TTY) information using a Modulator-DeModulator [or MoDEM or MODEM + system, this frequency pair represents what is called the Originate-signal.

Whereas , the 2025-2225 Hz pair represents the frequencies of Answer signal. By law , radio-teletype or [RTTY] must have a frequency shift of less than 900 Hz to meet certain band-width requirements. Ham radio operators many years ago Adopted the (2125-2975 Hz = 850 Hz = ) Standard for RTTY. APPLICATION-OF-565 (PLL):1. FSK-DEMODULATOR (AN APPLICATION-OF-565-PLL):-
FIG # 20 : A simple FSK-DeModulator using the 565 (PLL) for a { [ fm=1070 Hz][www.medical-image-processing.blogspot.com by Sikandar Khan Lodhi] Page 26-OF-63

[fs=1270 Hz ] = f = 200 Hz } mark-space pair is shown in above FSKDeModulator Circuit. As the FSK-signal appears at input, the (565 PLL) locks onto the input frequency and tracks it between the mark and space frequencies with a corresponding shift in DC-Voltage (VDC = Vo ) at the output (O/P). The VCO-free-running frequency is depending on R1 & C1. The free-running frequency of VCO is adjusted with (5k Ohms = R1 = Rpotentiometer ) in order to give a slightly positive output voltage with an input frequency of [1070 Hz ] ( the mark [ logic-1 ] frequency ) . 67-KHz FSK-DECODER { ANOTHER 565 PLL APPLICATION}:Another application is the SCA ( Subsidiary-Communications Authorization)-Decoder-circuit in below figure 13-15 or fig 21. Some Commercial-FM-radio stations are Authorized by the FCC to broadcast un-interrupted back-ground music for commercial use in stores , factories, offices and so on , To Accomplish this , SCA programming is transmitted on a 67 k Hz subcarrier in order not to interfere with the FM stations regular programming on its Assigned main carrier channel, which can be either in mono or stereo in addition, the level of this subcarrier is only [ 10% ] of the Amplitude of the combined signal. The input is connected to FM-tuners-detector-stage (before the deemphasis network ); the output of decoder can be connected to any (Audio-Amplifier) , since the SCA Audio-response is limited to a maximum of 7k Hz .once connected, the 5k Ohms potentiometer between pin-8 and the positive supply voltage ( +VCC ) is tuned to 67k Hz.
2.
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Fig # 13-15 or Fig # 21 -------------finished-here---------567-TONE-DECODER:- { AN APPLICATION OF 567 PLL }: The 567-Tone-Decoder is a Phase-locked-Loop-system (PLL) designed specifically to respond to a given tone of constant frequency with in its band-width.
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Fig # 22 Although similar to the 561B , the 567 also has a power output stage capable of sourcing 100mA. However, its frequency range is similar to the 565, which is limited to 500k Hz. The free-running VCO-frequency [ + is often called centerfrequency [ fo ] is set by as follow.
[ ];
]; The value for C2 is best found from the graph of bandwidth versus input
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signal [ Vin = Vi ] amplitude ( in blow graph ) usually given on 567 datasheet.
--------------567 BAND WIDTH VERSUS INPUT SIGNAL [ Vi ] AMPLITUDE CURVE FOR THE SELECTION-OF-CAPACITOR-C2 :BAND-WIDTH VS [ VERSUS ] INPUT SIGNAL [Vi ] AMPLITUDE GRAPH:-
Fig # 23 Key-point However , the value for C2 can be determined based on the level of the input signal [ Vin ] .
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Example 1. CASE-1 ( FOR Vin < 200 m V (RMS) ):[ ]; 2. CASE-2 ( FOR Vin > 200m V(RMS) ): For input levels greater than 200mV(RMS) , the band-width is then typically 14% of center frequency [ fo ]. That is Mathematically: [ Or [ ]; ];
When the loop is locked , the output at pin 8 is at ground. When the loop is un-locked, (pin-8) is at the supply-voltage (+Vcc ), which can range from ( +4.75 V to +9V = +Vcc ). BASIC-TONE DECODER-CIRCUIT:-
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Fig # 24: Because of its internal design , the 567 becomes some what sensitive to those input frequencies that are odd harmonics of the central-frequency . As a consequence, the 567 may lock onto frequencies that are f0/3,fo/5,fo/7,.infinity = Odd-harmonics frequency. f0/3,fo/5,fo/7,.infinity = Odd-harmonics frequency. Further more the loop may also lock onto frequencies near [ ];
Where * N=any integer=1,2,3,4,.,infinity +; If these such type of frequencies are Anticipated then they should be filtered (or
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Attenuated or Rejected ) before it reaching the 567 PLL IC input. -----------------------finished--Example # 13-1 ) using basic 567 PLL tone decoder circuit and find component value for R1,C1,C2 and C3 to meet the following specifications. Given : Input frequency = fo =700 Hz . Vin = input signal level = 100mV (RMS). Band-width ( BW ) = 12% of center-frequency [ fo ]. Solution: For R1 :- [ [ [ ------------------We Assume C1 as : C1= 0.1 F * its a Standard value of capacitor +. ]; ]; ];
--------------[ FOR C2 :[ ]; +; * we use 15k Ohms which is a standard value +
{:. Band-width ( BW ) = 12% of center-frequency [ fo ] }


[ [ ]; ]; [ Use a 1 F standard value ]
For C3 :[ [ ]; ]; [ Use a standard value ]
Fig # 25
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----------finished------AN-APPLICATION-FOR-THE-567-PLL: An application for the 567 is the decoding of touch-tone-signals, such as that use by most push-button-telephones. The Touch-Tone information is coded in tone-pairs using two of seven possible tone frequencies for the numbers (0) through (9) and the symbols (#) pound and (*) star. The seven Audio-frequencies used for these 12-keys are summarized in matrix form in table 13-2. The seven frequencies are divided into a low-tone group with frequencies of 697,770, 852, and 941 Hz and a High-tone group having frequencies of 1209,1336 and 1477 Hz each of 12 numbers & symbols are then represented by a unique pair of frequencies. One frequency is represented from each tone-group. [ ]; Table 13-2
Low-Tone Group ( f0 )
High-Tone-Group ( fo ) 1209Hz 1336 Hz 2 5 8 1477 Hz 3 6 9
697 Hz 770Hz 852Hz
1 4 7
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941 Hz * 0 #
For Example, The number 9 is represented by an ( fo= 852 Hz ) tone from the low-tone group and a ( fo = 1477 Hz ) tone from the High-tone-group. To decode the tone frequencies properly for number (9) from the 12 possible choices, two 567 decoders are needed. As shown in below figure # 26.
Fig # 26 when the touch-tone signal corresponding to number [ 9 ] is present at the circuit input , both decoder will be locked and output of both decoder will

be at logic *0s+ * ground+ . the output of NOR-gate will then be logic * 1s + ( +Vcc=+5 V for TTL ICs).if only one of required two tone frequencies is present, at input then only one of the decoder output will be at logic-0, so that the output of NOR-gate is also logic-0. Now, the below circuit is complete touch-tone decoder that is capable of decoding all 12-possible tone pairs.
Fig # 27 -----------finished-here---------
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4046-CMOS-PHASE-LOCKED-LOOP [ CMOS-PLL ] : The 4046 is a CMOS PLL device made by RCAand comes in 16-pin DIPconfiguration. One of the major differences between the 4046 and the 560 series is that the 4046s phase-detector system is digital rather than analog. Furthermore , the 4046 contain two different types of phase-detectors both of which require that the input signal have 50% duty-cycles . The VCO frequency [ fVCO ] is at a minimum [ fVCO (MIN ] ] when its input control voltage is zero and increases linearly to a maximum [ fVCO [ MAX ] ] when input control voltage [ Vin [ Control ] ] equal +VDD . Graphically.
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Fig # 28 :
Typically : [ ]; The frequency range , [ fVCO [ MAX ] fVCO [ MIN ] ] , of VCO is set by external components R1 and C1 whereas the minimum VCO frequency is controlled by R2 and C1 . [ [ ]; ];
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[ ]; The VCO can be turned-off at any time , reducing power consumption when its not in used, by connecting the inhibit-input ( pin-5) to (+ VDD) , otherwise (pin-5) is normally connected to ground.
-------APPLICATION-OF-4046 PLL [ CMOS PLL] :KEY-POINT 4046 frequency multiplier ( or synthesizer] is extremely useful when measuring the frequency of physiological events such as Respiration or Heart-Rate , one of the Bio-Medical engineering Application which used in Bio[www.medical-image-processing.blogspot.com by Sikandar Khan Lodhi] Page 40-OF-63

medical Instrumentations. 1. APPLICATION-NO-1 [ 4046 LOSS-OF-LOCK-CIRCUIT ]: In the below circuit the output of phase detector II ( Pin 1 ) can be NORed ( NOR ) with the output of phase-detector I ( pin 2 ) to form a lock detector . The output of last 4001 CMOS NOR gate will be a logic-1 when the ( 4046 PLL ) is locked. Circuit Diagram :-
2. APPLICATION NO-2 [4046 (PLL-CMOS)] : CMOS Phase-Locked Loop [ CMOS PLL ] frequency multiplier for increasing the resolution of frequency counters. An with many PLL-ICs , the 4046 can be used as a frequency-synthesizer

(or Multiplier) by inserting a CMOS-counter in the feed-back path between VCO (pin-4) output and phase-detector (pin-3). Application OF CMOS ( CMOS-4046 PLL ) Based frequency-multiplier its extremely useful when measuring the frequency of physiological events such as respiration or heart-rate-counter. EXAMPLE-OF-CMOS ( 4046 PLL ) BASED FREQUENCY MULTIPLIER (OR SYNTHESIZER) WHICH MULTIPLY INPUT (I/P) FREQUENCY BY 10n-FACTOR [ ]:-
Note: In above example circuit of frequency multiplier we can multiply the input frequency [ fin ] by the factor of 10n to form any required frequency at the output where [ n = No of 4017 ( CMOS ) Decade-Counter stages +.

When used with an ordinary-frequency counter, the resolution is then increased from ( 1 ) Hz to ( 0.01 Hz ) while still having a time base sampling or update time of 1second thus an input frequency of 59.72 Hz would be displayed as 5972 Hz . other wise , all you would observe is either 59 or 60 Hz. If the counters modulus is made equal to 60, the same technique can be used to display the input frequency in terms of cycles per minute. ------------------------------finished-here-----------BASIC-OF-PHASE-LOCKED-LOOP (PLL) OR BASIC PRINCIPLE OF PHASELOCKED-LOOP (PLL) :APPLICATION: In addition to FM-De-Modulation , PLLs are used in a wide variety of communication Applications , which include TV-Receiver, Tone-decoders , telemetry-receivers (Bio-Medical Telemetry-system), MoDems * Modulations/De-Modulations ] , data-synchronizers and in Bio-Medical Instrumentations , e.t.c. BASIC-PLL CONCEPT : The Phase-locked-Loop*PLL+ is a feed-back circuit consisting of a Phasedetector, a low-pass filter, and voltage controlled oscillator [VCO], some PLL also include an amplifier in the loop, and in some Applications the filter is not used. The PLL is capable of locking onto or synchronizing with an incoming signal , when the phase of the incoming signal changes, indicating a change in frequency, the Phase-detectors output increase or decrease just enough to keep the VCO frequency the same as the frequency of the incoming signal . The general operation of a PLL is as follows the Phase-detector compares the phase difference between the incoming signal Vin and the VCO signal V0 ;

When the frequency of incoming signal fin is different from that of the VCO-frequency [fo + , the phase angle between the two signals is also different. The output of phase-detector and filter is proportional to phase-difference of two signals this proportional voltage is fed to the VCO forcing its frequency to move towards the frequency of the incoming signal until the fin and fo become equal. At ( fin = fo ) the PLL is locked onto the incoming frequency , if fin changes the phase difference also changes , forcing the VCO to track the incoming frequency.
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Fig # 32 [ Basic-Phase-Locked-Loop PLL ]: 1. PHASE-DETECTOR (= LINEAR-MULTIPLIER ): The Phase-detector in a PLL is basically a linear-Multiplier.
Fig # 33 [ Phase-detector ] :Let, [ [ ]; ];
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Fig # 34 [ Phase-Detector ] .
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Fig # 35 [ Phase-Detector ] Calculations: [ ---------------Let, [ Non-inverting Amplifier gain = ----So, by putting above value in eq-A we get; ]; ];
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[ [ [ [ -----------------As we know [ [ ----------------[ ];
]; ]; ]; ];
]; ];
];
---------------and {:. ---------- The Phase detector = Linear-multiplier multiplies these two signals and produce a sum and difference frequency output [ ].
[
[ ];
are relative Phase angles of two signals . }
];
When the PLL is Locked [ fin= fo ] :
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[ fin= fo ] & => [ When PLL is locked=> then (fin = f0 ) . Therefore:
[ ];
];
];
];
];
So the part of above equation which is high-lighted in light blue color will filter-out [ or Attenuated ] by filter [ LPF ] 1st order LPF. The second cosine term in the above equation is a 2nd harmonic term [ ] and its filtered out by LPF (N=1, 1st order ) in PLL-system so then the control votage ( Vc) at the output of filter (LPF) is below .
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Fig # 36 :
[ [ [
]; ]; ]; The filter output voltage vc is proportional to the Phase difference between the incoming signal [ Vin ] and VCO signal [ Vo ] and is used as the control voltage [ vc ] for VCO .
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[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ] -----------finished-here-------THE-VOLTAGE-CONTROLLED-OSCILLATOR [VCO] : The voltage controlled-oscillator (VCO) can take many forms , A VCO can be some type of LC or crystal Oscillator, or it can be some type of RC-Oscillator or Multivibrator, No matter the exact type most VCOs employed in PLLs operate on the principle of variable reactance using a varactor diode as a Voltage variable capacitor . The capacitance of a Varactor-diode varies inversely with reverse bias-voltage. The capacitance decreases as reverseVoltage increases and vice-verca. [ Capacitance of varactor diode 1/ Reverse-bias-Voltage ];
In a PLL, the Control Voltage ( vc ) feed back to the VCO is applied as a reverse-bias-voltage to varactor-diode with in the VCO, the frequency of oscillation is inversely related to capacitance for an RC-type oscillator by below formula. [ ];
And for an LC-type oscillator by the formula: [ [ ]; Capacitance * C + decreases as reverse (control-voltage )-Voltage increases , therefore, increase in control-voltage to VCO cause
];
[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ] an increase in frequency and Vice-verca. BASIC VCO OPERATION IN PLL-SYSTEM:-
Fig # 37 fo (nom ) = ffR ( VCO ) = fo ( Nominal ) = VCO free-running frequency. The basic-VCO operation is shown in above figure # 37, the above graph shows that at the nominal-control voltage [ Vc ( nom ) ], the VCO-Oscillator is running at its nominal or free-running frequency [ fo ( nom ) ], an increase in Vc above the nominal value force the VCO-oscillator frequency to increase and a decrease in
[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ] Vc below the nominal value force the VCO-Oscillator frequency to decrease. There are of-course, limits on the operation as indicated by minimum and maximum points. The Transfer-function or conversion-gain ( k) of VCO is normally expressed as a certain frequency deviation per unit change in control-voltage [ Vc ].
[ ];
BASIC-PLL-OPERATION:1. When PLL is Locked, than [ fin = fo ] , however there is always a phase difference between them which is called the StaticPhase-Error [ + .that is [ [ 2. The phase-error [ . ]; its control voltage. ]; + , is parameter that keeps the PLL Locked in
1. CASE-STUDY : [ (a) PLL is Locked ( see in below fig # 38 ) ]:-
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Fig # 38 [ PLL is Locked ]: (b) PLL is Un-Locked [ see in below fog # 39 (a) and (b) :-
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Fig # 39 PLL is Un-Locked , (a) circuit Diagram
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Fig # 39 PLL is Un-Locked , (b) wave Form 2. CASE-STUDY : { PLL is Locked (see in fig # 40 ) }:-
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Fig # 40 [ PLL is Locked ]:---------finished-here--------LOCK ( or HOLD-IN ) RANGE : Once the PLL is Locked , it will track frequency changes in the incoming signal. The range of frequencies over which the PLL can maintain Lock is called the lock-range ( or hold-in or tracking-range). Limitations on hold-in range are maximum frequency deviations of VCO and the output limits of Phase-detector.
[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ] The hold-in range is independent of the band-width [BW] of the low-pass filter because , when the PLL is in Lock state, the difference frequency ( fin fo ) is zero or a very low instantaneous value that falls well within the band-width. The hold-in range is usually expressed as a percentage of VCOfrequency. CAPTURE-RANGE : Assuming the PLL is not in lock state , the range of frequencies over which PLL can acquire lock with an incoming signal is called the capture-range. Two basic conditions are required for a PLL to Acquire lock , which are given below. a. Difference frequency ( fo-fin ) must be low enough to fall with in the filters band-width . this means that the incoming frequency must not be separated from nominal or free-running frequency of the VCO by more than the band-width of LPF. b. The maximum deviation , of VCO frequency must be sufficient to allow fo to increase or decrease to a value equal to fin , As shown in bbew figure # 41 and when they exist , the PLL will Pull the VCO-frequency towards the incoming frequency until ( fo = fin ) .
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Fig # 41 [ Frequency Spectrum Graphical Analysis ]
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Case-1 :-
Fig # 42 [ Case-1 ]
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[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ] CASE-2 :
Fig # 43 [ CASE-2 ] :--------Finished-here---------THE LM-565 PHASE-LOCKED-LOOP [PLL] : The LM-565 is used as a PLL based FM-DeModulator. The LM-565 IC [Integrated-circuit] of PLL is used a good example of an PLL. The circuit consists of a VCO , Phase-detector , a Low-Pass Filter [ LPF ] of order [N=1 or one pole or one capacitor LPF circuit ],
[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ] formed by an internal-resistor and an external-capacitor an d an Amplifier. The free-running VCO frequency [ ffR ( VCO ) ] can be set with external components. The LM-565 PLL can be used for frequency range from 0.001 Hz to 500k Hz, that is : CALCULATIONS:[ [ FOR LOCK-RANGE f(Lock) :[ [ Where: The Vcc is the total Voltage between the positive and negative DCsupply voltage terminals. FOR CAPTURE-RANGE ( fcap ):[ ];
]; ];
]; ];
{:.
} => its a internal fixed value of LPF Resistor.
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[ ];
Key-point you can see that the capture range is dependent on filter band width as find by internal resistor ( RLPF = 3.6 k Ohms ) and external-capacitor [ C2 = CLPF ] . BLOCK-DIAGRAM-OF-(LM-565 PLL ) :-
Fig # 44 [ LM-565 PLL ] INTERNAL-CIRCUIT BLOCK DIAGRAM OF LM-565 PLL : ------------------Finished-here---------------------------- Ch-13 on OP-AMPs on Phase-Locked-Loop [PLL] finished[www.medical-image-processing.blogspot.com by Sikandar Khan Lodhi] Page 63-OF-63
[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ] here----------------
X
MUHAMMAD-SIKANDAR-KHAN-LODHI OWNER OF MY PERSOLAL NOTES
Saturday, June 15, 2013
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Phase Lock Loop (PLL), Op-Amp, Ch-13 in Bio-Medical Engineering

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Phase Lock Loop (PLL), Op-Amp, Ch-13 in Bio-Medical Engineering

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2013

*,ANALOG- PHASE-LOCKEDLOOP [A-PLL+ ON OPERATIONAL-AMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

MUHAMMAD-SIKANDAR-KHAN-LODHI BIO-MEDICAL ENGINEERING GUIDE.INC 6/15/2013

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

VCO=> voltage controlled oscillators [VCO]. i. THE PHASE-DETECTOR {MIXER OR PHASE-COMPARATOR}:-

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

[KVCO = VCO-Conversion- gain [Hz/V] ].

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

], then we have a sinusoidal-oscillator;

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

[13-2 ] THE FREQUENCY-SYNTHESIZER OR FREQUENCY-MULTIPLIERS:

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

------- AM-RECEIVER [ WITH 561B [PLL-IC]:-

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

FREQUENCY-MULTIPLIER [OR SYNTHESIZER ] :-

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

]; ]; A simplest first order (N=1) [ one pole =1 capacitor ] Loop-filter (LPF) is

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]

[{ANALOG} PHASE-LOCKED-LOOP [A-PLL] ON OPERATIONALAMPLIFIERS IN BIO-MEDICAL ENGINEERING [BME], CH-13 ]

by Sikandar Khan Lodhi]