CHAPTER 5

RISC Processor Design

The processor provides a mechanism where inputs are received, certain operation is performed on them and output is generated. The operation performed by the processor depends on the instruction set of the machine. The first point to designing a processor is thinking about the instruction set of the machine. Instruction Set architecture (ISA) describes instruction set, word size (as instruction are stored in memory), address modes (like direct, Indirect, Indexed) and processor registers to support the instruction set. The depth of ISA depends on function of the processor which might be General Purpose, Media Processor, DSP Processor, Network Processor etc. The second step is micro architecture; it defines Data Path and Storage elements. Microarchitecture determines how a certain ISA will be implemented. There are certain type of microarchitecture which are very popular i.e. RISC, CISC, MIPS, VLIW etc. The microarchitecture is classified on the basis of ISA organization. RISC (Reduced Instruction Set Architecture) makes number of instructions very less, only most needed instructions are added in ISA, this reduces the size of word size, busses, Memory Elements and Instruction decoder. However the programmers have to work hard with fewer instructions, for example if Instruction set does not contain instruction of multiply, it will be done by using Shift and Add Instructions. CISC (Complex Instruction Set) takes the alternative approach in this concern, it include more instructions. This increases the architectural complexity but reduces programmer labor. We will address 8-Bit RISC Processor with 16 Instructions; the purpose of the design will to comprehend the basics of Processor and its component design. This chapter requires complete understanding of ASMD based designs and partitioning.

5-1: ISA(Instruction Set Architecture)

Instruction Set architecture defines Instruction Set and Instruction word. The Instruction Set of any processor depends on the operation a processor can perform. Media Processor will have instructions supporting Media algorithms, similar can be deduced about DSP Processor. Instruction Set have set of instructions capable of performing a certain job. Generally these Instructions are classified into Four Categories on the basis of operation they perform Arithmetic, Logical, Memory based and Branching. In this section we will defines a small processor as an example, table 5-1 present Instruction set for the processor.

Table 5-1: Instructions Set for 8-Bit RISC Processor

ARITHMETIC ADD SUB MUL LOGICAL (Move register operation) AND is OR CMP SLR SLL Addition Subtraction Multiplication Logical AND Logical OR Complement Shift Logical Right Shift Logical Left 0000 0001 0010 0011 0100 0101 0110 0111 ADD R1,R2 SUB R1,R2 MUL R1,R2 AND R1,R2 OR R1,R2 CMP R1 MOV R1,2 SLL R1,AMT R1R1+R2 R1R1-R2 R1R1xR2 R1R1&&R2 R1R1||R2 R1!R1 R1>>2 R1<<2 Amount MOV BRANCH BRZ BRNZ BRLT Move Branch Zero Branch Not Zero 1000 1001 1010 SLR R1,AMT BRZ ADDRESS BRNZ ADDRESS BRLT ADDRESS,R1,R2 R12 PCADDRESS, if ZFLAG is 1 PCADDRESS, if ZFLAG is 0 PCADDRESS, if CMPFLAG is 1 1100 JMP ADDRESS PCADDRESS AMT is shift

Branch Less Than 1011 Zero

JMP

Jump Unconditional

MEMORY BASED

RD WR HALT

Read Write Halt

1101 1110 1111

RD R1,ADDRESS WR R1,ADDRESS HALT

R1MEM[ADDRESS] MEM[ADDRESS]R1

5-1-1: Instruction word design The instruction set given in Table 5-1 give 16 instructions at assembly language. The next step is to define instruction word, the purpose of Instruction word is to define mechanism to store the assembly based program inside memory. The assembly mnemonics are given in table 5-1 with op code, the instruction word defines how are certain program in Assembly is represented in Machine Language. RType- Register Type Instruction The register type instruction has two Register fields of 2-Bits. The register File will contain Four Registers. The instruction of RType Include all Arithmetic Instruction, AND, OR and CMP instructions. The R-Type instrution is 1-byte. OPCode(4Bits) Des Reg(2Bits) Src Reg(2Bits)

SRType- Single Register Type Instruction Single Register Type instruction include instructions with single register field. The remaining two bits are either given for Immediate Value as in MOV instructions or to Give Shift Amount. OPCode(4Bits) Branch Type Instruction All branching instruction are two byte instruction with second byte containing 8-Bit Address to address 256x8 Memory. The Src and Des Register Fields are donot care. OPCode(4Bits) Address (8 Bits) Memory Type Instruction The Memory Type Format is two byte instruction same as Branch, except for SRC/DES are not donot care. In Read Instruction Destination register is given and write instruction has Source register enabled. OPCode(4Bits) Address (8 Bits) SRCReg(WR Instruction) DesReg(RDInstruction) XXXXXXXXXX XXXXXXXXXX Des Reg(2Bits) Shift Amount /Immediate Value (2Bits)

Figure 5-1: Instruction Word for the instruction set given in Table 5-1
5-1-2: Conversion of Assembly Program into Machine Level Language

ISA also involve Address modes, however to keep the things simple we have not discussed address modes in this design. To Illustrate the Translation of Assembly code into machine level code Example 5-1 gives an assembly level code of program which sum all even numbers till 20. The memory of the design is Von Neuman with logical partitioning of Memory; however buses are separate for address and data. First 200 locations contain Code memory and next 56 locations contain data memory. Design Example 5-1: Translation of Assembly Level Code into Machine Level Code
The program will calcualte sum of even numbers till 20. Code is given in both C and aseembly level languages and possible machine level is given below. int sum; for (int i=0;i<=20;i+=2) { sum+=i; } 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8 9 10 0110 0110 1101 200 0110 0000 0001 1010 5 1111 xx xx 11 00 10 xx 01 01 11 xx

MOV R0,2 MOV R1,2 RD R2,200 MOV R3,1 LOOP: ADD R0,R1 SUB R2,R3 BRNZ LOOP HALT
00 01 10 10 10 xx

# Location 200 Contains 10

Assembler maintains a table called Label Table, which is mostly used in Loops. The line-5 of assembly has label LOOP the address of this label is 5. The Line 9 of Machine Level code contains address 5.

5-2: Micro Architecture

Data path of Processor is called Microarchitecture, it defines register File, ALU, Data bus, address bus , Registers associated and all other components.

INC_PC LD_PC RST_PC RW_RFile Add1_RFile(4) Add2_RFile(4) Din_RFile(8)

PC

Register File

CONTROL UNIT

Din_Mem(8) RW_Mem OpCode_ALU (3) Flag_ALU(3) ShAMT_ALU (2) Dout_Mem(8) LD_DReg

Memory ALU
256x8

DREG
Add_Mem(8)

Data_IM(2)

Sel_MData Sel_MAdd

MUX_DATA

MUX_ADD

LD_IR Inst(8) LD_AReg

IR

AREG

Figure 5-2: Micro Architecture of 8-Bit RISC Processor(Width of bus is 1 otherwise indicated)

Table 5-2: Summary of 8-Bit RISC Processor Micro Architecture Components

Register File Register File Contain Four Registers with two address lines for two consecutive reads and single write at Address-1. Read Write control decides whether to read or write on the Register File. The Data Write Input is connected to the data bus of the system shown in Bold Line in Figure 5-2. ALU ALU take two 8-bit inputs and perform operation based on 4-Bit op code performed. As a result ALU store the result in Data Register. The 3-Bit Flag is passed to control unit containing Flag for Zero and 2-Bit Flag Bits for Comparison of Inputs. First 3-Bits of Opcode are passed to ALU, this is for a reason that all ALU concerned instructions are covered in First three bits i.e. 4b0111. PC Program Counter contains the current pointer to the program. Program counter can be Reset or Incremented by the control unit. The Address Bus is connected to the Program Counter; its loading is controlled by control Unit. This option is used in Branching. Memory Memory contains 256 locations with each location is 8bit. The 256 location are divided into two parts first 200 locations as Code Memory and the next 56 locations as Data Memory. This architecture is Von Neuman Architecture with shared memory space. The Address of Memory is taken from Address Register (AReg). The output of Memory is given to both Address and Data Selection Multiplexers. The Memory Data put can go to address bus in case of two byte instructions and to Data bus in case of one byte instructions. The First 8-bits of Two byte instruction go to Data bus. Mux_Data Data Multiplexer select the data input from ALU or memory. It takes data from ALU when the result of ALU is to be stored in Register File and from Memory when data is to be stored in Instruction Register (IR) called fetch. Mux_Add Address Multiplexer selects address source from either Program counter (in fetch) or from Memory (in case of Read/Write operations). AReg IR Stores address for the memory, the address selection is done by Address multiplexer. Instruction Register Stores the Current Instruction taken from Memory and passes it to control unit. Dreg Data Register stores the Result of ALU, this result is written in Register File in Next Clock Cycle.

5-3: Micro Architecture Operations

The Microarchitecture presented in the last section contains the entire program in the code memory. The program is translated from assembly language to machine by assembler. The assembler writes this program in the instruction memory of the processor. The processor brings this code line by line (location by Location) from the memory to the instruction register (fetch). The First Stage for every location in Memory or Every line in Assembly is fetch i.e. to bring the instruction from memory to Instruction

register. Once the instruction is fetch the control Unit will execute the instruction depending on type of instruction fetch. The Op Code of the instruction in focus is used to determine what action should be taken to perform a relevant execution, this stage is called decode. The instruction is been fetch and it is known what instruction is brought (decode), finally the instruction is execute. The results of the execution are written back to the memory or register file, this step is called write back. The program is present in the memory, data path fetch, decode, execute and write back the program location by location. This operation is controlled by the Control Unit of the design.

Table 5-3: Summary of 8-Bit RISC Processor Micro Architecture Operations

Fetch Every instruction is Fetch from the memory, location by location. The address of the fetch is maintained by Program counter. The instruction is fetch into instruction register which is finally passed to Control Unit as shown in Figure 5-3. Execute Register Type Instruction Every instruction after been fetch is executed. The execution depends on Type of instruction. In case of R Type instruction the register file passes the address of registers on which operation is required. ALU is passed with these register which perform operation based on OP Code. The results are stored in data register and Flags are passed to control Unit. This is shown in Figure 5-4. Write Back The results stored in Data Register from Execution stage of Register Type instruction are passed to register file. This is shown in Figure 5-5. The address of second byte is brought from PC to Address register. This cycle is shared for branch operation and memory based operation. Branch Instruction Read, First Cycle Write Clock Branch instructions are first fetch then the second byte instruction word is stored in to Program Counter Creating a Jump on the required location. This is shown in Figure 5-6. The read/write instructions are first Fetched. Both instruction share common First State. The address stored in second byte of these instruction is not data itself but is indirect address of location where is data is to be written or to be read. In this State the Second byte of data is stored in Address register. This is sort of feedback of address.
Read Second In second cycle of read data is read from the location referred. And the data is written into register File. The first clock cycle of Read/Write is shown in Figure 5-7 while Second Clock Cycle of Read is shown in Figure 5-8. The second clock cycle of write is same as for read except for data is written from register file into memory location indicated by address register as shown by Figure 5-9.

Register Type Fetch 2 Byte

Clock Cycle Write Second

Clock Cycle

5-3-1: Fetch Operation Figure 5-3 indicates fetching of Instruction from the memory. The program counter is initially zero it points the first location of the memory, on each fetch it is incremented to the next location by the program counter.

INC_PC LD_PC RST_PC RW_RFile Add1_RFile Add2_RFile Din_RFile

PC

Register File

CONTROL UNIT

Din_Mem RW_Mem OpCode_ALU Flag_ALU ShAMT_ALU

Memory ALU
Dout_Mem

256x8

LD_DReg

DREG
Add_Mem

Data_IM

Sel_MData Sel_MAdd

MUX_DATA

MUX_ADD

LD_IR Inst LD_AReg

IR

AREG

Figure 5-3: Fetch Operation Illustrated in Bold

The address in the program Counter is passed from MUX_ADD to the AReg(Address Register). The data in the program memory is read and is passed to IR using MUX_DATA. This instruction is passed to control unit. This job is fundamental to any instruction in the memory. 5-3-2: Execute and Write back in Register based instructions Figure 5-4 show the execution of register based operation. Two addresses are passed to the register file, resulting two connective reads. ALU takes this data and performs operation based on OPCode_ALU.

INC_PC LD_PC RST_PC RW_RFile Add1_RFile Add2_RFile

PC

Register File

CONTROL UNIT

Din_RFile

Din_Mem RW_Mem OpCode_ALU Flag_ALU ShAMT_ALU Dout_Mem LD_DReg

Memory ALU
256x8

DREG

Add_Mem

Data_IM

Sel_MData Sel_MAdd

MUX_DATA

MUX_ADD

LD_IR Inst LD_AReg

IR

AREG

Figure 5-4: Register based Operation, Execute Illustrated in Bold

It is a 3-bit field which tells ALU which operation is to be performed. If the instruction is shift based 2-Bit ShAMT_ALU indicates amount of shift required. The result of Register Execution is stored into Data Register and FLAG_ALU are passed to the control Unit. FLAG_ALU are 3-bit Containing Zero Flag and Comparison Flag. The last two bits are comparison Flag, which combines to determine whether first number is Greater than second (00), Equal to second (01) or less then second (10). The second clock cycle of register based operation is shown in Figure 5-5 it is write back operation. The result in Figure 5-4 is Stored in Data Register. Write back writes data from Data register to Register File. the Destination register is indicated by the control unit.

INC_PC LD_PC RST_PC RW_RFile Add1_RFile Add2_RFile Din_RFile

PC

Register File

CONTROL UNIT

Din_Mem RW_Mem OpCode_ALU Flag_ALU ShAMT_ALU Dout_Mem LD_DReg

Memory ALU
256x8

DREG

Add_Mem

Data_IM

Sel_MData Sel_MAdd

MUX_DATA

MUX_ADD

LD_IR Inst LD_AReg

IR

AREG

Figure 5-5: Register based Operation, Write Back Illustrated in Bold

5-3-3: Fetch 2 Byte Both two words type instructions i.e. branching and memory based operations require program counter address in the Address register to read second byte. This cycle is similar to normal fetch shown in Figure 5-3. The Fetch 2 byte is shared in both Branch and read, write instructions. After it is known after decoding that Instruction is not HALT, R-Type or SR Type the processor goes to Fetch 2 Byte state.

5-3-4: Execute in Branch based instruction The Branch operation is shown in Figure 5-6, the Program Counter leaves it regular incremental process and jumps to address either on certain condition or unconditionally. The instruction word in Figure 5-1 indicates that the address where the branch is taken is kept in the second byte of the instruction. The second byte is read from the memory and store the result in program counter. The Dout_Mem is loaded into PC by asserting LD_PC and making SEL_MADD as 0.

INC_PC LD_PC RST_PC RW_RFile Add1_RFile Add2_RFile Din_RFile

PC

Register File

CONTROL UNIT

Din_Mem RW_Mem OpCode_ALU Flag_ALU ShAMT_ALU Dout_Mem LD_DReg

Memory ALU
256x8

DREG
Add_Mem

Data_IM

Sel_MData Sel_MAdd

MUX_DATA

MUX_ADD

LD_IR Inst LD_AReg

IR

AREG

Figure 5-6: Branch Operation, Illustrated in Bold

5-3-5: Read and Write Operations The read and write instructions share common first Clock Cycle as shown in Figure 5-7. The read/write instructions contain second byte with address. This is indirect address where the read/write is to be done. The data in second byte of read/write is only an address referring to location where either data is written in memory or to be read from memory.

INC_PC LD_PC RST_PC RW_RFile Add1_RFile Add2_RFile Din_RFile

PC

Register File

CONTROL UNIT

Din_Mem RW_Mem OpCode_ALU Flag_ALU ShAMT_ALU Dout_Mem LD_DReg

Memory
ALU
256x8

DREG
Add_Mem

Data_IM

Sel_MData Sel_MAdd

MUX_DATA

MUX_ADD

LD_IR Inst LD_AReg

IR

AREG

Figure 5-7: Read and Write Operation, First Clock Cycle

The DOut_Mem contains the second byte of instruction which is feed back to AReg(Address register). For example the second byte of instruction contains 200 and this instruction is present at location 5 of program memory, then 200 will be feed back into AReg. As discussed in the Figure 5-7 that Address register will now contain the address at second byte of read instruction For example 200 while PC will still hold the address of active program memory i.e. 5. First address in PC is incremented to point to the next address i.e. 6.

INC_PC LD_PC RST_PC RW_RFile Add1_RFile Add2_RFile Din_RFile

PC

Register File

CONTROL UNIT

Din_Mem RW_Mem OpCode_ALU Flag_ALU ShAMT_ALU Dout_Mem LD_DReg

Memory ALU
256x8

DREG
Add_Mem

Data_IM

Sel_MData Sel_MAdd

MUX_DATA

MUX_ADD

LD_IR Inst LD_AReg

IR

AREG

Figure 5-8: Read Operation, Second Clock Cycle

Figure 5-8 explains the second clock cycle of read operation while Figure 5-9 explains second clock cycle for Write operation. The AReg points to the indirect address, DOut_Mem has data from memory which is passed to register file through MUX_DATA.

INC_PC LD_PC RST_PC RW_RFile Add1_RFile Add2_RFile Din_RFile

PC

Register File

CONTROL UNIT

Din_Mem RW_Mem OpCode_ALU Flag_ALU ShAMT_ALU Dout_Mem LD_DReg

Memory ALU
256x8

DREG
Add_Mem

Data_IM

Sel_MData Sel_MAdd

MUX_DATA

MUX_ADD

LD_IR Inst LD_AReg

IR

AREG

Figure 5-9: Write Operation, Second Clock Cycle

The second Clock Cycle of write instruction writes Data from Register File into Memory using Din_Mem. The RW_RFile is selected to read data from the Register File and Add1_RFile indicates the address of source register of the register file. The second address in this case is donot care, and does not carry any

significance. Last but not least the move instruction passes the data to be moved on Data_IM line from the control unit. It is passed from MUX_DATA to the register File.

5-4: HDL code for Micro Architecture

The discussion will focus on FPGA based design and Behavioral simulations. The first module we will discuss is register file, containing 4 registers each of 8bit. 5-4-1: Register File Figure 5-10 show the Block Diagram and Verilog code of Register File.

RW_RFile Add1_RFile(2) Add2_RFile(2) Din_RFile(8) DOut1_RFile1(8)

Register File
DOut2_RFile2(8)

module RFile(input RW_RFile,input [1:0] Add1_RFile,input [1:0] Add2_RFile,input [7:0] Din_RFile, output reg [7:0] DOut1_RFile,output reg [7:0] DOut2_RFile, input Clk,input Enb_RFile); reg [7:0]RF[3:0]; always@(posedge Clk) if(Enb_RFile==1) if(RW_RFile==0)//Read begin DOut1_RFile<=RF[Add1_RFile]; DOut2_RFile<=RF[Add2_RFile]; end else //Write begin RF[Add1_RFile]<=Din_RFile; DOut1_RFile<=8'd0; DOut2_RFile<=8'd0; end else begin DOut1_RFile<=8'd0; DOut2_RFile<=8'd0; end endmodule

Figure 5-10:Register File Design

5-4-2: Program File Figure 5-11 Show Design of Program Counter, its a special register with increment, data loading and Reset Facility in it. Program counter keep the current address of the program to be fetch, it is increment once in all 1-Byte instructions and incremented twice in two byte instructions. Program Counter point the memory location by location, however the normal flow of program counter may change in case of branch instructions.

INC_PC Din_PC(8) RST_PC

PC

DOut_PC(8)

module PC(input INC_PC,input RST_PC,input LD_PC, input[7:0] Din_PC, output [7:0]DOut_PC,input Clk); reg [7:0]RPC; assign DOut_PC=RPC; always@(posedge Clk) if(RST_PC) RPC<=8'b0; else if(INC_PC==1) RPC<=RPC+1; else if(LD_PC==1) RPC<=Din_PC; Endmodule

Figure 5-11:Program Counter

5-4-3: General Purpose Register Figure 5-12 shows an 8-bit register with loading control at the input. There are 3 instances of this register including Data Register, Address Register and Instruction Register. All of these registers work in similar fashion, the load signal enables loading of data in the respective register. The output of the register is taken from the register. The data is always available at the output without any control signal.

LD_DReg Din_Reg(8)

Reg_8Bit

DOut_Reg(8)

module Reg_8Bit(input [7:0] Din_Reg,input Clk, output [7:0] DOut_Reg,input LD_DReg); reg [7:0]R; assign DOut_Reg=R; always@(posedge Clk) if(LD_DReg) R<=Din_Reg; else R<=R; endmodule

Figure 5-12:Register 8-bit, Used as Instruction, Data and Address Register

5-4-4: Arithmetic Logic Unit Figure 5-13 Show the Code and Diagram for Arithmetic Logical unit. The first always block control the operation of the ALU and the second Always block control the Flags of the ALU. The code for the multiplexers is not given in this section and is left to reader while for memory Xilinx Core generator is used. Xilinx Core generator provides a single port memory for Block RAMS of CLBs.

OpCode_ALU(3)

ALU

DOut_ALU(8)

ShAMT_ALU(2)

Din1_ALU(8) Flag_ALU(3) Din2_ALU(8)

module ALU(input [2:0] OpCode_ALU,output reg[2:0] Flag_ALU,input [1:0] ShAMT_ALU,input [7:0] Din1_ALU,input [7:0] Din2_ALU,output reg [7:0] DOut_ALU); //ALU Operations always@(OpCode_ALU or ShAMT_ALU or Din1_ALU or Din2_ALU)

case(OpCode_ALU) 3'b000:DOut_ALU<=Din1_ALU+Din2_ALU;//add 3'b001:DOut_ALU<=Din1_ALU-Din2_ALU;//sub 3'b010:DOut_ALU<=Din1_ALU*Din2_ALU;//mul 3'b011:DOut_ALU<=Din1_ALU&Din2_ALU;//and 3'b100:DOut_ALU<=Din1_ALU|Din2_ALU;//or 3'b101:DOut_ALU<=~Din1_ALU;//cmp 3'b110:DOut_ALU<=Din1_ALU>>ShAMT_ALU;//slr 3'b111:DOut_ALU<=Din1_ALU<<ShAMT_ALU;//sll endcase ///For Flags always@(Din1_ALU or Din2_ALU or DOut_ALU) begin if(Din1_ALU>Din2_ALU) Flag_ALU[2:1]<=2'b00; else if(Din1_ALU==Din2_ALU) Flag_ALU[2:1]<=2'b01; else if(Din1_ALU<Din2_ALU) Flag_ALU[2:1]<=2'b10; else Flag_ALU[2:1]<=2'b11; if(DOut_ALU==0) Flag_ALU[0]<=1'b1; else Flag_ALU[0]<=1'b0; end endmodule

Figure 5-13:Arithmetic Logic Unit

Since the memory is only 256x8 so BRAM is enough for such a small memory requirement. However in larger memory requirement SRAM is used. This requires either a SRAM core or SRAM controller code which is discussed in latter chapters. The method to use Memory Core generator is described in Laboratory manual and can be practiced by the students. The COE file contains the Program of machine language to be executed on the processor, this file is used as initialization file for core generator. 5-4-5: Top Level Module of Data Path The complete design for Data Path of the Processor is given in Figure 5-14. Two modifications are done in the data path, Enb_RFile and Enb_Mem are added. These signals are used to enable/disable these two

modules. Memory is not part of Data path so it shown as separate module. It is important to consider the sequential and combinational elements. The drives are always wire and does not have storage capabilities unless have register in them.

INC_PC LD_PC RST_PC RW_RFile Add1_RFile Add2_RFile

PC

Register File

BUS_ADD

DATA PATH

Enb_RFile Din_RFile

WRFOut11

WRFOut12

BUS_DATA

Din_Mem

Memory
256x8
Add_Mem

OpCode_ALU

WPCOut

CONTROL UNIT

Flag_ALU ShAMT_ALU

ALU
WALUOut

LD_DReg

DREG
WDROut
DOut_Mem

Data_IM

BUS_ADD

Sel_MData Sel_MAdd

MUX_DATA

BUS_DATA

MUX_ADD

LD_IR Inst

IR AREG

LD_AReg

RW_Mem Enb_Mem

Figure 5-14: Modifications in Data Path (All wires are shown in Italic)

The code of data path given in figure 5-15, connection wires are shown as separate wires after port definition is made.
module DP_RISC8Bit(input INC_PC,input LD_PC,input RST_PC,input RW_RFile, Add2_RFile,input RW_Mem,input [2:0] OpCode_ALU, input [7:0] Add1_RFile,input [7:0]

output [2:0] Flag_ALU,input [1:0] ShAMT_ALU, input

LD_DReg,input [7:0] Data_IM, input [1:0] Sel_MData, input Sel_MAdd,input LD_IR, output [7:0] Inst,input Clk, input LD_AReg, output [7:0] Din_Mem, output [7:0] Add_Mem,input [7:0] DOut_Mem, input Enb_RFile); wire [7:0]BUS_DATA,BUS_ADD; wire [7:0]WRFOut1,WRFOut2,WPCOut,WALUOut,WDROut; assign Din_Mem=WRFOut1; RFile R1(.RW_RFile(RW_RFile),.Add1_RFile(Add1_RFile),.Add2_RFile(Add2_RFile),.Din_RFile(BUS_DATA),

.DOut1_RFile(WRFOut1) ,.DOut2_RFile(WRFOut2),.Clk(Clk),.Enb_RFile(Enb_RFile)); PC ALU P1(.INC_PC(INC_PC),.RST_PC(RST_PC),.LD_PC(LD_PC),.Din_PC(BUS_ADD),.DOut_PC(WPCOut),.Clk(Clk)); A1(.OpCode_ALU(OpCode_ALU),.Flag_ALU(Flag_ALU),.ShAMT_ALU(ShAMT_ALU),.Din1_ALU(WRFOut1),

.Din2_ALU(WRFOut2),.DOut_ALU(WALUOut)); MUX_ADD MA1(.Din1_MADD(DOut_Mem),.Din2_MADD(WPCOut),.Sel_MADD(Sel_MAdd),.DOut_MADD(BUS_ADD)); Reg_8Bit DReg(.Din_Reg(WALUOut),.Clk(Clk),.DOut_Reg(WDROut),.LD_DReg(LD_DReg)); Reg_8Bit AReg(.Din_Reg(BUS_ADD),.Clk(Clk),.DOut_Reg(Add_Mem),.LD_DReg(LD_AReg)); MUX_DATA MD1(.DIn1_MData(WDROut),.DIn2_MData(Data_IM),.DIn3_MData(DOut_Mem),.DIn4_MData(8'dz), .DOut_MData(BUS_DATA),.Sel_MData(Sel_MData)); Reg_8Bit IR(.Din_Reg(BUS_DATA),.Clk(Clk),.DOut_Reg(Inst),.LD_DReg(LD_IR)); endmodule

Figure 5-15:Putting it All together Data Path

All intermediate wires are shown in italic in figure 5-14. The address bus and data bus uses BUS_ADD or BUS_DATA respectively. The interconnection WRFOut1 and WRFOut2 between Register File and ALU. The outputs of Register Program Counter, ALU and Data Register is used by WPCOut,WALUOut and WDROut respectively. There are three instances of Reg_8bit are used in the code Instruction register, data register and address register. However for program counter uses separate module, because it requires special function like increment of program counter.

5-5: Control Unit Design of Processor

In the last section the design of data path was completed. The current section will focus on control unit and its coding. At the end of this section we will design the top level module. The foundation for the control unit is already been laid in the section 5-3 where operations of data path are explained. As a good exercise for the reader try designing the control unit for yourself and then compare the design given in this section. Most of the designs required modifications in data path before we can write code of control unit. Two modifications are done in Figure 5-15 both register file and memory are added with enabled signals. This is done to ensure that both register file and memory dont have any accidental data operations.

Table 5-4: State for ASMD based design

Fetch In the fetch, address of PC is moved to address register. The content pointed by the address register is carried to the instruction register. To achieve all these operations Fetch State is defined. It requires Address and Data Multiplexers selection to take PC data on Address bus and Memory Out data on data bus respectively. The load of Instruction register and Address register must be asserted. Decode In decode the instruction received to the Control Unit is decoded. Program counter is incremented to prepare for next instruction. R Type Execute Two words from Register File are read and passed to ALU. The read addresses and read write signals are required for Register File. The ALU requires OP Code to perform operation on the operands and Write the data into data register. R Type WB The data from the data register is written back to register file. R Type instruction two cycles to perform Operation. Fetch 2 Byte The Address in Program counter is loaded in address register. The state is same as fetch with only difference that Memory out is not loaded in Instruction register. Branch The branch instruction takes the data from the memory pointed by the Address register and store the memory word into program counter. RW Execute The first clock cycle of read and write operation is shared. The addresses for both read and write instruction is stored on the second byte. In the first clock cycle the address is moved from second byte of Memory location to the address register. Read WB The read write back is second cycle of RW executed. In this cycle the data from memory pointed by address register is written in register file. Write WB The Data from register file is written on memory by address pointed by address register.

Table 5-4 show possible states for the ASMD, Figure 5-15 show the modification in data path as required by ASMD.

INC_PC LD_PC RST_PC RW_RFile Add1_RFile Add2_RFile Enb_RFile Din_RFile

PC

Register File

CONTROL UNIT

RW_Mem Enb_Mem OpCode_ALU Flag_ALU ShAMT_ALU

Din_Mem

Memory ALU
Dout_Mem

256x8

LD_DReg

DREG

Add_Mem

Data_IM

Sel_MData Sel_MAdd

MUX_DATA

MUX_ADD

LD_IR Inst LD_AReg

IR

AREG

Figure 5-16: Modifications in Data Path before writing ASMD of the control unit
Figure 5-16 shows the ASMD of the Processor with all states shown in table 5-4. Every instruction will be fetch and decode, after decode the type of instruction defines which will be the next state. For R-Type instruction Execute_Reg and Execute_WB. For Shift type instruction which is SR Type, Flow of R-Type instructions are followed. While for Move Type instruction S_Exec_SR is acquired. All Two bytes instructions S_Fetch2Byte is used. Branch instruction will use S_Branch. The read and write instruction follow common execute cycle. After execute Read and write will use different write back stats.

S_RST
RST_PC->1 LD_PC->0 LD_AReg->0 LD_IR->0 LD_DReg->0 Enb_RFile->0 Enb_Mem->0 INC_PC->0

S_Fetch
Sel_MAdd->1 LD_IR->1 Enb_Mem->1 LD_PC->0
Enb_RFile->0

S_Decode
LD_AReg->1 Sel_MData->2 RST_PC->0
RW_Mem->0

INC_PC->0

DesReg->Inst[4:5] SA->Inst[6:7] OCode->Inst[0:3] LD_AReg->0 Enb_Mem->0

SrcReg->Inst[6:7] IVal->Inst[6:7] INC_PC->1 LD_IR->0 Enb_RFile->0

S_Exec_Reg R-Type
Enb_RFile->1 RW_RFile->1 Add1_RFile->DesReg Add2_RFile->SrcReg OpCode_ALU->OCode LD_DReg->1 INC_PC->0 ShAMT_ALU->SA

S_WB_Reg
LD_Dreg->0 Sel_MData->0 RW_RFile->0 Enb_RFile->1 Add1_RFile->DesReg

S_Exec_SR SR-Type Shift Inst.

Data_IM->IVal Enb_RFile->1 ADD1_RFile->DesReg Sel_MData->1 RW_RFile->0 INC_PC->0

S_Fetch2Byte
Sel_MAdd->1 INC_PC->0 LD_AReg->1

B Type

S_Branch
INC_PC->0 LD_PC->1 Sel_MAdd->0 LD_AReg->0

S_Exec_RW M Type
Sel_MAdd->1 INC_PC->1 LD_AReg->0

S_WB_RD RD HALT
LD_AReg->0
Enb_RFile->1 Sel_MData->2 RW_RFile->0

Add1_RFile->DesReg

INC_PC->0

S_WB_WR WR S_HALT
LD_AReg->0
RW_RFile->1 Enb_RFile->1 RW_Mem->1

Add1_RFile->DesReg Enb_Mem->1 INC_PC->0

Figure 5-17:ASMD of the RISC Processor

5-5-1: Coding Control Unit All States and Instructions are defined as constant in the start and Figure 5-17 shows the Implementation of ASMD shown in figure 5-16. The implementation is orthodox ASMD style from chapter-3.
always@(posedge Clk or posedge RST) if(RST==1) State<=S_RST; else case(State) S_RST:State<=S_FETCH; S_FETCH:State<=S_DECODE; S_DECODE: case(OCode) ADD,SUB,MUL,AND,OR,CMP: State<=S_EXEC_REG;//R-Type Instruction SLR,SLL:State<=S_EXEC_REG;//Shift Type Instruction for SR Type MOV:State<=S_EXEC_SR;//SR Type Mov instruction BRZ,BRNZ,BRLT,JMP: State<=S_BRANCH;//Branch Instruction RD,WR: State<=S_EXEC_RW;///Memory based instruction HALT:State<=S_HALT;//Halt endcase S_EXEC_REG:S_WB_REG; S_EXEC_SR,S_BRANCH,S_WB_REG,S_WB_RD,S_WB_WR:State<=S_FETCH; S_EXEC_RW:if(OCode==RD) State<=S_WB_RD; else if(OCode==WR) State<=S_WB_WR; else State<=S_HALT;//Halt default: State<=S_HALT;//Halt endcase

Figure 5-18:Behavioural Block for State Transition

Figure 5-19 show the signal assignment of State transition reflected in Figure 5-18.

always@(State) case(State) S_RST: begin RST_PC<=1; LD_PC<=0; LD_AReg<=0; LD_IR<=0; LD_DReg<=0; Enb_RFile<=0; Enb_Mem<=0; INC_PC<=0; end S_FETCH: begin Sel_MAdd<=1; LD_AReg<=1; LD_IR<=1; Sel_MData<=2'd2; Enb_Mem<=1; RST_PC<=0; LD_PC<=0; RW_Mem<=0; Enb_RFile<=0; INC_PC<=0; end S_DECODE: begin DesReg<=Inst[5:4]; SrcReg<=Inst[7:6]; SA<=Inst[7:6]; IVal<=Inst[7:6]; OCode<=Inst[3:0]; INC_PC<=1; LD_AReg<=0; LD_IR<=0; Enb_Mem<=0; Enb_RFile<=0; end S_EXEC_REG: begin Enb_RFile<=1; RW_RFile<=1; Add1_RFile<=DesReg; Add2_RFile<=SrcReg; OpCode_ALU<=OCode; LD_DReg<=1; INC_PC<=0; ShAMT_ALU<=SA; end S_WB_REG: begin LD_DReg<=0; Sel_MData<=0; RW_RFile<=0; Enb_RFile<=1; Add1_RFile<=DesReg; end S_EXEC_SR: begin Data_IM<=IVal; Sel_MData<=2'd1; Enb_RFile<=1; RW_RFile<=0; Add1_RFile<=DesReg; INC_PC<=0; end S_BRANCH: begin INC_PC<=0; Sel_MAdd<=0; LD_PC<=1; LD_AR<=1b0; end S_EXEC_RW: begin Sel_MAdd<=1; LD_AReg<=1; INC_PC<=0; end

S_WB_RD: begin LD_AReg<=0; Sel_MData<=2'd2; Enb_RFile<=1; RW_RFile<=0; Add1_RFile<=DesReg; INC_PC<=1; end S_WB_WR: begin LD_AReg<=0; Enb_RFile<=1; RW_RFile<=1; RW_Mem<=1; Add1_RFile<=DesReg; Enb_Mem<=1; INC_PC<=1; end endcase

Figure 5-19:Behavioural Block for Signal Assignment

5-5-2: Top Level Module of Processor The last section of the chapter discusses the top level module of the processor.
module RISC_8Bit(Clk,Rst); wire W_INC_PC,W_LD_PC,W_RST_PC,W_RW_RF,W_RW_Mem,W_E_RF,W_LD_DR,W_LD_IR,W_LD_AR, W_SELA,W_EM; wire [7:0]W_A1_RF,W_A2_RF,W_INT,W_DinM,D_AddM,D_DOutM; wire [2:0]W_OC_ALU,W_F_ALU; wire [1:0]W_SA_ALU,W_DI,W_SELD; CU_RISC8Bit CR1(.INC_PC(W_INC_PC),.LD_PC(W_LD_PC),.RST_PC(W_RST_PC),.RW_RFile(W_RW_RF), .Add1_RFile(W_A1_RF),.Add2_RFile(W_A2_RF),.RW_Mem(W_RW_Mem),.Enb_RFile(W_E_RF),.OpCode_ALU(W_OC_ALU), .Flag_ALU(W_F_ALU),.ShAMT_ALU(W_SA_ALU),.LD_DReg(W_LD_DR),.Data_IM(W_DI),.LD_IR(W_LD_IR), .LD_AReg(W_LD_AR) , .Inst(W_INT),.Sel_MData(W_SELD),.Sel_MAdd(W_SELA),.Enb_Mem(W_EM),.Clk(Clk),.RST(Rst)); DP_RISC8Bit DR(.INC_PC(W_INC_PC), .LD_PC(W_LD_PC), .RST_PC(W_RST_PC), .RW_RFile(W_RW_RF), .Add1_RFile(W_A1_RF), Add2_RFile(W_A2_RF), .RW_Mem(W_RW_Mem), .OpCode_ALU(W_OC_ALU), .Flag_ALU(W_F_ALU),.ShAMT_ALU(W_SA_ALU), .LD_DReg(W_LD_DR), .Data_IM(W_DI), .Sel_MData(W_SELD),.Sel_MAdd(W_SELA), .LD_IR(W_LD_IR),.Inst(), .Clk(Clk),.LD_AReg(W_LD_AR), .Din_Mem(W_DinM), .Add_Mem(D_AddM), .DOut_Mem(D_DOutM),.Enb_RFile(W_E_RF)); Memory M1(.Din_Mem(W_DinM), .Dout_Mem(D_DOutM), .RW_Mem(W_RW_Mem),.Add_Mem(D_AddM), .Clk(Clk),.Enable(W_EM)); endmodule

Figure 5-20:Top Level module of RISC Processor

5-6: Testing and Synchronization of Design

Testing such a large design requires organize pattern of testing, this is good point to share Organize testing techniques. Chapter-14 will investigate SOC testing Techniques; however the current discussion will reflect methodologies from Chapter-14. All testing requires three components.

Exercise Problems
5-1: If the instruction set given in Table 5-1 does not have multiply instruction we would require it using assembly routine. Write Assembly routine to implement multiplication instruction using 15 Instructions given in Table 5-1. 5-2: The processor in Figure 5-16 contain data path having two flags. Modify the flag mechanism and add flagging mechanism with following flags.

C
Carry

AC
Auxiliary Carry

OV
Over Flow

Z
Zero

CP1
Compare-1

CP2
Compare-2

Write Verilog code, behavioral level block for ALU module to implement the flagging Logic. Over Flow is discussed in 6-1-5. 5-3: The process discussed in section 5-3 contains mov instruction to move immediately value into Din_Mem register File. Modify the architecture given in Figure P 5-3 to add a logic to move value from register to register.

RFile

ALU
Data_IM Mem_Out

MUX_DSEL

5-4: The instruction register is passed directly to the control unit and it issues OpCode and Shift amount to ALU, Source and destination address to Register File and determines the type of instruction. Come up with the architecture where only 4-Bit instruction type is passed to the control unit. The source, destination addresses and OpCode are directly passes in the datapath instead of routing through the control unit. Draw the architecture of such configuration. 5-5: Assume that the memory is divided into 3 Partitions Code memory, Data Memory and The Stack. Add two new instructions push and pop. The value to be pushed in the stack or popped form the stack is taken or stored in the register file respectively.
0-199

Code Memory

200-238

Data Memory

239-255

Stack

Push R0

//Push Register R0 into Stack

Pop R0 //Pop Value from the top of the stack into Register R0 Recommend possible changes in data path and control Unit Draw relevant portion of data path only, recommend changes in ASMD of control Unit after Fetch and decode. All other stages are not required.

5-6: Generally the registers in the processor are visible in the assembler. UART transmitter is used to transmitt all values to the computer. Control Unit send all the registers to the computer once halt is encountered in the program. Modify the ASMD to enable UART Transmission once HALT is encountered.

UART_TX

Processor

Assembler

Register File

CONTROL UNIT

ALU

Data_Ready

RST_UART T_Byte

UART_TX

5-7a: Consider Instruction set of 21 instructions given in the table P5-7. There are 16 registers and each register is 16-bit wide. Design Instruction word for 16-Bit architecture. ADD ADDi SUB MUL AND OR XOR ADD R0,R1 ADDi R0,2 SUB R0,R1 MUL R0,R1 AND R0,R1 OR R0,R1 XOR R0,R1 CMP SLL SLR MOV MOVR BRZ BRNZ CMP R0 SLL R0,1 SLR R0,1 MOV R0,3 MOVR R0,R1 BRZ LABEL BRNZ LABEL BRLT BREQ BRG JMP RD WR HALT BRLT LABEL BREQ LABEL BRG LABEL JMP LABEL RD R0,200 WR R0,200 HALT

5-7b : The instruction set given in Pb 5-7a contains two instructions SLL and SLR for shifting operation. Give the mechanism to merge the instructions into single shift instruction which can give shifting in both directions . 5-8a: Section 5-6 defines the retiming of the processor where synchronization of data path and control unit was done by premetive signal assignment. Another way of delaying the state transition of control unit is to insert dummy states to generate no operation, This gives relaxation time for data path to transact. Write the behavioural block for state transition of control unit or draw ASMD to reflect the change through delay states. 5-8b: This problem is extension of pb 5-8a. Another way of synchroniztion of data path and control unit is to make the clock of control unit slow so that it transact accordingly. If control unit of processor is made to move on slow clock what possible complication datapath can present. 5-9: If code and data memory were different, what difference will data path present. What other registers will be required? Give possible modification in ASMD of control Unit? 5-10: Consider mechanism of processor to handle routines/macros in assembly. Generally branches are created towards sub routines. This requires special instruction to create a jump with return. More registers are required to pass argument and to return the value from the register File. The 16x8 register file is so divided that the last four registers can be used to pass four argument. The value is returned into first argument register. If procedure call is not in progress these four register can be used as general purpose registers. A new instruction JR(jump with return address) is added to return after jump. Propose modification in control unit to accommodate this sort of jump. 12 x 8

R0 R1 R2 R3 5-11: The register file given Section 5-3 contains process where consective reads and writes are not

possible. Modify the architecture in a way that data register is not requred. Change the register file which can allow consective reads and write. Add1_RFile

RFile

Add2_RFile

ALU

DReg

MUX_DSEL
5-12:Figure 5-x presents modified Von Neuman architecture where the memory space is shared between code and data. The von Neuman generally have data and address shared. Draw a data path with shared data and address buses. 5-13: If the architecture is 32 bit and memory has each word equal to 1 byte. This means a oe instruction will be stored on 4-Locations in the memory. The branch in this case relative to memory program storage is deceptive. Think a way of achieving this possible type of branch. How to scale a address so that a single branch represent 4-Locations Jump? 5-14a: In 32-Bit architecture PC will represent 232 memory. Similar can be said about AR, Suppose a memory is of 216 location, hwo to ensure that memory cannot exceed 216 address possible location. Think a way that lower left 16 bit only contain zero. 5-14b: The control unit can also be used to prevent PC of exceeding 216 locations. Device a mechanism that control unit can prevent program counter for exceeding 216 Locations. Modify Data Path in a way that it does not allow the address calculation more than the more then code memory.

5-15: The PC counter has control signal INC_PC which increment the program counter by 1. Suppose PC does not have the signal to increment from Control Unit. Redraw the data path to accommodate increment PC using ALU. What possible modification can be done to facilitate the ALU to increment the PC. 5-16: The branching mechanism of process given in Chapter-5 is absolute branching where PC is exactly replaced with the address of branching. Another way of branching is PC relative addressing. For example if PC Is currently at 20 and jump at 4 or 35 is required. Instead of replacing PC with 4 or 36, 16 is added or subtracted from PC respectively. The branching process done by realtive of earlier PC address is called PC relative address. Modify datapath and control unit to make PC relative addressing. 5-24: The multiplication of two 8-bit number can be a product ofa 16-bit. However the data register attached with the ALU is only 8-bit. The architecture given in section 5-4 does not caters for this constriants. The only wat to get out of this problem is to let the programmer know that the result cannot exceed 8-bit. Suggest possible architecture for handling 16-Bit product results.