APPLIED PHYSICS LETTERS

VOLUME 76, NUMBER 16

17 APRIL 2000

Interface trap prole near the band edges at the 4H-SiCSiO2 interface
N. S. Saksa)
Naval Research Laboratory, Code 6813, Washington, DC 20375

S. S. Manib) and A. K. Agarwalc)

Northrop Grumman Corp., Pittsburgh, Pennsylvania 15235

Received 1 November 1999; accepted for publication 18 February 2000 The transconductance of SiC metaloxidesemiconductor eld-effect transistors MOSFETs is typically much lower in devices fabricated on the 4H-SiC polytype compared to 6H. It is believed that this behavior is caused by extreme trapping of inversion electrons due to a higher density of traps D it at the SiC/SiO2 interface in 4H-SiC. Here we present an approach for proling D it versus energy in the band gap using a modied capacitancevoltage technique on large-area MOSFETs. We nd that D it increases towards the conduction band edge E c in both polytypes, and that D it is much higher in 4H- compared to 6H-SiC for devices fabricated in the same process lot. 2000 American Institute of Physics. S0003-69510000516-7

Experimental transconductance reported for SiC metal oxidesemiconductor eld-effect transistors MOSFETs is relatively poor for both 4H- and 6H-SiC polytypes. Furthermore, the transconductance is typically worse on 4H compared to 6H material,1,2 even though 4H-SiC has a higher bulk electron mobility. Poor transconductance in SiC MOSFETs is generally believed to be caused by trapping of inversion layer electrons at traps D it at the SiO2 /SiC interface in both polytypes.37 Recent values reported for D it on 6HSiC are as low as mid-1010 traps/cm2 eV by using a lowtemperature reoxidation process.8 Despite this low D it value, however, the best reported inversion layer mobilities for 6HSiC MOSFETs are typically only about 40100 cm2/V s, which is considerably less than the expected value of about half the bulk mobility ( bulk 300 cm2/V s). Reported inversion layer mobilities for 4H-SiC MOSFETs are even worse, typically 0.125 cm2/V s, despite its higher bulk mobility ( bulk 900 cm2/V s). Recent Hall measurements on 6H-SiC MOS inversion layers reveal substantial electron trapping which is inconsistent with the apparently low D it ( 1 2 1011) in these samples.9 To explain this apparent discrepancy, it has been proposed that D it increases very rapidly near E c . 37 Here we report measurements of D it near both band edges in 4H-SiC MOSFETs using a modied GrayBrown technique.10 We nd that D it does increase dramatically near E c in both SiC polytypes, and that D it near E c is an order of magnitude higher in 4H compared to 6H devices fabricated in the same process lot, consistent with the lower transconductance in 4H. N-channel, nonself-aligned polysilicon gate MOSFETs were fabricated on 4H- and 6H-SiC wafers. The 4H-SiC wafers have a 10-m-thick, lightly doped ( 1 1016/cm3) p-type epitaxial layer grown over a heavily doped p substrate.11 n source and drain regions were created by multiple energy nitrogen implantation to create a box doping prole approximately 0.5 m deep. This implant was
a

Electronic mail: saks@nrl.navy.mil Present address: Sandia National Laboratory, Albuquerque, NM 87185. c Present address: CREE Inc., Durham, NC 27703.
b

annealed uncapped at 1300 C 4H-SiC or 1200 C 6HSiC this was the only intentional process difference between the two SiC polytypes. After a standard RCA clean, a 31 nm gate oxide was grown wet at 1100 C for 3 h, followed by a wet reoxidation at 950 C for 2.5 h to obtain a lower D it . 8 Other details of the fabrication process are described elsewhere.12 Gate capacitance was measured as a function of gate voltage on large area (100 m long 100 m wide) MOSFETs. The MOSFETs were bonded in ceramic packages and measured under vacuum at temperatures from 80 to 570 K. During the CapacitanceVoltage ( C V ) measurements, the MOSFET n source and drain are tied to the p-type substrate. The source and drain act as a source of minority carriers electrons, so that an effective lowfrequency C V curve can be obtained. This is similar to quasistatic C V 13 where a slow direct current dc sweep rate is used, wherein equilibrium is maintained by slow thermal generation of minority carriers. Here, the rate-limiting step is electron conduction in the MOS inversion layer from the source/drain to the center of the MOSFET channel. Since inversion conduction in the SiC MOSFETs is poor, a low 10 Hz frequency was used to minimize the effect of the high inversion layer series resistance. Although both minority and majority carrier densities are in equilibrium with the slowly varying applied dc gate bias, the occupancy of interface traps far from the band edges is not, due to the very wide 3 eV SiC band gap. The thermal emission rate for carriers trapped in midgap interface traps is very long 1016 s at 22 C!. The key to the C V measurement technique here is that equilibrium of the traps is re-established only in strong accumulation or strong inversion when the trapped carriers are removed by recombination with high densities of free carriers in the accumulation/inversion layers which is fast, not by emission which is slow. Thus, although the C V data obtained in these measurements looks like classic low-frequency data, the standard quasistatic analysis13 cannot be applied, since most interface traps are not in equilibrium. Experimental C V results for 4H MOSFET at 20 and
2250 2000 American Institute of Physics

0003-6951/2000/76(16)/2250/3/$17.00

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FIG. 2. C V curves for a 4H-SiC MOSFET from 140 to 200 C.

FIG. 1. Comparison of experimental and theoretical low frequency C V curves at 20 C top and 200 C bottom in a 4H-SiC MOSFET. The total number of interface traps between atband and inversion can be determined from the difference between the experimental and theoretical curves between atband and inversion.

200 C are shown in Fig. 1. Theoretical curves calculated using the known oxide thickness and substrate doping are also shown for comparison. The theoretical curves in Fig. 1 use a atband voltage V fb of 3.0 V which was obtained by matching theory and experiment at 200 C.14 At 20 C, the experimental data looks like a good low-frequency curve. A larger experimental gate voltage swing is required to move from accumulation to inversion compared to theory because of charge in interface traps. Good low-frequency data is also obtained at 200 C, although some distortion is apparent. The average D it in this device can be calculated from the difference between theory and experiment using D itav C ox( V fb V th)/( q E ), where E is the change in surface potential from atband to inversion, C ox is the oxide capacitance, and ( V fb V th) is the difference in gate voltage swing between experimental and theoretical curves from atband to inversion. In Fig. 1 at 200 C, ( V fb V th) 0.31 V and E 2.5 eV. The extracted value for average midgap D itav is reasonably low at 8.5 1010 traps/cm2 eV. Note: for convenience, V th is dened here to occur at the same capacitance as atband. In Fig. 1 at 20 C, this point is about 0.07 eV closer to the conduction band edge than the normal denition of inversion for a MOSFET, s 2 * bulk. C V curves for the same sample at various temperatures are shown in Fig. 2. Both the atband and inversion points move as the temperature changes, but in opposite directions. Gray and Brown demonstrated that this temperature dependence is caused partly by the temperature dependence of the atband capacitance itself, and partly by the changing occupancy of the interface traps which causes a change in the trapped charge. By subtracting the amount of threshold shift due to the theoretical temperature dependence, the remainder can be used to calculate D it( E ) at atband.10 Here we also use analogous changes in the threshold voltage V th to deter-

mine D it( E ) at threshold. Changes in V th can be measured here because MOSFETs are used rather than MOS capacitors. The analysis is essentially the same as at atband: At each temperature, the theoretical capacitance at threshold is calculated and subtracted from the measured shift. D it( E ) at threshold is calculated from the remainder. In this technique, at both atband and threshold, the difference in interfacial trapped charge is calculated from two C V curves at successive temperatures. Therefore, the calculated D it( E ) is independent of unknown constants such xed oxide charge, so long as these values do not depend on temperature. Using this approach, analysis of the C V data in Fig. 2 yields a D it( E ) prole for a 4H-SiC MOSFET as shown in Fig. 3. Similar data for a 6H-SiC MOSFET from the same process lot, cleaned and oxidized at the same time, is also shown in Fig. 3.15 Average midgap D it values for both 4H and 6H samples, obtained at 200 C as discussed earlier, are shown by the dashed lines in Fig. 3. D it is substantially higher near the band edges than the average midgap values. Electron densities in strong inversion range from mid1011 to 1013 e/cm2 depending on gate voltage. If D it is reasonably low ( 1 1011), electron trapping should not materially reduce MOSFET transconductance in strong inversion. However, the important D it values are those at inversion; i.e., near E c . The data in Fig. 3 show that D it( E ) increases dramatically near E c in both polytypes, and that D it is about an order of magnitude worse higher in 4H compared to 6H. This result is consistent with reports that the

FIG. 3. Interface trap density D it( E ) vs energy in the SiC band gap, referenced to the band edges, for 4H-SiC symbols and 6H-SiC solid lines, calculated using GrayBrown analysis. Average midgap values dashed lines are calculated from 200 C data. D it( E ) near E c is much higher in 4Hcompared to 6H-SiC, which is consistent with the lower transconductance typically reported for 4H MOSFETs.

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effective mobility is typically a smaller in 4H compared to 6H MOSFETs, despite the higher bulk mobility in 4H.1,2 In Fig. 3, the integrated density of traps close to E c within 0.2 eV in the 4H sample is 1.0 1013 traps/cm2. Thus, most electrons in the 4H MOS inversion layer will be trapped even at the highest gate biases, leading to a very poor transconductance. Hall Effect measurements on the 6H MOSFETs from the same process lot reported elsewhere9 reveal much less electron trapping ( 1.5 1012 trapped electrons/ cm2, indicating a much better interface in 6H. In Fig. 3, D it near the valence band edge E v shows a broad peak which is similar for both SiC polytypes. D it near E v is only about a factor of 2 higher in 4H compared to 6H-SiC, much less than the difference measured near E c . It has been pointed out that articial peaks in D it near E v in a p-type semiconductor can be obtained from GrayBrown analysis if the traps capture cross-section varies rapidly with energy.16 Indeed, recent measurements of using conductance measurements on n-type 4H-SiC MOS capacitors apparently show a rapid decrease near E c . 17 Also, Gray Brown analysis is not self-consistent because the contribution of interface trap capacitance itself to the theoretical atband capacitance is not taken into account.16 These sources of error could cause the D it peak observed near E v in Fig. 3, although a detailed calculation is beyond the scope of this letter. Finally, both the 4H and 6H data show a sharp minimum in D it( E ) at 0.15 eV below E c . Although this minimum in D it has been reproducibly observed in all 4H- and 6H- SiC MOS devices measured here about six devices, it is not known whether this minimum appears in SiC MOS devices from other process lots. Proling D it( E ) by changing the temperature and using GrayBrown analysis is a relatively insensitive technique and can only be used effectively on samples with high D it . For the samples here, a 10 C change in temperature at 22 C causes only a small change in the surface potential at atband 9 mV. It is therefore very important that any sources of C V instability, such as caused by ionic contamination of the oxide e.g., sodium, be negligible. In order to investigate this possible error source, C V curves were compared for forward and reverse sweep directions of the gate voltage at most measurement temperatures. Bias dependent instabilities should be evident as a C V hysteresis between the two sweep directions at temperatures where the sodium is mobile. No such hysteresis was apparent in any sample reported here up to the highest measurement temperatures. However, samples from other process lots did show signicant hysteresis, indicating problems with contamination, and making these samples useless for Gray Brown analysis. Another effect was also observed which limits the accuracy of these measurements. After C V measurements were made at high temperatures, additional traps were found to be created due to the bias-temperature cycling. Consequently, the maximum measurement temperature was limited to 200 C. This effect is discussed in more detail elsewhere.15 In summary, D it has been proled near the band edges using a modied GrayBrown C V technique on large MOSFETs. This measurement approach has several advantages: it is simple to implement, D it proles are obtained near

both band edges with a single sample, and it is possible to obtain proles very close to the band edges. Perhaps most important, it is possible to obtain D it and mobility data on the same device, which is a powerful advantage in understanding mobility issues. Drawbacks include that MOSFETs are more difcult to fabricate than capacitors, and GrayBrown analysis is relatively insensitive and cannot be used if C V instabilities are present. Also, the technique has inherent errors which limit the techniques accuracy and which need to be evaluated more thoroughly. D it( E ) is found to increase rapidly close to the conduction band edge in 4H-SiC mid-1013 traps/cm2 eV compared to a low average midgap value low 1011 range. This behavior is qualitatively similar to that found previously in 6HSiC, but D it( E ) near E c is much higher in 4H. These results clearly demonstrate that severe electron trapping at the SiC/SiO2 interface is the major factor causing the low transconductance reported for 4H-SiC MOSFETs. The authors thank the staff of the Northrop Grumman Corp., Pittsburgh, PA, for fabricating the samples, M. White and V. Vathulya for growing the gate oxides, and E. Arnold for pointing out Ref. 16. This work was partially supported by the Ofce of Naval Research.

H. Yano, T. Kimoto, H. Matsunami, M. Bassler, and G. Pensl, International Conference on SiC and Related Materials 1999, Research Triangle Park, NC., 1015 Oct. 1999. 2 M. K. Das, M. A. Capano, J. A. Cooper, Jr., and M. R. Melloch, Electronic Materials Conference, Santa Barbara, CA, June 30July 2, 1999. 3 R. Schorner, P. Friedrichs, and D. Peters, IEEE Trans. Electron Devices 46, 533 1999. 4 D. M. Brown, E. Downey, M. Ghezzo, J. Kretchmer, V. Krishnamurthy, W. Hennessy, and G. Michon, Solid-State Electron. 39, 1531 1996. 5 M. K. Das, and J. A. Cooper, Jr., International Conference on SiC and Related Materials 1999, Research Triangle Park, NC, 1015 Oct. 1999. 6 E. Arnold, IEEE Trans. Electron Devices 46, 497 1999. 7 V. V. Afanasev, M. Bassler, G. Pensl, and M. Schulz, Phys. Status Solidi A 162, 321 1997. 8 L. A. Lipkin, D. B. Slater, Jr., and J. W. Palmour, Mater. Forum 264 8, 853 1998. 9 N. S. Saks, S. S. Mani, V. S. Hedge, and A. K. Agarwal, International Conference on SiC and Related Materials 1999, Research Triangle Park, NC, 1015, Oct. 1999. 10 P. V. Gray and D. M. Brown, Appl. Phys. Lett. 8, 31 1966; D. M. Brown and D. V. Gray, J. Electrochem. Soc. 115, 760 1968. 11 Wafers with epitaxial layers were purchased from CREE Research, Research Triangle Park, NC. 12 N. S. Saks, S. S. Mani, A. K. Agarwal, and M. G. Ancona, IEEE Electron Device Lett. 20, 431 1999. 13 M. Kuhn, Solid-State Electron. 13, 873 1970. 14 Because the amount of oxide xed charge is unknown, the atband voltage V fb cannot be known a priori, and V fb must be obtained from experimental data. However, we emphasize that the value extracted here for V fb is not used in, and does not affect, later calculations of D it( E ). 15 N. S. Saks, S. S. Mani, and A. K. Agarwal, International Conference on SiC and Related Materials 1999, Research Triangle Park, NC, 1015 Oct. 1999. 16 M. R. Boudry, Appl. Phys. Lett. 22, 530 1973. 17 M. K. Das and J. A. Cooper, Jr., Purdue University and Lori Lipkin, Cree Research. private communications.