Company Name: Texas Instruments India Pvt Ltd Job Opening: RTL Senior Design Engineer Location: Bangalore

Exp: 2-5 yrs Job Description: Required Basic Qualifications: B.Tech/M.Tech in Electronics Engineering/Electrical Engineering, VLSI Strong Digital logic, Circuit theory fundamentals Good communication and presentation skills and team work. Prior Industry experience in SoC/IP RTL development using Verilog/VHDL. Exposure to SoC architecture and aspects like Clock/Reset/Power Management Strong digital design problem solving and debug skills. Familiarity with simulation tools like NCSIM/VCS Additional Preferred Qualifications: Exposure to other SoC aspects like DFT, timing closure. Expertise in automation using perl/Tcl/shell scripting Primary Responsibilities: SoC/IP RTL development meeting all power/performance/area/schedule (PPAS) goals. Work with worldwide IP provider teams to meet chip requirements. Work closely with Verification/DFT/STA/Physical Design teams. Communicate on daily basis with various teams to ensure that the PPAS goals are met. Simulation debugs. Secondary Responsibilities include one or more of below: Work with other RTL teams to share best practices. Interact with system application teams to understand the specification and end application requirements. Silicon debugs Complex Tasks: SoC designs in TI typically have very tight performance, power, and area targets set by the high-volume high-performance markets, and high configurability for catering to the needs of a wide-variety of target applications. Meeting such conflicting requirements often demands extensive planning and pure innovation along with robust functional verification to ensure products ramp faster. Chips that are being developed in TI India DSP team integrate high performance and power optimized processor cores along with analog and digital IPs that are implemented across TIs sites world-wide. K Veeranjaneyulu PGP/16/144 Section C Page 1

 Candidate Should be able to understand system-level details, have excellent problem solving skills to resolve complex issues as they occur. The RTL engineers responsibilities involve understanding the specification, development/integration of IPs, managing communication with the world-wide IP providers in defining the chip requirements accurately for complex IPs and also ensuring on-time closure of IP dependencies for SoC. The candidate also needs to work with application teams to debug, trouble shoot any of the failures on prototyping environments pre and post silicon.

Management/Organizational Skills: The ability to work across organizational boundaries and also to collaborate well within the team toward fostering team-work and productivity are crucial for this position. The position sometimes expects significant level of interaction with non-India sites in terms of handling/planning external deliverables and adopting common design lows/methodologies that are developed in various other sites. Clearly communicate RTL status, issues, and concerns with various teams along with management. Team and People Skills: Expects excellent team work skills and ability to guide members The position as a SoC RTL engineer requires rigorous interactions with the specifications team, systems engineering team, verification, DFT, STA and the physical design engineers.

Projects and Deliverables: Work on leading edge ARM based SoC to grow TI market share in the Focused End Equipments market Be part of best is class chip team and work tightly coupled with worldwide firmware/systems team to successfully design products to grow small cell radio solution Deliver robust functional silicon. SoC/IP RTL design and release efforts. Debug functional simulation failures and provide RTL fixes. Participate in verification/DFT/timing constraint reviews. Identify areas in the design process that will improve the SoC integration/release activity for SoC. Unique selling features of this position, team, or project: We are a growing team that develops ARM based SoCs in deep sub micron technology (45nm and lower) for portable equipments market. Challenging design projects that push performance, process technology, and integration, as well as demand innovative solutions to complex design issues, in order to maintain and grow the companys status as the market leader in ARM based low-power products. You will be a member of a development team with an open, creative, collaborative, and learning work environment. Decision making, ownership and accountability are held by design

K Veeranjaneyulu PGP/16/144 Section C

Page 2

engineers. We offer the ability to interface with industry experts and work on complete signal chain solutions. The TI India DSP design organization will be responsible for the complete design execution of Single chip solutions for ARM based portable devices, starting from the specifications definition phase closely working with the business team, through the RTL/DFT implementation and verification phases, to synthesis and physical design, all the way to the silicon bring-up and sample delivery. Work environment: Very open environment, flat hierarchies, focused work, ownership of key technologies and IPs, publishing papers and opportunities to participate in defining modeling standards and conferences , working with a very cross functional team involving SW component and integration teams, Design and DV teams, 3P modeling and integration vendors and suppliers, customers, EDA partners etc

Competency:
Management/ Organizational skills:
First Degree:

The ability to work across organizational boundaries and also to collaborate well within the team toward fostering team-work and productivity are crucial for this position. The ability to express own ideas, thoughts, and feelings
Second Degree:

The position sometimes expects significant level of interaction with non-India sites in terms of handling/planning external deliverables and adopting common design lows/methodologies that are developed in various other sites. It requires the person to be proactive in approaching the other sites and proper planning to meet the deadlines.
Third Degree:

Clearly communicate RTL status, issues, and concerns with various teams along with management. Effectively listens in group or one-to-one situations involving distractions, stress, complex information, or when the person speaking is emotional/distraught. Creates/maintains a positive working environment that encourages expression of thoughts, ideas, and feelings. Technical Knowledge: This factor measures the technical expertise, skills and experience required to perform the job. This also measures the training required to perform the job duties. First Degree Demonstrates the ability to Strong analytical, mediation and problem resolution skills. Basic knowledge of people management in the operation industry. SoC designs in TI typically have very tight performance, power, and area targets set by the high-volume highK Veeranjaneyulu PGP/16/144 Section C Page 3

performance markets, and high configurability for catering to the needs of a wide-variety of target applications. Meeting such conflicting requirements often demands extensive planning and pure innovation along with robust functional verification to ensure products ramp faster. Second Degree Use of advances tools and techniques for optimizing the operations process for successfully achieving the operational goals. Should be able to understand system-level details, have excellent problem solving skills to resolve complex issues as they occur. The RTL engineers responsibilities involve understanding the specification, development/integration of IPs, managing communication with the world-wide IP providers in defining the chip requirements accurately for complex IPs and also ensuring on-time closure of IP dependencies for SoC. Third Degree: Demonstrate quantitative decision making, ability to drive business/operations metrics. Participate in defining modeling standards and conferences , working with a very cross functional team involving SW component and integration teams, Design and DV teams and other teams. Interact with system application teams to understand the specification and end application requirements.

K Veeranjaneyulu PGP/16/144 Section C

Page 4