C2020 Assignment

JSIIT
Yusif Suleiman2308-0703-0223
Computer Institute
Kazaure, Jigawa State, Nigeria
Computer Architecture and Data Communication (C2020) Assignment
By
Yusif Suleiman
2308-0703-0223
Supervisor/lecturer:
Mr. Salisu Garba

Date: 12th October, 2012
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Computer Architecture(C2020
JSIIT
Table of Contents
CONTENT
PAGES
Cover ..i
Table of Contents.......ii
Question 1 Fetch and Execute Instruction Cycle.3 Fetch Cycle......3 Execute Cycle Step 1 ..4 Execute Cycle Step 2...4 Question 2 Addressing Format ...5 Zero Addressing Format .....5 One Addressing Format ..6 Two Addressing Format ..6 Three Addressing Format ....7 Question 3 RPN Expression8
Question 4 Data Line, Address Line & Bits Allocated to Op-Code..9 Apple Computer...10 Hp Computer. ..12 Dell Computer..15 References....18
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QUESTION 1.
Instruction, Mov [600], [601], copies number stored in address 600 to address 601. Assume instruction is stored at address 700, show the fetch and execute steps
ANSWER:
THE FETCH AND EXECUTE STEPS
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QUESTION 2
Write the Assembly codes for the expression PO = Q-R/(S+T)*Y-V using Zero, One, Two and Three Addressing Format Machines
ANSWER:
ADDRESSING FORMATS
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QUESTION 3
Provide the RPN for the expression A/(C-D)*B-F/E
ANSWER: RPN Expression for the above value
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QUESTION 4
Give 3 examples of machine, using diagrams, with different number of data channels, address channels and bits allocated to op-code field and contrast the followings:
Number of different commands that the different computers could issue Number of different addressable locations that the computers could access Data transfer rate per fetch cycle for the different computers Length of the instruction register of the different computers.
ANSWER:
The following diagram represents the structure of computer, which shows the Main Memory, CPU and some of the registers located in the CPU. It also symbolize the number of Data Channels, Address Channels and the Bits Allocated in the Instruction Registers, the Op-code and Address fields for the Apple Computer.
Number of commands that Apple Computer could issued is determined by the size of Op-Code fields. This could be obtained by two to the power of n (2n), where n is the number of Bits of the Op-Code fields.
Op-Code = 12Bits Number of different commands Apple Computer could issue = 212 = 4096
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NUMBER OF ADDRESSABLE LOCATIONS

The number of different addressable locations the computers could access is determined by the size of their address fields, this could be attain by two to the power of n (2n), where n is the number of Bits of the Address fields. The determinant n word must e used n = 2n where n refers to size of memory address in bits
Number of addressable locations for Apple Computer is n = 218 = 262144
DATA TRANSFER RATE PER FETCH CYCLE

Data transfer rate per fetch cycle can be determined by knowing the possible length of word to be found in each memory location of the computer main memory. These can be resolved as follows: the size of word is usually known in bits
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Apple Computer Length of word = 512 In computer system, 1 character = 1 byte = 8bits Therefore number of character = 512/8 =64 character/fetch cycle
So Apple Computer could be able to fetch 64 character from main memory to CPU per fetch cycle.
LENGTH OF INSTRUCTION REGISTERS

The length of Instruction register can be obtained by summing the number of bits of OpCode, Address fields and others, including special fields which are employed under certain circumstances. Apple Computer
Apple Computer uses three addressing format Length of IR = 12+18+18 = 12+36 = 48bits
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Hp Computer
The following diagram represents the structure of computer, which shows the Main Memory, CPU and some of the registers located in the CPU. It also symbolize the number of Data Channels, Address Channels and the Bits Allocated in the Instruction Registers, the Op-code and Address fields for the Hp Computer Number of commands that Hp Computer could issued is determined by the size of OpCode fields. This could be obtained by two to the power of n (2n), where n is the number of Bits of the Op-Code fields.
Op-Code = 10Bits Number of different commands Hp Computer could issue = 210 = 1024
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The number of different addressable locations the computers could access is determined by the size of their address fields, this could be attain by two to the power of n (2n), where n is the number of Bits of the Address fields. The determinant n word must e used n=2n where n refers to size of memory address in bits Number of addressable locations for Hp Computer is n = 212 = 4096
DATA TRANSFER RATE PER FETCH CYCLE

Data transfer rate per fetch cycle can be determined by knowing the possible length of word to be found in each memory location of the computer main memory. These can be resolved as follows: the size of word is usually known in bits
Hp Computer Length of word = 128 In computer system, 1 character = 1 byte = 8bits Therefore number of character = 128/8 =16 character/fetch cycle So Hp Computer could be able to fetch 16 character from main memory to CPU per fetch cycle.

The length of Instruction register can be obtained by summing the number of bits of OpCode, Address fields and others, including special fields which are employed under certain circumstances. Hp Computer
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Hp Computer uses one addressing format Length of IR = 10+12 = 22bits
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Dell Computer
The following diagram represents the structure of computer, which shows the Main Memory, CPU and some of the registers located in the CPU. It also symbolize the number of Data Channels, Address Channels and the Bits Allocated in the Instruction Registers, the Op-code and Address fields for the Dell Computer Number of commands that Dell Computer could issued is determined by the size of OpCode fields. This could be obtained by two to the power of n (2n), where n is the number of Bits of the Op-Code fields.
Op-Code = 8Bits Number of different commands Dell Computer could issue = 28 = 256
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The number of different addressable locations the computers could access is determined by the size of their address fields, this could be attain by two to the power of n (2n), where n is the number of Bits of the Address fields. The determinant n word must e used n=2n where n refers to size of memory address in bits Number of addressable locations for Dell Computer is n = 216 = 65536
DATA TRANSFER INFORMATION Data transfer rate per fetch cycle can be determined by knowing the possible length of word to be found in each memory location of the computer main memory. These can be resolved as follows: the size of word is usually known in bits
Dell Computer Length of word = 256 In computer system, 1 character = 1 byte = 8bits Therefore number of character = 256/8 =32 character/fetch cycle So Dell Computer could be able to fetch 32 character from main memory to CPU per fetch cycle.

The length of Instruction register can be obtained by summing the number of bits of OpCode, Address fields and others, including special fields which are employed under certain circumstances. Dell Computer
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Dell Computer uses two addressing format Length of IR = 8+16+16 = 10+32 = 42bits
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REFERENCE
1. John L. Hennessy, David A. Petterson, (2010) Computer Architecture: A Quantitative Approach, 4th Edition Paper 2. Informatics holding, (2006) Computer Architecture and Data
Communication(C2020), Global Business Unit, Higher Education Informatics Holdings. 3. Lan Sommerville, (2009) Computer Architecture: Pearson 9th Edition 4. Wikipedia 2012, the Free Encyclopedia on Computer Architecture and Data Communication. www.en.wikipedia.org/wiki/computer_architecture 5. Paul A. Carter. (2001) PC Assembly Language
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JSIIT

Computer Architecture and Data Communication (C2020) Assignment

Mr. Salisu Garba

THE FETCH AND EXECUTE STEPS

ANSWER: RPN Expression for the above value

NUMBER OF ADDRESSABLE LOCATIONS

Number of addressable locations for Apple Computer is n = 218 = 262144

DATA TRANSFER RATE PER FETCH CYCLE

LENGTH OF INSTRUCTION REGISTERS

DATA TRANSFER RATE PER FETCH CYCLE

LENGTH OF INSTRUCTION REGISTERS

Hp Computer uses one addressing format Length of IR = 10+12 = 22bits

LENGTH OF INSTRUCTION REGISTERS

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