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Features
Generates the System Clock For CMOS or NMOS Microprocessors Up to 25MHz Operation Uses a Parallel Mode Crystal Circuit or External Frequency Source Provides Ready Synchronization Generates System Reset Output From Schmitt Trigger Input TTL Compatible Inputs/Outputs Very Low Power Consumption Single 5V Power Supply Operating Temperature Ranges - C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C - I82C84A . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C - M82C84A . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER CP82C84A CP82C84AZ (See Note) IP82C84A CS82C84A CS82C84AZ (Note) PART MARKING CP82C84A CP82C84AZ IP82C84A CS82C84A CS82C84AZ TEMP. RANGE (C) 0 to +70 0 to +70 -40 to +85 0 to +70 0 to +70 0 to +70 PACKAGE 18 Ld PDIP 18 Ld PDIP* (Pb-free) 18 Ld PDIP 20 Ld PLCC 20 Ld PLCC (Pb-free) PKG. DWG. # E18.3 E18.3 E18.3 N20.35 N20.35
Pinouts
CSYNC PCLK AEN1 RDY1 READY RDY2 AEN2 CLK GND
CS82C84AZ96 CS82C84AZ (Note) IS82C84A CD82C84A ID82C84A MD82C84A/B 8406801VA MR82C84A/B 84068012A IS82C84A CD82C84A ID82C84A MD82C84A/B 8406801VA MR82C84A/B 84068012A
N20.35 20 Ld PLCC Tape and Reel (Pb-free) 20 Ld PLCC N20.35 18 Ld CERDIP F18.3 18 Ld CERDIP F18.3
PCLK
AEN1
VCC 20
-55 to +125 20 Pad CLCC J20.A -55 to +125 20 Pad CLCC J20.A SMD#
RDY1 READY RDY2 AEN2 NC 4 5 6 7 8
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
9 CLK
10 GND
11 RESET
12 RES
13 OSC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1997, 2002, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X1
CSYNC
D CK
10 RESET 12 OSC
13 14 1 4 3 6 7 15 CK D Q FF1
3 SYNC
2 SYNC
2 PCLK
8 CLK
CK 5 D Q FF2
READY
LOGICAL 1 External Clock Normal Bus Ready Address Disabled 1 Stage Ready Synchronization
LOGICAL 0 Crystal Drive Reset Bus Not Ready Address Enable 2 Stage Ready Synchronization
4, 6
15
5 17, 16 13
O IO I
EFI
14
CLK
2 12 11
O O I
RESET CSYNC
10 1
O I
9 18
1. If the crystal inputs are not used X1 must be tied to VCC or GND and X2 should be left open.
Clock Outputs
The CLK output is a 33% duty cycle clock driver designed to drive the 80C86, 80C88 processors directly. PCLK is a peripheral clock signal whose output frequency is 1/2 that of CLK. PCLK has a 50% duty cycle.
Reset Logic
The reset logic provides a Schmitt trigger input (RES) and a synchronizing flip-flop to generate the reset timing. The reset signal is synchronized to the falling edge of CLK. A simple RC network can be used to provide power-on reset by utilizing this function of the 82C84A.
READY Synchronization
Two READY input (RDY1, RDY2) are provided to accommodate two system busses. Each input has a qualifier (AEN1 and AEN2, respectively). The AEN signals validate their respective RDY signals. If a Multi-Master system is not being used the AEN pin should be tied LOW. Synchronization is required for all asynchronous active-going edges of either RDY input to guarantee that the RDY setup and hold times are met. Inactive-going edges of RDY in normally ready systems do not require synchronization but must satisfy RDY setup and hold as a matter of proper system design. The ASYNC input defines two modes of READY synchronization operation. When ASYNC is LOW, two stages of synchronization are provided for active READY input signals. Positive-going asynchronous READY inputs will first be synchronized to flipflop one of the rising edge of CLK (requiring a setup time tR1VCH) and the synchronized to flip-flop two at the next falling edge of CLK, after which time the READY output will go active (HIGH). Negative-going asynchronous READY inputs will be synchronized directly to flip-flop two at the falling edge of CLK, after which the READY output will go inactive. This mode of operation is intended for use by asynchronous (normally not ready) devices in the system which cannot be guaranteed by design to meet the required RDY setup timing, TR1VCL, on each bus cycle. When ASYNC is high or left open, the first READY flip-flop is bypassed in the READY synchronization logic. READY inputs are synchronized by flip-flop two on the falling edge of CLK before they are presented to the processor. This mode is available for synchronous devices that can be guaranteed to meet the required RDY setup time. ASYNC can be changed on every bus cycle to select the appropriate mode of synchronization for each device in the system.
matches the load capacitance as specified by the crystal manufacturer. This ensures operation within the frequency tolerance specified by the crystal manufacturer. Clock Generator The clock generator consists of a synchronous divide-bythree counter with a special clear input that inhibits the counting. This clear input (CSYNC) allows the output clock to be synchronized with an external event (such as another 82C84A clock). It is necessary to synchronize the CSYNC input to the EFI clock external to the 82C84A. This is accomplished with two flip-flops. (See Figure 1). The counter output is a 33% duty cycle clock at one-third the input frequency.
NOTE: The F/C input is a strapping pin that selects either the crystal oscillator or the EFI input as the clock for the 3 counter. If the EFI input is selected as the clock source, the oscillator section can be used independently for another clock source. Output is taken from OSC.
82C84A
>
>
(TO OTHER 82C84As)
NOTE: If EFI input is used, then crystal input X1 must be tied to VCC or GND and X2 should be left open. If the crystal inputs are used, then EFI should be tied to VCC or GND. FIGURE 1. CSYNC SYNCHRONIZATION
82C84A
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance. . . . . . . . . . . . . . . . . JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 80 20 CLCC Package . . . . . . . . . . . . . . . . . . 95 28 PDIP Package* . . . . . . . . . . . . . . . . . . 85 N/A PLCC Package. . . . . . . . . . . . . . . . . . . 85 N/A Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Max Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+300oC (PLCC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC I82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC M82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Gates
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Capacitance TA = +25oC
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance TYPICAL 10 15 UNITS pF pF TEST CONDITIONS FREQ = 1MHz, all measurements are referenced to device GND
82C84A
AC Electrical Specifications VCC = +5V 10%,
TA = 0oC to +70oC (C82C84A), TA = -40oC to +85oC (I82C84A), TA = -55oC to +125oC (M82C84A) LIMITS SYMBOL TIMING REQUIREMENTS (1) (2) (3) TEHEL TELEH TELEL External Frequency HIGH Time External Frequency LOW Time EFI Period XTAL Frequency (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) TR2VCL TR1VCH TR1VCL TCLR1X TAYVCL TCLAYX TA1VR1V TCLA1X TYHEH TEHYL TYHYL TI1HCL TCLI1H RDY1, RDY2 Active Setup to CLK RDY1, RDY2 Active Setup to CLK RDY1, RDY2 Inactive Setup to CLK RDY1, RDY2 Hold to CLK ASYNC Setup to CLK ASYNC Hold to CLK AEN1, AEN2 Setup to RDY1, RDY2 AEN1, AEN2 Hold to CLK CSYNC Setup to EFI CSYNC Hold to EFI CSYNC Width RES Setup to CLK RES Hold to CLK 13 13 36 2.4 35 35 35 0 50 0 15 0 20 20 2 TELEL 65 20 25 ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Note 3 Note 3 Note 2 ASYNC = HIGH ASYNC = LOW 90%-90% VIN 10%-10% VIN PARAMETER MIN MAX UNITS (NOTE 1) TEST CONDITIONS
TIMING RESPONSES (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) NOTES: 1. Tested as follows: f = 2.4MHz, VIH = 2.6V, VIL = 0.4V, CL = 50pF, VOH 1.5V, VOL 1.5V, unless otherwise specified. RES and F/C must switch between 0.4V and VCC -0.4V. Input rise and fall times driven at 1ns/V. VIL VIL (max) - 0.4V for CSYNC pin. VCC = 4.5V and 5.5V. 2. Tested using EFI or X1 input pin. 3. Setup and hold necessary only to guarantee recognition at next clock. 4. Applies only to T2 states. 5. Applies only to T3 TW states. 6. Tested with EFI input frequency = 4.2MHz. TCLCL TCHCL TCLCH TCH1CH2 TCL2CL1 TPHPL TPLPH TRYLCL TRYHCH TCLIL TCLPH TCLPL TOLCH TOLCL CLK Cycle Period CLK HIGH Time CLK LOW Time CLK Rise or Fall Time PCLK HIGH Time PCLK LOW Time Ready Inactive to CLK (See Note 4) Ready Active to CLK (See Note 3) CLK to Reset Delay CLK to PCLK HIGH Delay CLK to PCLK LOW Delay OSC to CLK HIGH Delay OSC to CLK LOW Delay 125 (1/3 TCLCL) +2.0 (2/3 TCLCL) -15.0 TCLCL-20 TCLCL-20 -8 (2/3 TCLCL) -15.0 -5 2 10 40 22 22 22 35 ns ns ns ns ns ns ns ns ns ns ns ns ns Note 6 Note 6 Note 6 1.0V to 3.0V Note 6 Note 6 Note 4 Note 5
PCLK
(13) tEHYL
CSYNC
RES RESET
I O
(26) tCLIL
NOTE:
All timing measurements are made at 1.5V, unless otherwise noted. FIGURE 2. WAVEFORMS FOR CLOCKS AND RESETS SIGNALS
CLK (7) tCLR1X tR1VCH (5) RDY1, 2 (10) tA1VR1V AEN1, 2 tAYVCL (8) tCLAYX READY (9) (25) tRYHCH tCLA1X (11) tCLR1X (7) tR1VCL (6)
ASYNC
(24) tRYLCL
CLK tCLR1X RDY 1, 2 tA1VRIV AEN1, 2 (8) ASYNC tCLAYX READY (9) (25) tRYHCH (24) tRYLCL tAYVCL tCLA1X (11) (10) tCLR1X (7) (7) (4) tR1VCL tR1VCL (6)
CL (SEE NOTE 3)
NOTES: 1. CL =100pF for CLK output. 2. CL = 50pF for all outputs except CLK. 3. CL = Includes probe and jig capacitance. FIGURE 5. TEST LOAD MEASUREMENT CONDITIONS
X1 C1 X2 C2 F/C CSYNC
CLK
EF1
CLK
F/C
CSYNC
VCC AEN1 C1 24MHz C2 PULSE GENERATOR TRIGGER X2 X1 READY LOAD (SEE NOTE 2) TRIGGER PULSE GENERATOR CLK LOAD (SEE NOTE 1) PULSE GENERATOR VCC F/C AEN1 RDY2 READY AEN2 CSYNC LOAD (SEE NOTE 2) EF1 CLK LOAD (SEE NOTE 1)
OSC
NOTE:
Input test signals must switch between VIL (maximum) -0.4V and VIH (minimum) +0.4V. RES and F/C must switch between 0.4V and VCC -0.4V. Input rise and fall times driven at 1ns/V. VIL VIL (max) -0.4V for CSYNC pin. VCC -4.5V and 5.5V.
MR82C84A CLCC
VCC VCC / 2 C1
F6
F9
R4
R4
R4
3 F5 VCC / 2 F7 F8 OPEN R4 R4 R4 R4 4 5 6 7 8 9
10 11 12 13
R4
R4
R4 F12
VCC / 2
VCC / 2
NOTES: VCC = 5.5V 0.5V, GND = 0V. VIH = 4.5V 10%. VIL = -0.2 to 0.4V. R1 = 47k, 5%. R2 = 10k, 5%. R3 = 2.2k, 5%. R4 = 1.2k, 5%. C1 = 0.01F (minimum). F0 = 100kHz 10%. F1 = F0/2, F2 = F1/2, . . . F12 = F11/2.
10
VCC / 2
R4
R4
F0
X2 RDY1
ASYNC READY
RDY2
EFI
AEN2
F/C
CLK
GND
RESET
RES
OSC
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN2974.3 December 6, 2005