IMPLEMENTATION OF FPGA-BASED ANN FOR CHARACTER RECOGNITION

LEE YEE ANN

SCHOOL OF COMPUTER AND COMMUNICATION ENGINEERING UNIVERSITI MALAYSIA PERLIS 2013

IMPLEMENTATION OF FPGA-BASED ANN FOR CHARACTER RECOGNITION

by

LEE YEE ANN

Report submitted in partial fulfilment of requirements for degree of Bachelor of Engineering (Hons.) (Computer Network Engineering)

MAY 2013

ACKNOWLEDGEMENT

First of all I would like the express my gratitude to God for giving me this chance to study here in UniMAP and to be able to complete this FPGA implementation of ANN for character recognition project as my final year project. I would also like to thank my project supervisor, Dr. PhakLen EhKan, from the bottom of my heart for his endless encouragement, help, support and guidance throughout the duration of implementing this final year project. His guidance on how to execute this project, and how to write an academic and engineering report was extremely helpful and is very useful for my future. Next, my sincere appreciation goes to Universiti Malaysia Perlis and the School of Computer and Communication Engineering for giving me the opportunity to further my study in this very university. I also wish to extend my token of appreciation to all the lecturers, teaching engineers, and other staffs of the School of Computer and Communication Engineering for the knowledge and experience I gained throughout the years I had been studying here. Also not to forget, millions of thank to my course-mates and all friends, for the experience, care and supports they had given me all the time. Last but not least, my love and appreciation to my loving parents, siblings and all my family members for the love, support, and care they had showered onto myself.

ii

APPROVAL AND DECLARATION SHEET

This project report titled Implementation of FPGA-based ANN for Character Recognition was prepared and submitted by Lee Yee Ann (Matrix Number: 101230415) and has been found satisfactory in terms of scope, quality and presentation as partial fulfillment of the requirement for the Bachelor of Engineering (Hons.) (Computer Network Engineering) in Universiti Malaysia Perlis (UniMAP).

Checked and Approved by

________________________ (PhakLen EhKan) Project Supervisor

School of Computer and Communication Engineering Universiti Malaysia Perlis

May 2013

iii

PELAKSANAAN RANGKAIAN NEURON TIRUAN MENGGUNAKAN FPGA BAGI PENGECAMAN AKSARA ABSTRAK

Projek ini merupakan satu titik permulaan untuk mempelajari rangkaian neural buatan (ANN). Projek ini menyingkap satu pendekatan untuk pelaksanaan ANN berasaskan perkakasan dengan menggunakan FPGA. Bagi menunjukkan salah satu fungsi ANN berasaskan FPGA ini, ANN tersebut dilatih untuk mengecam sehingga 16 corak aksara dalam grid 44. Projek ini dibangunkan menggunakan bahasa VHDL dan dikompil menggunakan perisian Altera QuartusII. Fail-fail yang dihasilkan selepas dikompil kemudian diprogram ke dalam peranti FPGA Altera CycloneII yang terdapat di atas kit pembelajaran Altera DE2. Di dalam projek ini, ANN tersebut direka sebagai rangkaian neuron 3 lapis. ANN tersebut direka untuk belajar menggunakan algoritma perambatan ke belakang ("backward propagation"). Projek ini juga direkabentuk agar mengandungi satu penyelia latihan yang akan melatih ANN tersebut untuk mengecam 16 corak aksara yang telah ditentukan. Penyelia latihan ini turut bertanggungjawab untuk membaca masukan daripada pengguna, menghantar nilai masukan tersebut kepada ANN untuk diproses, menerima keluaran daripada ANN dan mentafsir keluaran tersebut. Sebanyak 16 suis digunakan sebagai masukan daripada pengguna manakala keluaran daripada sistem ini dipaparkan pada paparan LCD. Projek ini membuahkan hasil yang memberangsangkan apabila ANN tersebut dapat mengecam semua 16 aksara yang dilatih. Namun ANN tersebut gagal untuk mengecam beberapa corak aksara yang tidak termasuk dalam latihan pengecaman. Secara keseluruhannya, projek ini menunjukkan kemampuan dan kemungkinan pelaksanaan ANN berasakan perkakasan serta kemungkinan dan kemampuan VHDL dan FPGA dalam penyelidikan dan pembangunan prototaip sistem-sistem baru.

iv

ABSTRACT

This project can be seen as a starting point for learning artificial neural network(ANN). It explores an approach of hardware based implementation of ANN using FPGA. To demonstrate the functionality of the FPGA implementation of ANN, the ANN is trained to recognise up to 16 character patterns on a 44 grid. The development of this project is done by using VHDL and compiled using Altera QuartusII software. The resulting design files is programmed into the Altera CycloneII FPGA on the Altera DE2 development and education board. In this project, the ANN is designed to be a 3-layer feed-forward neural network. The ANN learns by applying the backward propagation (BP) algorithm. The design also include a training supervisor that trains the ANN to recognise the 16 predefined characters. The training supervisor will also read user's input, send the input to the ANN for processing, read the ANN's output and interpret the output from the ANN. Sixteen toggle switches are used as inputs while the output is displayed on LCD. The result is promising as the ANN is able to recognise all 16 training characters pattern. However the ANN fails to properly recognise several character patterns which it was not included in the training. In overall, this project shows the ability and the endless possibilities of hardware based implementation of ANN, and the infinite possibility of developing and prototyping of new systems using VHDL and FPGA.

TABLE OF CONTENTS

Page ACKNOWLEDGEMENT APPROVAL AND DECLARATION SHEET ABSTRAK ABSTRACT TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES LIST OF ABBREVIATIONS ii iii iv v vi ix x xi

CHAPTER 1 INTRODUCTION 1.1 1.2 1.3 1.4 1.5 1.6 Introduction Problem Statement Objectives Contribution Scope of Study Conclusion

1 1 2 3 4 4 4

CHAPTER 2 LITERATURE REVIEW 2.1 2.2 Introduction Background 2.2.1 2.2.2 2.2.3 2.3 Biological Neuron Artificial Neural Network ANN Learning Algorithm: Back-Propagation Algorithm

6 6 6 7 9 12 13 vi

Development Tools

2.3.1 2.3.2 2.3.3 2.4 2.5 2.4.1

Field-Programmable Gate Array Altera QuartusII Altera DE2 Development & Education Board

13 15 16 17 19

Very High Speed Integrated Circuit Hardware Description Language 14

Hardware Components Conclusion

CHAPTER 3 METHODOLOGY 3.1 3.2 Introduction Project Phases 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.9 3.4 Project Study Planning the Architecture, Algorithm, and Learning Rule of the ANN on FPGA Develop the VHDL Code in Altera QuartusII Software Perform Simulation on Altera QuartusII Software Download the VHDL Code onto Altera DE2 Development Board Train the ANN for Character Recognition Application Deploy the ANN on Actual Data for Character Recognition Data Collection and Analysis Data Presentation Artificial Neural Network Block ANN Training Supervisor Block Pseudo-Random Number Generator Block Floating Point Processor Block SRAM Driver Block LCD Controller Block LCD Driver Block User Input Devices Output Devices

21 21 21 21 22 23 23 23 23 24 24 24 24 24 25 26 26 26 26 27 27 27 27 28 vii

Functional Blocks

3.3.10 Memory Devices Conclusion

CHAPTER 4 RESULT AND DISCUSSION 4.1 4.2 4.3 4.4 4.5 Introduction Top Level Entity 4.2.1 Result Discussion Conclusion FPGA Device's Resources Used

29 29 29 29 31 34 37

CHAPTER 5 CONCLUSION 5.1 5.2 5.3 5.4 Introduction Conclusion Future Works Potential Commercialisation

38 38 38 39 39

REFERENCES

40

APPENDICES Appendix A Appendix B Appendix C 42 48 49

viii

LIST OF TABLES

Table No. 4.1

Table Title Character Pattern and Its Expected Output

Page 31

ix

LIST OF FIGURES

Figure No. 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3.1 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11

Figure Title A Biological Neuron Cell A Node of the Artificial Neural Network Single Layer ANN Small Multi-Layer ANN Complex Multi-Layer ANN Altera QuartusII Web Edition Software Version 9.1 SP2 Altera DE2 Development & Education Board Layout of Altera DE2 Development & Education Board Development Flowchart for FPGA Implementation of ANN for Character Recognition Synthesised Top-level RTL Circuit Project Compilation Report on Altera QuartusII System Output During Initialisation System Output During ANN Training Phase System Output During Running Mode System Output for Input A System Output for Input F System Output for Input Z System Output for Input Similar to C System Output for Input C System Output for Input D

Page 7 9 10 10 11 16 18 18 22 30 30 32 32 33 33 34 34 36 36 36

LIST OF ABBREVIATIONS

AI ANN ASIC BP CAD CPLD CPU FPGA HDL IC IDE IEEE LCD LFSR NN SRAM VHDL VHSIC

Artificial Intelligence Artificial Neural Network Application-Specific Integrated Circuit Back Propagation Computer Aided Drafting Complex Programmable Logic Device Central Processing Unit Field-Programmable Gate Array Hardware Description Language Integrated Circuit Integrated Development Environment Institute of Electrical and Electronic Engineers Liquid Crystal Display Linear Feedback Shift Register Neural Network Static Random Access Memory VHSIC Hardware Description Language Very High Speed Integrated Circuit

xi

CHAPTER 1

INTRODUCTION

1.1

Introduction

The human brain is the most complex system of the human body. Consisting of billions of neurons, the brain is capable of performing extraordinary tasks. The brain is generally accepted as the CPU that controls every function performed by the human body similar to the processor or CPU of a computer system. Researchers had been studying how the brain functions and had been trying to imitate the brain's operation to be used for processing complex information and to perform some processing that is tedious for a general purpose processor to process. The desire to imitate the functions of the human brain fuelled the development of ANN. The basic model of ANN first emerged back in 1943 when McCulloch and Pitts developed the computational model of NN based on mathematics and algorithms [1-2]. Their works paved the way to more research and development of ANN. Today, ANN is implemented for the purposes of AI, pattern recognition, and forecasting of future events. However, most of ANN implementations today is based on software that runs on top of a typical computer system. This limits the true capabilities of ANN as the actual processing is done by the processor of the computer system running the ANN software. Hardware implementation of ANN does exist, but the number is limited, because it is complex and complicated. 1

This project is aimed to implement an ANN on FPGA. These include the basic functional structure and architecture of ANN, the algorithms to run the ANN and the learning rules to train the ANN to produce the expected result. In order to demonstrate the operation of the ANN implemented on the FPGA, the system will be trained to recognise certain characters. Besides, the history of ANN will briefly be explored, the basic function, building block, and the algorithm of ANN will be explained, and all of these will be implemented using VHDL and programmed into an FPGA device. 1.2 Problem Statement

The ANN is complicated and complex to be implemented. It involves modelling the function of biological neuron, developing an algorithm for the ANN to function, and to train the ANN to perform its tasks accordingly. Since its initial model by McCulloch and Pitts in 1940's, the research and development of ANN had seen a tremendous progress. The ANN has been widely implemented, however, the current implementations of ANN is mostly software based. This limits the actual capabilities of the ANN as the actual processing is done by the conventional general-purpose processor of the computer system of which the ANN is running on. Furthermore, the ANN is running as a software that run on top of another software (the operating system) of the computer system. Thus this software based implementation of ANN significantly reduced the processing speed as compared to implementation of the ANN directly on hardware which will make it possible to fully harness the fast processing speed of ANN. Even though the ANN had been implemented in hardware before, the total number of hardware based implementations of ANN is limited as compared to the software based implementations. This is because of the complexity of the ANN itself and the complexity of the resulting circuit when the ANN is to be constructed using hardware devices. For practicality, it is more ideal for the ANN to be constructed on a single chip. This again posed another problem as the development of application specific integrated circuit (ASIC) is extremely costly. 2

Hardware implementation of ANN using ASIC faced another issue due to the high cost that came from the development of the complex ANN circuit, the process to produce the IC, and the lack of demand for ASIC based ANN devices. Furthermore, ASIC based ANN is application specific and cannot be reconfigured for other purposes. This is where FPGA based implementation of ANN comes into perspective. Previously, the FPGA was not seriously considered as the hardware base for implementation of ANN mainly due to its poor performance in yesteryears, but the advancement in FPGA technologies nowadays made ANN implementation on FPGA possible. Moreover, despite the FPGA has considerably inferior performance than ASIC, the flexibility offered by FPGA made it better choice for small-scale implementation of ANN, and it is also possible to reconfigure the FPGA according to the ANN to be implemented. Digital systems require an algorithm or some other methods to recognise characters. Human beings are familiar with recognition tasks such as recognition of characters. These characters may be in the form of written characters that form a part of a string of text to convey information. However to a digital system, this task is not as easy as it seems. The system has to convert the character information into string of 0's and 1's for further processing. Then this string of binary information has to be processed using certain processor running some algorithms. There are many algorithms or methods implemented for character recognition. The use of ANN is one of the method used for character recognition. 1.3 Objectives

The objectives of this project include: To study and review the existing ANN structure, architecture, learning algorithms, and learning rules. To develop the VHDL code to implement the ANN. To download the VHDL code of the ANN to the Altera CycloneII FPGA on the Altera DE2 Development and Education board. To implement the FPGA based ANN for character recognition application and to be able recognise a number of characters. 3

 1.4

To compare the output from the ANN with the actual result. Contribution

This research will introduce a new hardware based implementation of ANN and also a new FPGA architecture for implementing an ANN. The implementation of ANN on hardware as in FPGA is expected to overcome the slower processing speed of current software based implementation of ANN. This project will also introduce an application of ANN such as character recognition. 1.5 Scope of Study

This research is limited to the following scope of study. 1.6 The development of the ANN architecture will be done using VHDL. The learning algorithm to be implemented for the FPGA implementation of ANN is based on a slightly modified BP algorithm. The ANN will be trained and applied for character recognition. Conclusion

This report will cover the project of FPGA implementation of ANN for character recognition. In the end of the project, it is hoped that the project is a success and this project will pave a new way, and provide a better perspective of ANN implementation on hardware, especially on FPGA. Basically this project report is divided into 5 chapters. Chapter 1 will introduce the ANN, the current implementation of ANN, and the implementation of ANN on a FPGA device. The problem that paved the way for this project is explored, and the overall objective and scope of the project is presented. The possible contribution of this project is also mentioned. Chapter 2 will introduce the structure of of biological neuron, the basic of ANN 4

and its learning algorithm, the HDL used in this project, and the FPGA. This chapter also explore the related works regarding this project and the tools used throughout the project. Chapter 3 will explain the steps taken to implement the ANN on FPGA device and to apply the developed ANN for character recognition. Chapter 4 demonstrates the result from the project. The result is analysed and compared to the desired result. Chapter 5 concludes the whole project and provides a few things that can be improved concerning the project in the future.

CHAPTER 2

LITERATURE REVIEW

2.1

Introduction

This chapter aims to provide basic information about the project. The chapter starts by introducing the terminologies such as the biological neuron, ANN, FPGA, and VHDL. These terms is discussed as how it related with the project. Next, the development tool used throughout the project is introduced and discussed together with the FPGA development board of where the ANN is to be implemented. 2.2 Background

AI aims to make machines and robots to be able function without relying too much on human interactions. It is a vision for most researchers to make machines and robots to think on their own when they are operating. An approach to achieve AI is by the use of algorithms that was carefully planned will deal with any problem that might arise when the machines and robots are operating. This approach is tedious, but when more researchers developed more algorithms and the size of memory contained in the robots and machines increases over time, engineers are able to load more of these algorithms into these devices memory so that it can function on its own.

Another approach that was implemented to achieve AI is Fuzzy Logic. Fuzzy logic relies on logic processing that contain many values instead of traditional true-false logic. Another approach of AI which is the highlight in this project is called ANN. The vision of ANN is to imitate the function of biological brain. 2.2.1 Biological Neuron The ANN is a mathematical/computational model that was inspired by actual neuron of the nervous system of animals. The nervous system of human is make up of billions of neurons or nerve cells. These cells are connected with each other by synapses and there are trillions of synapses in the whole nervous system.

Figure 2.1: A Biological Neuron Cell [3] Figure 2.1 shows a typical biological neuron cell. The neuron cell consists of the soma, axon and dendrites. The soma is the cell body of the neuron that contains, like most other cells, a nucleus which controls the function and operations of the cell, mitochondria, and other organelles. The neuron has a long extension that extend out from the soma which is the axon. The axon carries signals out from the soma to other neurons. At the end of the axon are terminals that connects to the dendrites of other neurons. Dendrites are the many short extensions that branch out from the soma. These

dendrites are signal receivers that carry signals from other neuron cells into the soma. The axons and dendrites are not directly connected or coupled together, instead the signal carried by axon of one neuron are transmitted to the dendrites of other neurons over a very small gaps called the synapses. Neurons send and receive signals in electrical-chemical form called nerve impulses or action potentials. The function of a biological neuron can be described as: 1. The dendrites of the neuron will receive signals, or action potentials, transmitted by adjacent axons and carry these signals into the cell body (the soma). 2. The signals from all the dendrites of the neuron are added together or processed. The result of the processed signals are determine if it is strong enough or surpasses a certain threshold value. 3. 4. 5. If it exceed the threshold, that neuron will generate an action potential. This action potential will then propagate along the axon to the synapses between itself and other adjacent neurons or other cells. This action potential that is transmitted over the synapses will in turn excite the dendrites of adjacent neurons to receive this action potential and carry this signal into its soma. 6. The above mentioned steps will then cycle again in other neurons. In the whole nervous system, the neurons are connected into a network of neurons. This network of neurons allow basic control of bodily functions, reflexes, and the concept of memory, learning, emotion, abstract thoughts, etcetera observed by living beings. This network that consist of billions of neuron cells works continuously to relay, process and store informations. One of the ability of biological neurons or nervous system that became the highlight for researchers to initiates and to continuously perform research of ANN is the neurons' special ability to learn.

2.2.2 Artificial Neural Network (ANN) ANNs are computational model inspired and based on the function and operation of biological neurons. The ANN was developed to imitate the principles of computations performed by the biological neural network [4]. Moreover, the ANN is attempting to imitate and apply the learning ability of the brain or the natural biological neural network into computational models for information processing purpose in computer system or other digital systems. The ANN was developed as an alternative to the conventional general-purpose processor that is mostly sequential, structured, and linear. These conventional processors are good for most problem that can be solved in sequential manner. However, it is not very effective in problems such as pattern recognitions, character recognition and signal processing. The ANN has the many attractive characteristics that may potentially surpass some of the limitations found in conventional general-purpose processors.

Figure 2.2: A Node of the Artificial Neural Network Just like the neuron is the basic building block of the nervous system, the ANN itself is made up from network of nodes or artificial neurons. In ANN, the complexity of real neuron is abstracted into a node of artificial neuron. This node basically consists of multiple inputs (analogous to the dendrites) that is multiplied by respective weight for each input, a central node analogous to the soma that will perform the computations and determine the activation of action potential, and an output (the axon) that will carry the result out from the node to another adjacent node in the network. This node of artificial neuron can be simplified as in the Figure 2.2.

This individual artificial neurons is then connected with other neurons that realised the ANN. These artificial neurons can be connected into straightforward singlelayer networks, or into small and simple multi-layer ANNs, or into massive and complex multi-layer ANNs as shown in Figures 2.3, 2.4, and 2.5. In these ANNs, the nodes exchanges informations between itself and other nodes in the network just like how biological neurons exchange informations between themselves.

Figure 2.3: Single Layer ANN [5]

Figure 2.4: Small Multi-layer ANN [6]

10

Figure 2.5: Complex Multi-layer ANN [7] The ANN is massively parallel computational system, and is also highly distributed just like the biological neural network in the brain. This parallel and distributed processing is achieved because each node can process the informations from its inputs and compute the output individually without relying much on other nodes in the ANN. Another interesting characteristic of ANN is fault-tolerant. Even if there are few node or connection is lost or damaged, this will not severely affect the whole ANN. This characteristic is also based on the brain ability to create new connection to other neurons when a neuron is damaged. Majority of ANN implementations are mainly software-based, and it runs on top of conventional sequential processors. Hardware-based implementation does exist but in very small number. Much can be gained by directly implement the ANN on hardware, especially to fully exploit the parallelism of the ANN.

11

2.2.3 ANN Learning Algorithm: Back-Propagation (BP) Algorithm One of the interesting characteristic of ANN is its ability to learn, much like the human brain itself. ANN learning process requires a training supervisor and a set of training data. An ANN normally function in feed-forward mode. In a 3-layer feed-forward ANN, the data from input layer is fed to the next layer (hidden layer) after it is computed by the input layer's nodes. This hidden layer's nodes will then compute the data it received from input layer's nodes and send the computed data to the output layer. The output layer when it received data from hidden layer's nodes will perform final computation to the data before presenting it as final output of the ANN. All nodes in all 3 layers perform the same computation. To enable the ANN learn how to perform its tasks, recognition of characters for the case of this project, BP algorithm is used. The learning process requires the use of a training supervisor, a set of predefined input data and a set of output data that is the expected output for the given input data. During this supervised training session, the ANN's training supervisor will feed 1 input data to the ANN and the expected output that the ANN should obtain based on the given input. Before the ANN begin the learning session, the weights of the dendrites for all nodes are set to any random value. From the provided input data fed by the training supervisor, the ANN will compute an output. The ANN will then compare its computed output with the expected output as stated by the training supervisor to see if it match. If the ANN's output and the expected output is not the same, the ANN will calculate the difference between the expected output and the ANN output. The ANN will then update all its connections' weight factor accordingly so that it will be able to obtain an output that match the expected output. This learning process is very slow because the ANN take time to update all its connections' weight factor. The ANN may have to execute this BP algorithm several times to achieve the ideal weight factor of all the connections for a given input data. 12

The ANN will then repeats the same learning process and BP algorithm on the other data in the training data set. All input data in the training data set has its own expected output data. Therefore the ANN will have to learn all the expected output for all input data in the training data set. This learning process takes some times to be completed. An BP algorithm is the most used learning algorithm for training an ANN. Other learning algorithms do exist but most of these algorithms are based on the BP algorithm. 2.3 Development Tools

The development of this project will be done by using VHDL. There are some development tools or IDEs that can be used for project development using VHDL. Companies such as Xilinx Inc. and Altera Corporation are very active in this field. They are major producers of FPGA chips and had developed several development tools. The Altera Quartus II software is used throughout this project,. 2.3.1 Field-Programmable Gate Array (FPGA) An FPGA is a type of semiconductor device that contains programmable logic cells and interconnections that are reprogrammable. It was designed to be programmed, configure, reprogrammed and reconfigured by the user even after manufacture. The FPGA is a programmable logic device that support implementation of relatively large logic circuits [8]. FPGA contains programmable logic components called logic blocks and reconfigurable interconnections that connect the logic blocks together. These logic blocks and its interconnections can be configured to function as simple gates or as complex combinational circuits. In most FPGAs, the logic blocks also include memory elements, like simple flip-flops or more complete blocks of memory [9]. The advantages of FPGA includes the ability to be reconfigured and reprogrammed. Being reprogrammable, the use of FPGA will significantly reduce the initial cost and lower the risk of designing unusable system. This advantages make the 13

FPGA very suitable for research and prototyping purposes before the design is submitted for fabrication on ASICs. FPGAs are also able to handle dense logic and memory elements offering very high logic capacity [10]. However the FPGA is relatively much slower than other hard-wired devices. The device itself is more expensive than any other hard-wired devices. The internal structure of FPGA is more complex to provide the reprogrammable ability. 2.3.2 Very High Speed Integrated Circuit Hardware Description Language (VHDL) Hardware description language (HDL) is a type of computer language used to describe and design the structure, operation and behaviour of electronic circuits or systems, especially digital electronic circuits or digital systems [11]. There are many HDLs exist. The 2 most widely-used HDLs are the VerilogHDL (shorted to Verilog) and the Very High Speed Integrated Circuit Hardware Description Language (VHSIC HDL or simply VHDL). For the purpose of this project, VHDL is used to describe the entity, architecture and behaviour of the system. This VHDL code will then be compiled and programmed onto a FPGA to implement the ANN project. VHDL started as a work done by the U.S. Department of Defence in the 1980's. The original VHDL standard was adopted by the IEEE in 1987 and this standard had been revised and updated several times [8]. An interesting note regarding VHDL is that the statements in VHDL are executed concurrently with exception of statements contained in a PROCESS, FUNCTION or PROCEDURE blocks that execute sequentially [12]. This is contrary to typical computer programs that are sequential. The main advantage of VHDL is that it is a standard language, has well-defined standards, and had been adopted as a standard by the IEEE. It also has wide range of readily available tools included in its standard. As a standardised language, VHDL codes are portable and can be implemented across wide range of CAD tools or software without or with minor adjustments. VHDL is powerful and versatile and VHDL codes are reconfigurable and reusable for multiple purposes [13]. The concurrent execution nature of VHDL is extremely useful to model concurrent flow of data. 14

The disadvantages on the other hand are that VHDL is complicated and confusing for beginners. One of the advantage of VHDL that can be seen as confusing is that in VHDL, there are many different ways of modelling the same design, architecture or behaviour [14]. 2.3.3 Altera Quartus II As one of the main contender in the FPGA field, Altera had developed its own suite of development tools to be used for developments of new systems or prototypes using its FPGAs. The main development software for designing with CPLDs, FPGAs from Altera is the Altera Quartus II. The Altera Quartus II is a complete suite of development tools. As of version 9.1, the Quartus II software contains all of the required tool for development of systems or prototypes with Altera's CPLDs and FPGAs devices. Altera Quartus II contains design tools that support designing using block diagrams, schematic diagrams, state diagrams, VerilogHDL, VHDL, and other design methods. The software also include compiler tool for compiling the developed design files. This compiler will check the file for any design errors and for compatibility with the selected FPGA or CPLD device to be used. Other standard tool included in QuartusII is the programmer tool for downloading users' design into selected FPGA or CPLD device. As of version 9.1, the QuartusII software also contains simulation tool for users to simulate their design. This build-in simulation tool is very useful for designers to review their design before downloading the design to the selected FPGA or CPLD device for hardware implementations. However, the simulation tool was removes in the later version of Quartus II following version 9.1, but simulation is supported by another software.

15

Figure 2.6: Altera Quartus II Web Edition Software Version 9.1 SP2 For the purpose of this project, the specification of the Quartus II development tool used and the specification of the computer system that run Quartus II are as follow. 2.4 Tool: Altera Quartus II Web Edition Version: 9.1 with service pack 2 Operating System: Microsoft Windows 7 Ultimate OS version: 6.1.7601 Service pack 1 Processor: Intel Core Duo T2450 @ 2.0GHz Main memory: 2.5Gbyte Hardware Components

This FPGA implementation of ANN for character recognition project involved the use of real hardware devices (FPGA device) to be fully implemented. The VHDL source code is developed and the compiled hardware architecture for this project will be downloaded onto an FPGA device when it is fully developed. In order to make deployment slightly easier, a development/training kit is used. The hardware components to be used in this project is the Altera CycloneII 2C35 FPGA device mounted on the Altera DE2 Development and Education Board. 16

2.4.1 Altera DE2 Development & Education Board The Altera DE2 development and education board is one of the training/development kits developed by Altera Corporation. This development kit is aimed to be used by the universities and other educational institutions. Altera DE2 is distributed by Terasic Technologies Inc. The Altera DE2 board provide the ideal support for learning about digital logic, computer organization, FPGAs, and development and prototyping for multiple purposes [15]. The board offers all features that make it suitable for laboratory use for university courses, for a variety of design projects, as well as for the development of sophisticated digital systems [16]. The main FPGA device of Altera DE2 is the Altera CycloneII EP2C35 FPGA that has a total of 33,216 Logic Elements, 105 M4K RAM blocks, 483,840 total RAM bits, 35 embedded multipliers, 4 PLLs, and 475 user I/O pins in a 672-pin FineLine BGA package [17]. Figures 2.7 and 2.8 show the Altera DE2 development and education board and the layout of the major components on the DE2 board respectively. The DE2 board comes in a boxed packaging that contains the Altera DE2 board with Plexiglas cover for the DE2 board, a 9V AC/DC adaptor, a USB cable for FPGA programming and control, and installation guide contained in a CD/DVD-ROM media [15, 17, 19].

17

Figure 2.7: Altera DE2 Development & Education Board [15]

Figure 2.8: Layout of Altera DE2 Development & Education Board [18] The specifications of the Altera DE2 development and education board as stated in the DE2 user guide are as follow [17]: Altera Cyclone II 2C35 FPGA device Altera Serial Configuration device EPCS16 USB Blaster (on board) for 18

programming and user APIcontrol; both JTAG and Active Serial (AS) programming modes are supported 2.5 512-Kbyte SRAM 8-Mbyte SDRAM 4-Mbyte Flash memory (1 Mbyte on some boards) SD Card socket 4 pushbutton switches 18 toggle switches 18 red user LEDs 9 green user LEDs 50-MHz oscillator and 27-MHz (from TV decoder) for clock sources 24-bit CD-quality audio CODEC with line-in, line-out, and microphone-in jacks VGA DAC (10-bit high-speed triple DACs) with VGA-out connector TV Decoder (NTSC/PAL) and TV-in connector 4-Mbyte Flash memory (1 Mbyte on some boards) 10/100 Ethernet Controller with a connector 4 pushbutton switches USB Host/Slave Controller with USB type A and type B connectors RS-232 transceiver and 9-pin connector PS/2 mouse/keyboard connector IrDA transceiver Two 40-pin Expansion Headers with diode protection Conclusion

The materials included in this chapter explained the general idea about this project. The basic idea behind the development of ANN paved the way for more development in this field of study. The ANN require some algorithm to function properly, and most currently used algorithms were derived and modified from the BP algorithm. The FPGA may not has the best performance in its class of semiconductor devices, but its programmable and reconfigurable characteristic made the FPGA a good choice for hardware 19

prototyping of new design and architecture. HDL such as the VHDL had made development of new digital electronic system design and architecture much easier. The VHDL allows the FPGA to be more flexible in design. The development of the project will be done using the development tools, FPGA device, and development board from Altera Corporation. The Altera Quartus II software is used to develop the project and the project in turn will be implemented onto Altera CycloneII 2C35 FPGA device on the Altera DE2 board.

20

CHAPTER 3

METHODOLOGY

3.1

Introduction

This chapter will elucidate the steps undertaken in executing the FPGA implementation of ANN for character recognition project. The methodology started by a study phase which will then progress to planning and development phase. Later, the project will enter execution phase and is followed by error recording and correction. The result is then recorded and analysed before being presented. The project should end when it produce the appropriate or acceptable result. The project will then put on hold while it is concluded and the result data will be presented. 3.2 Project Phases

The phases for developing the project can be summarised as shown in Figure 3.1. 3.2.1 Project Study This phase of the project is all about gathering information about the ANN and the motivation that fuelled the research and development of ANN which is modelled by the function of the network of biological neuron of the nervous system. Other than the ANN, information about the FPGA is also studied. The character recognition application which will be used to demonstrate the functionalities of the ANN is also studied.

21

Figure 3.1: Development Flowchart for FPGA Implementation of ANN for Character Recognition. This project phase is crucial as it provide a solid base in order for the project to be able to be carried out successfully. 3.2.2 Planning the Architecture, Algorithm, and Learning Rule of the ANN on FPGA After gathering all of the important information about the project, the methodology to carry out the project has to be carefully planned. The architecture for the ANN to be implemented on the FPGA device must be planned. This architecture plan will later be described in VHDL. The architecture of the ANN must also include the learning algorithm and the learning rule for the ANN to function.

22

3.2.3 Develop the VHDL Code in Altera Quartus II Software Once the planning is completed, the architecture, including the learning algorithm and learning rule, is then translated into VHDL code. The VHDL code is then compiled for any error and the necessary corrections is made. The development tool used for this project is the QuartusII software from Altera. The version of Altera QuartusII used throughout the project is Quartus II version 9.1 Web Edition Service Pack 2. 3.2.4 Perform Simulation on Altera Quartus II Software When the development of the VHDL code is done and there are no compile error, the code will be simulated in Altera QuartusII. The simulation result will be carefully examined for any run-time error. Any detected error has to be corrected. Correction is done by going back to code development phase and correcting the VHDL code which caused the error. Once the error is fixed, the code is simulated again and the result is examined for other error that might occur. This phase will continue until the simulation produced an acceptable result. 3.2.5 Download the VHDL Code onto Altera DE2 Development Board Once the simulation of the VHDL code produce a satisfactory result, the VHDL is then downloaded onto the Altera DE2 Development Board by Terasic. The Altera DE2 board is connected to the computer that run the Quartus II software using a USB Blaster cable. 3.2.6 Train the ANN for Character Recognition Application After the VHDL code of the ANN is downloaded onto the FPGA board, the ANN will be trained for character recognition application. The ANN is trained using the developed learning rule so that it is able to recognise and classify all of the training characters.

23

3.2.7 Deploy the ANN on Actual Data for Character Recognition The ANN is later on deployed for character recognition application using actual data. This data is obtained from the user which will input the character pattern to the system. 3.2.8 Data Collection and Analysis The resulting data obtained from the deployment of the ANN is collected and it is analysed. 3.2.9 Data Presentation The analysed data will be presented to be used by others in a format that is easily understood by other readers. 3.3 Functional Blocks

The project's overall system will consists of 7 functional blocks and a few on-board devices. The functional blocks are the ANN block, ANN training supervisor block, pseudo-random number generator block, floating point processor block, SRAM driver block, LCD controller block, and LCD driver block. The on-board devices to be used in this project are 16 toggle switches, 3 push-button switches, a SRAM memory, LEDs and LCD displays 3.3.1 Artificial Neural Network (ANN) Block This functional block is the main processing block of the project. This functional block models the ANN to be implemented in the FPGA. The ANN consist of 3 layers; input layer, hidden layer and output layer. The input nodes are connected to the toggle switches used to input the character pattern to be recognised into the system. The output from these inputs nodes are then multiplied with the associated weight factor each input-hidden nodes connection before being fed to the nodes of the hidden layer of the ANN. Each hidden nodes will sum all the input-weight product of its respective input 24

lines and perform a series of calculations. The calculated value (hidden nodes' output) is again multiplied with the associated weight factor each hidden-output nodes connection before being fed to the nodes of the output layer of the ANN. This output layer then perform the same calculations as done by hidden nodes before deciding the actual output of the system. The outputs from the nodes at the output layer forms the actual output of the whole system. This operation is called feed-forward operation. The weight factors associated to each connection between input and hidden nodes, and the weight factors associated to each connection between hidden and output nodes are assigned with random number when the ANN is initialised. This random number is generated by the pseudo-random number generator block. The ANN only perform feed-forward operations when operating normally to recognise the user input pattern. However, before the ANN can be used to perform character recognition tasks or any other tasks, it had to be trained to recognised and differentiate the different input patterns that may be input by the user. For learning process, backward propagation algorithm is used. During the learning phase, the ANN is fed with a predefined input patterns and the output from the system is compared with the expected output value. If the output from the ANN is different from the expected output, the ANN will calculate the difference between the 2 values and modify the weight factor for each of its connections accordingly so that the output from the ANN match with the expected output. This learning process is repeated several times until the ANN is able to perform the required tasks efficiently. The learning process of the ANN block is supervised by the ANN training supervisor block. 3.3.2 ANN Training Supervisor Block This functional block oversee and supervise the training process of the ANN block. It feed the predefined input pattern to the ANN during learning phase and provide the expected output for the input pattern for the ANN to learn. This block also format the user input pattern and feed the formatted user input to the ANN for processing. It then receive the output from the ANN and format it into a format used by display controller functional block to be displayed on the LCD display. 25

3.3.3 Pseudo-Random Number Generator Block This block generates pseudo random number to the assigned as the weight factors for all connections between the input and hidden nodes and all connections between the hidden and output nodes of the ANN. It has a linear feedback shift-register to generate the pseudo-random number. This block is used as actual random number generator cannot be modelled for this project. 3.3.4 Floating Point Processor Block This functional block is the arithmetic logic unit to perform arithmetic and logic operations of floating point number for the ANN block and the ANN training supervisor block. The ANN block and the ANN training supervisor block will provide the floating point numbers to be processed and provide the desired operations. The floating point processor will then signal the ANN block and the ANN training supervisor block when it finish its its operation so that the result can be collected. 3.3.5 SRAM Driver Block This is a functional block that provide the interface between the ANN block and the SRAM memory device on-board the Altera DE2 board. This block is needed as the ANN block has to access some external memory device to store the weight factors for all connections. This block provide the necessary abstraction of the on-board SRAM memory and made it easier to access the SRAM memory from the ANN block. 3.3.6 LCD Controller Block This block controls what to be displayed on the LCD module on-board the Altera DE2 board. It provides the LCD driver block with the data to generate custom characters on the LCD module. It also provide the text string of what to be displayed on the LCD module to the LCD driver block. This block receive the user input data from the toggle switches and format these 26

input data to be displayed on the left side of the LCD text field. It also receive the output from the ANN and display the recognised character on the LCD module. 3.3.7 LCD Driver Block LCD driver block is similar to the SRAM driver block as it provide the necessary abstraction for interfacing with the LCD module on-board the Altera DE2 board. This block will initialise the on-board LCD module when the system is reset and interfaces with the on-board LCD module to send custom character data and text string to be displayed on the LCD module. The custom character data and the text string to be displayed is obtained from the LCD controller block. 3.3.8 User Input Devices This system receives input from users through 16 toggle switches out of the 18 toggle switches and 3 push-button switches out of the 4 available push-button switches onboard the Altera DE2 board. The 16 toggle switches is used by the users to input the pattern to be recognised into the system. The user input pattern is reflected on the LCD module. Then the user will press the run button (one of the push-button switch) to signal the system to read the input and process it to produce the output. 3.3.9 Output Devices The liquid crystal display module on-board the Altera DE2 board is the only output device used in this project. It is used to produce user friendly output that is easier for the user to read, interpret and understand. 3.3.10 Memory Devices The SRAM memory device on-board the Altera DE2 board is also utilised to store the weight factors for all connections of the ANN.

27

3.4

Conclusion

This chapter had very much summarised all the methodologies involved in the project. The project is divided into several phases starting with study phase and ends with data collection, analysis and presentation phase. Beside that, the functional blocks representing the top-level architecture of the system to be developed on the FPGA is also explained. Each functional block has its own architecture and behaviour. These functional blocks are connected together to produce the desired behaviour of the overall system for this project. Hopefully the material in this chapter will be helpful for future projects.

28

CHAPTER 4

RESULTS AND DISCUSSION

4.1

Introduction

In this chapter, the outcome of the project FPGA implementation of ANN for character recognition is presented. The synthesised top level entity of the system is presented and clearly explained. Then the output from the system is collected and analysed. Some discussions related to the issues faced by the system and the overall project are included at the end of the chapter. 4.2 Top Level Entity

The top level entity of the system shows the overall configuration of the system, the functional blocks and the interconnections between the functional blocks. Figure 4.1 shows the synthesised RTL circuit of the whole system. The functional blocks included in the systems are the ANN (block ann:ann0), ANN training supervisor (block pr:pr0), pseudo-random number generator (block lfsr:lfsr0), floating point processor (block float_alu:float_alu0), SRAM driver (block sram:sram0), LCD controller (display_controller:display0), and LCD driver (LCDdriver:lcd0). The input/output devices used in this projects are 16 toggle switches, a SRAM memory, LEDs and LCD displays. 4.2.1 FPGA Device's Resources Used After the project is compiled on Altera Quartus II software, its shown that the 29

development and deployment of this project only utilise 35% of the total 33216 logic elements on the Altera CycloneII EP2C35F672C6 FPGA on-board the Altera DE2 board. Out of the 475 I/O pins of the FPGA device, only 158 pins are used (Figure 4.2).

Figure 4.1: Synthesised Top-level RTL Circuit

Figure 4.2: Project Compilation Report on Altera QuartusII 30

4.3

Results

When system is finalised, the VHDL code is compiled and programmed onto the Altera Cyclone II FPGA on-board the Altera DE2 board. The full system of this FPGA implementation of ANN for character recognition is deployed. The system is designed to recognise a total of 16 character patterns on a 44 grid. The system is trained with the following character patterns (Table 4.1). Table 4.1: Character Pattern and Its Expected Output Character Pattern Expected Output A C D F H I J L N O

31

Character Pattern

Expected Output P T U X Y Z

Figure 4.3: System Output During Initialisation

Figure 4.4: System Output During ANN Training Phase

32

Figures 4.3 and 4.4 show the output on the LCD module during system initialisation and during ANN learning phase. During learning phase, user can input their desired input pattern. The input pattern will be displayed on the left side of the screen of LCD module. The system will enter running mode once the run push-button switch is pressed. In this mode, the ANN will recognise the input character. Once the character is recognised, the LCD module will display the output.

Figure 4.5: System Output During Running Mode The input patterns and the recognised outputs can be viewed on the on-board LCD module. The following figures shows the result when the system is deployed.

Figure 4.6: System Output for Input A

33

Figure 4.7: System Output for Input F

Figure 4.8: System Output for Input Z 4.4 Discussion

Throughout the design, development and deployment of this FPGA implementation of ANN for character recognition project, there are several issues occurred. The availability of real number data type in VHDL will benefit the project greatly. This real data type will be used to represent and store numbers out of the range of integer type as well as fractional numbers [20]. This data type is included in the standard package of VHDL. However the Altera QuartusII Software version 9.1 Web Edition used for this project does not support this feature of real number data type. In Altera QuartusII Software version 9.1 Web Edition, real type can be compiled but the software is unable to synthesis non-constant real type. Instead QuartusII will issue Error (10414): VHDL Unsupported Feature error: cannot synthesize non-constant real 34

objects or values. This issue had affected the project in many ways as real data types is necessary to represent fractional and exponential numbers. The floating point processor is used to overcome the issue in using VHDL real data type. Although Altera QuartusII is unable to synthesis real numbers, the software does included a wizard to generate files needed to process floating point values. This generated VHDL code for floating point processing is used to process the fractional and exponential numbers exist in the design of this project. The connection weights in the ANN had to be initialised to random value of real type when the ANN is reset. However due to above mentioned issue with real number data type in Altera QuartusII, actual real type random number generator cannot be modelled for this project. Moreover, it is hard to model an actual random number generator in digital hardware. Therefore a pseudo-random number generator utilising linear feedback shift-register is modelled to supplement the lack of real random number generator in the design of this project. The system is functioning properly and it is able to recognise the character patterns it was trained to recognise. An issue arise when user input a character pattern that is similar to any of the trained pattern but not exactly the same as shown in the figures below. When the user input a character pattern that is similar to the character pattern for C, the ANN recognise the input character pattern as D instead of C. The actual character pattern of C and D of which the ANN is trained to recognise is also shown below for reference. This issue may or may not arise because the weight factors for all connection between the nodes in the ANN is initialised randomly. A plausible reason for the above mentioned issue may be due to the lack of pixels used to represent each characters. As shown in Figures 4.9, 4.10 and 4.11, the difference between the character pattern C and D is the position of the dots at the right side of the character pattern. This may lead the ANN to mistakenly recognise the user input of a character pattern that is similar to the character pattern for C as D. One way to overcome this issue is by increasing the number of pixels for the character patterns from 44 to 57. Do bear in mind that when the number of pixels for the character patterns is increased, the number of nodes in the ANN will increase. 35

Figure 4.9: System Output for Input Similar to C

Figure 4.10: System Output for Input C

Figure 4.11: System Output for Input D

36

4.5

Conclusion

This project had produced favourable result. The system is capable to recognise all 16 character patterns included in its training data set. During initialisation, the system will enter initialisation state before going to learning state where the ANN learn to recognise the 16 character patterns in the training data set. During this time the system will not be able to perform any recognition task until the ANN finishes the learning state. Users input the character patterns into the system using SW17 SW2 toggle switches onboard the Altera DE2, and PB3 push-button switch is pressed to signal the ANN to perform recognition process of the input character pattern. The input pattern and recognition output is displayed on the LCD module. Apart from some issues discussed earlier, this project is functional to recognise 16 character patterns.

37

CHAPTER 5

CONCLUSION

5.1

Introduction

This chapter of the report will include some concluding remarks regarding the project and short discussion of possible future works to further improve the project. 5.2 Conclusion

This project started off with a study phase to familiarise with ANN as a mathematical and computational model of biological neural network based on mathematics and algorithms. Then a methodology is developed to design the ANN model using VHDL, followed by execution phase of developing the VHDL codes for the whole project. The completed code is compiled and programmed onto the Altera Cyclone II FPGA on the Altera DE2 board where the code is tested. When faced with some issues, the VHDL code is revised, recompiled and reprogrammed onto the FPGA device again and again. The outcome of this project is collected and analysed for future improvements. In overall, this project of FPGA implementation of ANN for character recognition can be seen as a starting point for introduction to ANN, future exploration of the wide range of application of ANN, the multiple designs available to develop an ANN. The ANN itself is an interesting topic that can be further explored to fully understand and design. This project may also be seen as a starting point for developing a ANN to be directly embedded on hardware devices instead of running the ANN algorithms on a computer system. 38

In conclusion, this project works as an introduction to the endless possibilities of ANN design, development and applications. This project is also an eye opener to the infinite possibility of designing, developing and prototyping of new systems using VHDL and FPGAs. 5.3 Future works

This project is by no means is finished. The ANN system developed for this project is can be develop further to be able to recognise more character patterns with larger pixel counts. The ANN may also be applied for other applications other than character recognition, for example, voice recognition, natural image recognition, and many other applications. The VHDL code for this project can be further optimised to obtain better result and performance. The issues discussed in Chapter 4 is yet to be solved. All of this issues, optimisations, and developments regarding this project are just a small fraction of what other tasks that can be done in the future. 5.4 Potential Commercialisation

This ANN system has the potential to be commercialised as a system to be used as recognition system to recognise characters. Once the ANN is improved, the system may be deployed as character recognition system to read car plate numbers and other natural characters. With the flexibility of ANN the system may also be deployed for other application provided that the ANN is trained for the said applications. Other potential application of this system that has commercial potential may include barcode reader, biometric systems such as thumbprint reader and facial recognition system, etc.

39

REFERENCES [1] Gurney, K., (1997). An introduction to neural networks. London: UCL Press. [2] Wikipedia, (2013). Neural network. Retrieved from en.wikipedia.org/wiki/ Neural_network [3] EnchantedLearning.com, (2001). Brain cells. Retrieved from http://www.enchantedlearning.com/subjects/anatomy/brain/Neuron.shtml [4] Omandi, A. R., Rajapakse, J. C., & Bajger, M. (2006). FPGA neurocomputers. In A. R. Omandi, & J. C. Rajapakse (Eds.), FPGA implementation of neural network (pp. 1-36). Netherlands: Springer. [5] Wikibooks, (2008). Artificial neural networks/print version. Retrieved from http://en.wikibooks.org/wiki/Artificial_Neural_Networks/Print_Version [6] Satizbal, H., & Perez-Uribe, A., (2012). Supervised learning: TORCS, the open racing car simulator. Retrieved from http://ape.iict.ch/teaching/AIGS/AIGS_Labo/Labo4-Supervised [7] Mol, A. C. D. A., Martinez, A. S., & Schirru, R. (2003). A neural model for transient identification in dynamic processes with don't know response. Annals of Nuclear Energy, 30(13), 1365-1381. Retrieved from http://www.sciencedirect.com/science/article/pii/S0306454903000720 [8] Brown, S., & Vranesic, Z., (2009). Fundamentals of digital logic with VHDL design [3rd ed.]. New York: McGraw-Hill. [9] Wikipedia, (2013). Field-programmable gate array. Retrieved from http://en.wikipedia.org/wiki/FPGA [10] Hossz, G. (2006). FPGA circuits [PPT lecture slides for Computer-Aided Engineering course]. Retrieved from http://nimrud.eet.bme.hu/cae/ppt/1dig_circ/4fpga.ppt [11] Wikipedia, (2013). Hardware description language. Retrieved from http://en.wikipedia.org/wiki/Hardware_description_language [12] Pedroni, V. A., (2004). Circuit design with VHDL. Cambridge, Massachusetts: MIT Press. [13] Klenke, R., (1999). Advanced Concepts in VHDL [PPT presentation slide]. Retrieved from http://www.people.vcu.edu/~rhklenke/tutorials/vhdl/modules/m13_23/index.htm 40

[14] The Digital Electronics Blog, (2007). Comparison of VHDL to other hardware description languages [Blog entry]. Retrieved from http://digitalelectronics.blogspot.com/2007/07/comparison-of-vhdl-to-otherhardware.html [15] Altera Corporation, (n.d.). DE2 development and education board. Retrieved from http://www.altera.com/education/univ/materials/boards/de2/unv-de2-board.html [16] Terasic Technologies Inc., (n.d.). Altera DE2 board overview. Retrieved from http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English& Category No=39&No=30 [17] Altera Corporation, (2012). DE2 development and education board user manual [User manual] (Version 1.6). Altera Corporation. [18] Terasic Technologies Inc., (n.d.). Altera DE2 board layout. Retrieved from http://www.terasic.com.tw/attachment/archive/30/image/image_58_thumb.jpg [19] Terasic Technologies Inc., (n.d.). Altera DE2 board kit content. Retrieved from http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&Category No=39&No=30&PartNo=5 [20] Perry, D. L., (2002). VHDL: Programming by example [4th ed.]. McGraw-Hill. [21] Wikipedia, (2013). VHDL. Retrieved from http://en.wikipedia.org/wiki/Vhdl [22] Terasic Technologies Inc., (n.d.). Altera DE2 board specification. Retrieved from http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&Category No=39&No=30&PartNo=2 [23] Gnani, D., Guidi, V., Ferroni, M., Faglia, G., & Sberveglieri, G. (1998). Highprecision neural pre-processing for signal analysis of a sensor array. Sensors and Actuators B: Chemical, 47(1), 77-83. Retrieved from http://www.sciencedirect.com/science/article/pii/S0925400598000100 [24] Hoehn, K., (2012). Neuron. Retrieved from http://www.biologyreference.com/MoNu/Neuron.html [25] Krse, B., & Smagt, P. (1996). An introduction to neural networks (8th ed.). Amsterdam. [26] Zhou, Z. (2010) FPGA-based Artificial Neural Network. Retrieved from http://www.ziyan.info/2010/05/fpga-based-artificial-neural-network.html

41

APPENDIX A VHDL CODE FOR TOP-LEVEL DESIGN ENTITY

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE WORK.ann_types.ALL; USE WORK.ann_components.ALL; USE WORK.pr_components.ALL; USE WORK.lfsr_components.ALL; USE WORK.pattern_types.ALL; USE WORK.pattern_constants.ALL; USE WORK.float_types.ALL; USE WORK.float_components.ALL; USE WORK.float_constants.ALL; USE WORK.display_types.ALL; USE WORK.display_components.ALL; USE WORK.lcd_types.ALL; USE WORK.lcd_components.ALL; USE WORK.sram_types.ALL; USE WORK.sram_components.ALL; ENTITY de2_ann IS PORT ( -----------------------Clock Input CLOCK_50 : IN STD_LOGIC;

-------------------------On Board 50 MHz

-----------------------Push Button -----------------------KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --Pushbutton[3..0] -----------------------Toggle Switch -----------------------SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0); --Toggle Switch[17..0] -----------------------7-SEG Dispaly -----------------------HEX0 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --Seven Segment 0 HEX1 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --Seven Segment 1 HEX2 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --Seven Segment 2 HEX3 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --Seven Segment 3 HEX4 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --Seven Segment 4 HEX5 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --Seven Segment 5 HEX6 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --Seven Segment 6 HEX7 : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); --Seven Segment 7 -----------------------LED -----------------------LEDG : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); --Green LED[8..0] LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); --Red LED[17..0] -----------------------SRAM Interface -------------------------SRAM Data bus 16 Bits SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); --SRAM Address bus 18 Bits SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);

42

--SRAM High-byte Data Mask SRAM_UB_N : OUT STD_LOGIC; --SRAM Low-byte Data Mask SRAM_LB_N : OUT STD_LOGIC; --SRAM Write Enable SRAM_WE_N : OUT STD_LOGIC; --SRAM Chip Enable SRAM_CE_N : OUT STD_LOGIC; --SRAM Output Enable SRAM_OE_N : OUT STD_LOGIC; -----------------------LCD Module 16X2 -------------------------LCD Power ON/OFF LCD_ON : OUT STD_LOGIC; --LCD Back Light ON/OFF LCD_BL : OUT STD_LOGIC; --LCD Read/Write Select; 0 = Write; 1 = Read LCD_RW : OUT STD_LOGIC; --LCD Enable LCD_EN : OUT STD_LOGIC; --LCD Command/Data Select; 0 = Command; 1 = Data LCD_RS : OUT STD_LOGIC; --LCD Data bus 8 bits LCD_DB : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ENTITY de2_ann; ARCHITECTURE de2_ann_beh OF de2_ann IS CONSTANT PATTERN_SIZE : INTEGER := PATTERN_SIZE; CONSTANT PATTERN_CLASS_COUNT : INTEGER := PATTERN_CLASS_COUNT; CONSTANT PATTERN_TRAINING_COUNT : INTEGER := PATTERN_TRAINING_COUNT; -- user inputs SIGNAL system_reset_key : STD_LOGIC; SIGNAL ann_reset_key : STD_LOGIC; SIGNAL run_key : STD_LOGIC; SIGNAL user_inputs : STD_LOGIC_VECTOR(PATTERN_SIZE - 1 DOWNTO 0) := (OTHERS => '0'); -- ANN supervisor SIGNAL pr_ready : STD_LOGIC := '0'; SIGNAL pr_inputs : STD_LOGIC_VECTOR(PATTERN_SIZE - 1 DOWNTO 0) := (OTHERS => '0'); SIGNAL pr_output : INTEGER := 0; SIGNAL pr_training_mse : float := float_half; SIGNAL pr_training_mse_sel : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; -- ann SIGNAL ann_alpha : float := float_one; SIGNAL ann_inputs : float_vector(PATTERN_SIZE - 1 DOWNTO 0) := (OTHERS => float_zero); SIGNAL ann_outputs : float_vector(PATTERN_CLASS_COUNT - 1 DOWNTO 0) := (OTHERS => float_zero); SIGNAL ann_targets : float_vector(PATTERN_CLASS_COUNT - 1 DOWNTO 0) := (OTHERS => float_zero); SIGNAL ann_ready : STD_LOGIC := '0';

43

SIGNAL ann_mse : float := float_zero; SIGNAL ann_mode : ann_mode := idle; -- alu SIGNAL float_alu_ready : STD_LOGIC := '0'; SIGNAL float_alu_a, float_alu_b, float_alu_c : float := float_zero; SIGNAL float_alu_mode : float_alu_mode := idle; -- sram SIGNAL sram_address : sram_address := (OTHERS=>'0'); SIGNAL sram_input : sram_data := (OTHERS=>'0'); SIGNAL sram_output : sram_data := (OTHERS=>'0'); SIGNAL sram_mode : sram_mode := read; SIGNAL sram_ready : STD_LOGIC := '0'; -- lfsr SIGNAL lfsr_output : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'0'); -- lcd SIGNAL lcd_dd : lcdtext_t_vector(0 TO 31) := (OTHERS => x"00"); SIGNAL lcd_cg : lcdcustomchar_t_vector(0 TO 7) := (OTHERS => (OTHERS => '0')); -- display SIGNAL display_mode : display_mode := training; SIGNAL display_mode_sel : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; BEGIN -- user inputs user_inputs <= SW(17 downto 2); system_reset_key <= NOT KEY(0); ann_reset_key <= NOT KEY(1); run_key <= NOT KEY(3); pr_inputs <= user_inputs; -- ANN BLOCK ann0 : ann GENERIC MAP ( N_I => PATTERN_SIZE, N_H => PATTERN_SIZE + PATTERN_CLASS_COUNT, N_O => PATTERN_CLASS_COUNT ) PORT MAP ( reset => system_reset_key OR ann_reset_key, clock => CLOCK_50, mode => ann_mode, alpha => ann_alpha, inputs => ann_inputs, targets => ann_targets, outputs => ann_outputs, mse => ann_mse, ready => ann_ready, float_alu_a => float_alu_a, float_alu_b => float_alu_b, float_alu_c => float_alu_c, float_alu_mode => float_alu_mode, float_alu_ready => float_alu_ready, sram_addr => sram_address,

--number of input node --number of hidden node --number of output node

44

sram_input sram_output sram_mode sram_ready lfsr_output );

=> sram_input, => sram_output, => sram_mode, => sram_ready, => lfsr_output

-- ANN training supervisor block pr0 : pr GENERIC MAP ( N_I => PATTERN_SIZE, -- pattern input size N_O => PATTERN_CLASS_COUNT, -- number of classes to recognize N_T => PATTERN_TRAINING_COUNT -- number of traning data ) PORT MAP ( reset => system_reset_key OR ann_reset_key, clock => CLOCK_50, go => run_key, training_data => PATTERN_TRAINING_DATA, training_class => PATTERN_TRAINING_CLASS, training_mse => pr_training_mse, inputs => pr_inputs, output => pr_output, ready => pr_ready, ann_mode => ann_mode, ann_alpha => ann_alpha, ann_inputs => ann_inputs, ann_targets => ann_targets, ann_outputs => ann_outputs, ann_mse => ann_mse, ann_ready => ann_ready, lfsr_output => lfsr_output ); -- pseudo-random number generator block lfsr0 : lfsr PORT MAP( reset => system_reset_key, clock => CLOCK_50, output => lfsr_output ); -- floating point processor block float_alu0 : float_alu PORT MAP ( reset => system_reset_key, clock => CLOCK_50, a => float_alu_a, b => float_alu_b, c => float_alu_c, mode => float_alu_mode, ready => float_alu_ready ); -- SRAM driver block sram0 : sram PORT MAP ( reset clock

=> system_reset_key, => CLOCK_50,

45

addr input output mode ready SRAM_DQ SRAM_ADDR SRAM_UB_N SRAM_LB_N SRAM_WE_N SRAM_CE_N SRAM_OE_N );

=> sram_address, => sram_input, => sram_output, => sram_mode, => sram_ready, => SRAM_DQ, => SRAM_ADDR, => SRAM_UB_N, => SRAM_LB_N, => SRAM_WE_N, => SRAM_CE_N, => SRAM_OE_N

-- display controller block display0 : display_controller PORT MAP( rst => system_reset_key, clk => CLOCK_50, mode => display_mode, inputs => user_inputs, class => PATTERN_DISPLAY(pr_output), lcddd => lcd_dd, lcdcg => lcd_cg ); -- lcd driver block lcd0 : LCDdriver PORT MAP ( rst clk LCDON LCDBL LCDRS LCDRW LCDEN LCDDB lcddd lcdcg ); -- display mode select display_mode_sel <= pr_ready & ann_ready & run_key; WITH display_mode_sel SELECT display_mode <= training WHEN "000"|"001"|"010"|"011", running WHEN "100"|"101"|"111", idle WHEN "110"; -- training accuracy pr_training_mse <= float_half; -- output class display LEDG(7 DOWNTO 0) <= STD_LOGIC_VECTOR(TO_UNSIGNED(pr_output, 8)); -- bist indicator LEDG(8) <= pr_ready;

=> system_reset_key, => CLOCK_50 , => LCD_ON, => LCD_BL, => LCD_RS, => LCD_RW, => LCD_EN, => LCD_DB, => lcd_dd, => lcd_cg

46

-- mean squared error display LEDR <= ann_mse(31 DOWNTO 14); -- turn off the 7 segment displays HEX0 <= (OTHERS => '1'); HEX1 <= (OTHERS => '1'); HEX2 <= (OTHERS => '1'); HEX3 <= (OTHERS => '1'); HEX4 <= (OTHERS => '1'); HEX5 <= (OTHERS => '1'); HEX6 <= (OTHERS => '1'); HEX7 <= (OTHERS => '1'); END ARCHITECTURE de2_ann_beh;

47

APPENDIX B RTL VIEW OF TOP-LEVEL ENTITY

48

APPENDIX C LCD OUTPUTS During initialisation

When the ANN is training

When the ANN is recognising an input character pattern

49

Output for input A

Output for input C

Output for input D

Output for input F

50

Output for input H

Output for input I

Output for input J

Output for input L

51

Output for input N

Output for input O

Output for input P

Output for input T

52

Output for input U

Output for input X

Output for input Y

Output for input Z

53

LEE YEE ANN

B.ENG. (HONS) (COMPUTER NETWORK ENG.)

2013

UniMAP