CIT-EEE-09EE48-LAB MANUAL EXP NO: 12

EXPERIMENT NO : DATE : AIM:

DESIGN OF PRBS GENERATOR AND SHIFT REGISTER

To verify the sequence of PRBS generator and to design and study the operation of shift register using JK flip flop. APPARATUS REQUIRED: . Sl. NAME OF THE No. APPARATUS IC 7476 1. 2. 3. 4. 5. IC 7404, IC 7400, IC 7486 Resistor Bread board Connecting wires

RANGE

QUANTITY 1

330

Each 1 2 1 1set

Theory: A shift register is the one which is capable of shifting its binary information in one or both direction. The output of a given flip flop is connected to the input of the next flip flop. Each clock pulse given simultaneously shifts the contents of the register one bit position to the right. The serial input determine what goes into the left most flip flop will be passed serially to the next flip flop after each clock pulse. When preset enable is enables then it acts as parallel in parallel out shift register. When preset is disabled then it acts as a serial in serial out shift register. CIRCUIT DIAGRAM: UNIVERSAL SHIFT REGISTER:

CIT-EEE-09EE48-LAB MANUAL EXP NO: 12

Truth Table: Parallel Input Parallel Output: S.No Preset Enable 1. 2. High High Di3 1 1 Parallel IN Di2 0 0 Di1 1 0 Di0 1 1 Q3 1 1 Parallel OUT Q2 0 0 Q1 1 0 Q0 1 1

3. 4.

High High

0 1

1 0

0 1

0 0

0 1

1 0

0 1

0 0

Parallel Input Serial Output:

Preset Enable Di3

Parallel IN

Preset Enable

Serial OUT Before clock Q3 1 Q2 0 1 0 0 Q1 1 0 1 0 Q0 0 1 0 1 After Clock Q3 Q2 Q1 Q0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0

Di2

Di1

Di0

High

0 Low 0 0

CIT-EEE-09EE48-LAB MANUAL EXP NO: 12

Serial Input Serial Output: Preset Enable Serial Input Low Low Low Low Low Low Low 1 0 1 0 0 0 0 Q3 0 1 0 1 0 0 0 Serial OUT Before clock Q2 0 0 1 0 1 0 0 Q1 0 0 0 1 0 1 0 Q0 0 0 0 0 1 0 1 After Clock Q3 Q2 Q1 Q0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0

Serial Input Parallel Output: S.No Preset Enable Serial Input Q3 1 2 3 4 Low Low Low Low 1 0 1 0 0 1 0 1 Serial OUT Before clock Q2 0 0 1 0 Q1 0 0 0 1 Q0 0 0 0 0 After Clock Q3 Q2 Q1 Q0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0

PRBS Counter: A shift register with suitable feedback can be used to generate the PRBS waveform. The input to the feedback network, which have to be linear and follow combinational logic are the outputs at selected stages of the shift register. The sequencegenerated by this 4 stage arrangement at clock input pulse is easily derived as in table. Considering the initial contents of the four stages to be arbitrary chosen as 1,1,1,1 as seen in table. The 15th clock pulse restores the shift register to the initial stage viz 1,1,1,1 and the sequence repeats.

CIT-EEE-09EE48-LAB MANUAL EXP NO: 12

Circuit Diagram:

Truth Table: Q1(A) 1 0 0 0 1 0 0 1 1 0 1 0 1 1 Q2(B) 1 1 0 0 0 1 0 0 1 1 0 1 0 1 Q3(C) 1 1 1 0 0 0 1 0 0 1 1 0 1 0 Q4(D) 1 1 1 1 0 0 0 1 1 0 1 1 0 1

CIT-EEE-09EE48-LAB MANUAL EXP NO: 12

1 1

1 1

1 1

0 1

Viva Questions: 1. What is a shift register? Give some applications that use shift register. 2. What is universal shift register? 3. What is shift register counter? Give examples. 4. Mention the applications of shift register.

Result: Thus the universal shift register and sequence PRBS generator using JK flip flop are designed and their operations were studied.