2012 25th International Conference on VLSI Design

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs
Chetan Vudadha, Goutham Makkena, M Venkata Swamy Nayudu, Sai Phaneendra P, Syed Ershad Ahmed, Sreehari Veeramachaneni, N Moorthy Muthukrishnan, M.B. Srinivas
Department of Electrical Engineering, Birla Institute of Technology and Science-Pilani, Hyderabad Campus, Hyderabad, India. {chetan, h2009002, h2009007, h2009009, syed, srihari, moorthy, mbs}@bits-hyderabad.ac.in
AbstractThis paper presents a new improved multiplexer based decoder for flash analog-to-digital converters. The proposed decoder is based on 2:1 multiplexers. It calculates the binary code for low operand length thermometer code at initial stages and groups the output of initial stages to generate the final result. The proposed decoder can be configured to operate on thermometer code with reduced length without any extra overhead. This self-reconfigurable property is particularly useful in adaptive resolution analog-to-digital converters. Simulation results indicate that the proposed decoder results in reduced delay, power and power delay product when compared to existing digital decoders for flash analog-digital converters. Keywords-Flash converter; Multi-precision; Reconfigurable;Low power; Thermometer-to-binary ;

jitter, device mismatch, meta-stability and error probability of the comparators etc. This paper presents an improved Multiplexer (MUX) based decoder for flash ADCs. The proposed decoder can be configured to operate on thermometer code with reduced operand length without any extra overhead and is suitable for adaptive resolution ADC designs. The decoder can also be configured to operate on multiple thermometer codes of reduced length. The proposed decoder results in reduced delay and power than the existing digital decoders.

I.

INTRODUCTION

Analog to-digital converter (ADC) is a key functional block in the design of mixed signal, system on chip and signal processing applications. Many types of ADCs have been developed for different applications [1]. High speed ADCs are often based on flash structure [2-4] shown in Figure 1. Recently flash ADCs with adaptive resolution have also been proposed [5-6]. In the flash ADC implementation the input signal is applied to inputs of 2N-1 comparators, where N indicates the resolution of the ADC. Each comparator is connected to a reference voltage commonly generated by a resistive ladder. The output of comparator is high if the input voltage is larger than the reference voltage at the input of comparator otherwise the output is low. Hence the output pattern corresponds to thermometer code. The thermometer code is converted in to binary code by (2N-1)to-N decoder generally called as Thermometer-to-Binary decoder. Many implementations have been proposed for thermometer to binary conversion [7-13]. A comparison of different decoders was presented in [7]. Folding techniques for the decoders have been presented in [13] [15]. These techniques result in reduced hardware complexity. For low resolution and low speed ADCs, the inputs to the decoder will be perfect thermometer code. As the resolution and speed of operation of the ADC increase, bubble errors are introduced in the thermometer code. The bubble errors are unwanted digital zeros introduced in the thermometer code and are result of many sources, for example: clock
1063-9667/12 $26.00 2012 IEEE DOI 10.1109/VLSID.2012.84 280

Figure 1. Illustration of Flash ADC

The rest of the paper is organized as follows: Section II describes the related work. Section III describes the proposed improved MUX based decoder. This section also explains the self reconfigurable property of the proposed decoder. Simulation results are presented in section IV and conclusions are drawn in section V. II. RELATED WORK

A common approach to decode the thermometer code is to use a gray or binary ROM based decoder [8-9]. The basic structure of the ROM based decoder is shown in Figure 2. The ROM based approach has 2 stages. In the first stage the thermometer code is converted in to 1-out of-2N-1 code. This can be done by using array of NAND gates as shown in the Figure 2. The second stage is the ROM structure which takes the 1-out-of 2N-1 code as input and selects appropriate row in the ROM. Although ROM decoder approach is simple and straight forward to design, it is however slow and consumes large power due to a constant static current used to preset the ROM encoder [9]. Another problem of binary ROM decoder

is the bubble error. When bubble error occurs there are more than one 1s in 1-out of-2N-1 code. Hence more than one row in the ROM will be enabled resulting in erroneous binary code. Many digital decoders for converting thermometer code to binary code have been presented in the literature. The straight forward approach is the Wallace tree based decoder [10] [7], which count the number of number of 1s. This approach has the benefit of bubble suppression. Another advantage of using ones counter as a decoder is that depending on the speed of ADC a suitable ones counter topology may be used by a speed power trade off. The disadvantage of this approach is that it results in large delay and power.

A more optimized implementation of the fat tree based encoder is presented in [12]. This approach reduces the array of OR gates into NAND-NOR pairs. The NAND-NOR gates were implemented using a pseudo-dynamic CMOS logic. A MUX based thermometer to binary decoder is proposed in [13]. This decoder results in short critical path and small area. At each level, the input thermometer code is divided in two and one of the bits in the binary output is calculated. Figure 4 shows the implementation of MUX based decoder for 15-bit thermometer code input. The disadvantage of this approach is that it results in huge fan-out in the critical path. The MUX based implementation of 15bit thermometer code to binary decoder results in fan-out of 7 in level 1 and 4 in level 2. The increased fan-out results in increased power consumption and delay.

Figure 2. Flash ADC implmentation with ROM Decoder

A more power and delay efficient approach of converting thermometer to binary code is to use Fat tree based decoder [11]. Fat tree structure has two stages. The first stage converts the thermometer code to 1-out of-2N-1 code. The second stage converts the 1-out of-2N-1 code to binary code using multiple trees of OR gates. This results in reduced area and delay when compared to Wallace tree based decoder. Figure 3 shows the implementation of fat tree based decoder for 15-bit thermometer code input.

Figure 4. Existing MUX Based Decoder [13]

III.

PROPOSED IMPROVED MUX-BASED DECODER

A. Basic Idea The main idea behind the design of the proposed MUX based decoder is to group the results of smaller length MUXbased decoders to form a larger decoder for thermometer to binary conversion. This idea is explained by designing a 7bit thermometer code to binary decoder using a 3-bit thermometer to binary code decoder. A simple circuit to convert 3-bit thermometer code to binary code along with the truth table for the same is shown in the Figure 5. Here T3-T1 represents the input Thermometer code and B2-B1 represents the binary code.

Figure 5. 3-bit Thermometer to binary decoder for 2-bit Flash ADC Figure 3. Fat Tree Based Decoder [11]

Now the 3-bit thermometer to binary decoder can be used to design a 7-bit thermometer to binary decoder. The truth

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table and pictorial representation of the design of 7-bit thermometer to binary decoder using the 3-bit thermometer to binary decoder is shown in Figure 6. In the truth table, T7T1 represents the input thermometer code and B3-B1 represents the binary code. As seen from truth table B3= T4, and When T4 = 0 the B2-B1 are equivalent to the outputs of 3bit thermometer to binary decoder with T3T2T1 as inputs. When T4 = 1 the B2-B1 are equivalent to the outputs of 3bit thermometer to binary decoder with T7T6T5 as inputs.

present in the left hand side of T4 signal, which is equal to two i.e. 10. This now represents the LSB bits B2-B1 of the final binary code. This design methodology can be extended to implement a 2N-1 bit decoder that can be used for an N-bit flash ADC. A generalized implementation of a 2N-1 bit decoder is shown in the figure 8.

Figure 8. Generalized Implmentation of 2N-1 thermometer to binary decoder for N-bit Flash ADC

Figure 6. Truth table for 7-bit thermometer to binary decoder

Hence using a T4 as selection signal, 7-bit thermometer to binary decoder can be constructed using 3-bit thermometer to binary decoders and array of MUXs. Such an implementation of 7-bit Thermometer to binary decoder is shown in the figure 7, the dotted block indicates 3-bit thermometer to binary decoder.

A 2N-1 bit decoder can be designed by using two 2N -1-1 bit decoders and an array of MUXs to generate the binary N code BN-B1 from the thermometer code T (2 -1) - T1. Each N -1 of the 2 -1 bit decoders can further be designed using two 2N -2-1 bit decoders and an array of MUXs. This iterative implementation can be done until the basic element, i.e. a 3bit thermometer to binary decoder, is reached. This implementation results in a more regular structure. The proposed 15-bit thermometer to binary decoder is shown in figure 9(d).This decoder results in a more regular structure, same number of gates and less maximum fan-out than the existing MUX based decoder [13]. The proposed decoder results in reduced number of gates when compared to Wallace tree decoder and fat tree decoders. B. Critical pathdelay comparision The critical path delay for existing and proposed decoders is shown in figure 9. The proposed MUX based decoder has three gates delay in its critical path for a 15-bit thermometer to binary decoder shown in figure 9(d). Although the existing 15-bit thermometer to binary MUX based decoder has a 3 gate delay in the critical path, a maximum fan-out of 7 for the input signal at the first stage results in increased delay. The proposed decoder has a maximum fan-out on input signal in the last stage of the circuit and hence does not occur in the critical path. The 15-bit Wallace tree based decoder and Fat tree based decoder has a critical path delay of 7 gates and 4 gates respectively. The critical path delay in terms of gates for different 63-bit decoders, which can be used in 6-bit flash ADC are presented in Table I.

Figure 7. Proposed 7-bit Thermometer to binary decoder for 3-bit Flash ADC

The 7-bit thermometer to binary converter uses two 3-bit thermometer to binary converters. Two MUXs are used for implementing the selection. The outputs of 3-bit decoders are fed to these MUXs and the selection signal T4 selects outputs from either one of the dotted 3-bit decoders. Consider example where the 7-bit thermometer code T7T1 is given by 0111111, since the T4 signal being 1 indicates that all the bits to right hand side of T4 i.e. T3-T1 are 1 making the binary code B3-B1 greater than 100. The LSB bits B2-B1 are now defined by the number of 1s

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(a)

(b)

(c)

(d)

Figure 9. Different 15-bit Thermometer to Binary Decoders (a) Wallace Tree Based (b) Fat-tree Based (c) Existing MUX Based (d) Proposed TABLE I. CRITICAL PATH DELAY COMPARISON FOR DIFFERENT DECODERS
No. of gates in Critical Path Delay 18 6 5 5 Maximum fan-out in the Critical path 2 2 31 2

63-bit Decoder (for 6-bit Flash ADC) Wallace Tree Fat Tree Decoder Existing MUX-based Proposed MUX-based

the existing decoder designs. The switching activity is directly related to dynamic power, which forms a major component of the total power consumption. Hence the proposed decoder results in low power consumption when operated for thermometer codes with smaller length and is ideally suited for adaptive resolution ADCs. Further the proposed decoder can be configured to operate on multiple thermometer codes. The 15- bit thermometer to binary decoder can be operated as two 7-bit thermometer to binary decoders by making the T8 signal as logic zero and latching the intermediate outputs of the 7-bit thermometer to binary decoder which has T9-T15 as inputs. This can also be achieved by making the T8 signal as logic one and latching the intermediate outputs of the 7-bit thermometer to binary decoder which has T1-T7 as inputs. This property is unique to the proposed MUX based decoder and is not present in any of the existing decoder designs. Since the proposed decoder can be configured to operate on single or multiple thermometer codes of shorter length without any extra circuitry, it is said to be selfreconfigurable. D. Bubble Error Correction Wallace tree based decoder has inherent bubble suppression property, where as for other decoders, including the proposed decoder, need a bubble correction circuit for correcting the bubble errors. The different bubble correction circuits that can be used for different decoders are presented in [14]. Since the basic operation of the proposed MUX based decoder is similar to the existing MUX based decoder, the same bubble correction circuit that was used for MUX based decoder in [14] can be used for the proposed improved MUX based decoder. Figure 10 shows the bubble error correction circuits for single bubble and double bubble error respectively. In the Figure 10 T1-T8 signals represents thermometer code with bubble errors.

C. Self-Reconfigurable Property The proposed thermometer to binary decoder is designed by grouping the signals generated from the smaller thermometer to binary converters. Hence the proposed decoder has a unique self reconfigurable property. Consider a 15-bit thermometer to binary decoders shown in the Figure 9(d). These decoders can be configured to operate as a 7-bit thermometer to binary decoders by making the MSB bits T8-T15 as logic zero. Since the MSB bits are tied to logic zero the gates to which these signals are fed do not have switching activity. The gates with switching activity for the existing and proposed decoders are shown in grey in the Figure 9. The Table II shows the number of gates with switching activity for different decoders, when 15-bit decoders are used to operate on Thermometer codes of 7-bit i.e. when 4-bit flash ADC is used for 3-bit resolution.
TABLE II. GATES WITH SWITCHING ACTIVITY FOR LOWER RESOLUTION OPERATION
Decoder Wallace Tree Fat Tree Decoder Existing MUX-based Proposed MUX-based No. gates with switching activity 21 18 11 7

15-bit decoders used as 7-bit decoder by zero padding (Figure 6)

As seen from the Table II the gates with switching activity are less in the proposed decoder when compared to

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TABLE III. SIMULATION RESULTS FOR 63-BIT (FOR 6-BIT FLASH ADC) THERMOMETER TO BINARY DECODERS FOR SLOW_NORMAL LIBRARY Delay (nS) Wallace Tree Fat Tree Existing MUX Based Proposed 1.926 0.701 1.021 0.546 Area (m2) 1276.430 752.170 361.973 361.973 Power (W) 351.428 62.412 44.745 44.732 Power-Delay Product (fJ) 676.850 43.751 45.685 24.424

TABLE IV. SIMULATION RESULTS FOR 63-BIT (6-BIT RESOLUTION) THERMOMETER TO BINARY DECODERS FOR SLOW_HIGHVT LIBRARY Figure 10. Circuit for (a) Single Bubble Error Correction. (b) Double Bubble Error Correction. Delay (nS) Wallace Tree Fat Tree Existing MUX Based Proposed 2.582 0.931 1.334 0.752 Area (m2) 1276.430 752.170 361.973 361.973 Power (W) 340.879 60.054 42.953 42.565 Power-Delay Product (fJ) 880.15 55.910 57.299 32.009

E. Heterogenous Decoders In the proposed methodology of designing thermometer to binary decoders for flash ADC, smaller decoders were used to implement larger decoders as shown in the Figure 8. Any of the existing decoders like Wallace tree decoder or Fat tree decoder can be used for implementing the smaller decoders. This results in a family of heterogeneous decoders. Consider as an example a 7-bit decoder shown in Figure 5. The dotted block in the Figure 5 indicates a 3-bit MUX based decoder. This 3-bit decoder can be a fat tree based decoder of a Wallace tree based decoder. One such implementation which uses a combination of 3bit counter and proposed methodology is shown in the Figure 11. Since the selection signal used for MUXs is critical they can be made bubble tolerant. The remaining signals are used as inputs to a 3-bit counter.

Wallace tree decoder has more power, area and delay compared to the other architectures. Delay of the fat tree based decoder falls in between the proposed architecture and the existing MUX based decoder. Because of its inherent tree structure, the area occupied by the fat tree based decoder is more compared to existing MUX based and proposed decoder. The design presented in [12] optimizes the fat tree based decoder at transistor level using pseudo dynamic CMOS logic. In this paper, we have concentrated on gate level implementation of the design and hence comparison of [12] with the proposed decoder has not been done. Although the proposed and existing MUX based decoders have same area, the proposed decoder results in lower delay, as it removes high fan-out in the critical path which the existing MUX based decoder suffers from. The proposed architecture has the same number of gates as the existing MUX based design and hence the power dissipated by both the decoders is almost the same.

Figure 11. Heterogeneous Decoder

IV.

SIMULATION RESULTS AND COMPARISIONS

All the architectures were structurally described using Verilog HDL and simulated using Cadence Incisive Unified Simulator (IUS) v6.1 covering all functional combinations. The designs were mapped on the TSMC 180nm Technology with slow_normal library (operating conditions 1.8 V, 25C), and slow_highVt(operating conditions 0.9 V, 125oC) using Cadence RTL Compiler v7.1.The power analysis is done on all designs with 50% toggle rate at 500MHz frequency. Table III and IV show simulation results for all the architectures for 63-bit thermometer to binary decoders i.e., for a 6-bit resolution, for slow_normal and slow_highvt libraries respectively.

A. Power Results for re-configurability The table V and VI show the power consumption of all the decoders of 63-bit length (for 6-bit flash ADC), when operated for lesser bit lengths i.e., for different resolutions, for slow_normal and slow_highvt libraries respectively. The existing MUX based decoder has no selfreconfigurable property. This results in higher power consumption for lower resolution inputs when compared to fat tree and proposed decoders. The power consumption of the existing MUX based decoder for lower resolution is lower than its higher resolution counterpart because the activity is less in lower resolution inputs. Wallace tree, fat tree and proposed decoders have selfreconfigurable property as discussed in section III. But the number of gates the Wallace tree and fat tree based decoders

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require is high, when compared to the proposed decoder and hence consume more power.
TABLE V. POWER CONSUMPTION FOR DIFFERENT OPERAND LENGTHS IN SLOW_NORMAL CORNER LIBRARY. ALL UNITS ARE IN W 7-bit (for 3-bit flash ADC) 56.516 9.737 11.523 8.413 15-bit (for 4-bit flash ADC) 104.859 17.048 19.995 13.571 31-bit (for 5-bit flash ADC) 184.889 31.812 32.202 23.538

thermometer to binary decoders. It can be configured to operate on thermometer code with reduced length without any extra overhead which is suitable for adaptive resolution analog to digital converters. Simulation results indicate that the proposed decoder results in better performance when compared to the existing decoders in terms of power, delay and area.
[1]

Wallace Tree Fat Tree Existing MUX Based Proposed TABLE VI.

[2]

POWER CONSUMPTION FOR DIFFERENT OPERAND LENGTHS IN SLOW_HIGHVT CORNER LIBRARY. ALL UNITS ARE IN W 7-bit (for 3-bit flash ADC) 50.702 7.229 10.055 7.013 15-bit (for 4-bit flash ADC) 98.317 14.558 18.363 12.116 31-bit (for 5-bit flash ADC) 177.047 29.367 30.107 21.979

[3]

Wallace Tree Fat Tree Existing MUX Based Proposed

[4]

[5]

B. Bubble Error Correction Results The tables VII and VIII show the results of the proposed decoder with single and double error bubble correction circuits shown in Figure 7.
TABLE VII. SIMULATION RESULTS FOR PROPOSED DECODER WITH SINGLE AND DOUBLE BUBBLE ERROR CORRECTION IN SLOW_NORMAL
LIBRARY

[6]

[7]

Bubble Error Correction Single Double

Delay (nS) 0.698 0.739

Area (m2) 580.709 624.456

Power (W) 63.028 52.278

Power-Delay Product (fJ) 43.994 38.633

[8]

[9]

TABLE VIII. SIMULATION RESULTS FOR PROPOSED DECODER WITH SINGLE AND DOUBLE BUBBLE ERROR CORRECTION IN SLOW_HIGHVT
LIBRARY

Bubble Error Correction Single Double

Delay (nS) 0.950 1.006

Area (m2) 580.709 624.456

Power (W) 54.672 49.443

Power-Delay Product (fJ) 51.9384 49.740

[10]

[11]

The proposed decoder with single bubble correction circuit has 21.7%, 37.9% and 29% delay, area and power overheads respectively under slow_normal library conditions. The proposed decoder with double bubble correction circuit has 26.1%, 42.15% and 14.4%delay, area and power overheads respectively under slow_normal library conditions. V. CONCLUSION

[12]

[13]

[14]

A new improved multiplexer based decoder for flash analog-to-digital converters is proposed, which converts thermometer code to binary code. The proposed decoder is designed by grouping the signals generated from the smaller

[15]

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