David W.

Parent

EE Department 1 Washington Sq SJSU San Jose CA, 95192

Phone 408.924.3963

Fax 408.924.3963

Documentation for Spartan Semiconductor Services NMOS Mask Set.

Chapter

Documentation for NMOS Mask Set

Top View
In Figure 1, we see the legend use for this mask set. Mask 1 consists of GDS layer 1 XORED with GDS layer 49 and the digitized data is clear. This means all non-common areas between GDS 1 and 49 will have an open widow and light from the aligner is allowed through these areas. All other areas of the mask will be chrome. Mask 1 is the N+ Source/Drain/Resistor step. Mask 2 consists of GDS layer 2 XORED with GDS layer 49. The digitized data is clear is the same manner as Mask 1. This is the gate etch step. This step also Pre-Etches the contact step. Mask 2 is aligned to Mask 1. Mask 3 consists of GDS layer 3 XORED with GDS layer 49. The digitized data is clear is the same manner as Mask 1. This is the contact etch step and is aligned to Mask 1. Mask4 consists of GDS layer 4 only and the data is digitized dark. This means that wherever layer 4 is drawn will be chrome on the mask and block light from passing through the mask. Mask 4 is aligned to Mask 3.

 Figure 1: Legend

In Figure 2, we see the complete view of all layers of the mask set over the whole 4 wafer. The three process widows are in the top third of the wafer and are labeled as S/D, GATE, and CONT. Note that the CONT window will be pre-etched during the GATE step (Mask 2) so after mask two there will be all three process widows will be visible. The alignment marks can be seen at the extremes of the horizontal axis of the wafer (The areas inside the purple regions.). There are addition alignment marks along the centerline as well for processing smaller diameter wafers. The four big squares in the alignment marks are just to help the operator to find the much smaller alignment marks set inbetween them. There are also seven sets of PL test structures (The red yellow and blue features.). The blue squares are 40 pin test structures. There are six different test structures. The first is the Material test structure, which appears almost all blue with a little bit of green. The second is the DEVICE1 block, which has transistors and diodes and BJTs. The third is the DEVICE2 block and contains transistors with a gate length of 16 microns arranged to examine orientation effects. The forth is the DEVICE3 block which contains transistors with a minimum gate lenth of 32 microns to examine orientation effects. The fifth block the DEVICE4 block, which contains transistor witth the source and body shorted, and the gate and drain shorted. The gate lengths vary from 6 microns to 14 and are arranged to look at orientation effects as well. The LOGIC block consists of inverters, nand gates and ring oscillators. The blocks are laid out in rows from left to right in this order: MATERIAL, DEVICE1, DEVICE2, DEVICE3, DEVICE4 followed by LOGIC. Each column consists of one type of test block. It should be very easy to divide the testing to row and column addresses. The blocks are clearly labeled.

Figure 2: Complete View of all layers of the complete 4 wafer. 3

Alignment Marks
In Figure 3, we see the top view of the alignment marks. The four big squares which appear orange (due to the fact that all the layers are have these large squares and the colors bleed through.). The alignment marks that will be used are in the center of the cross formed by the four squares. The four squares will be chrome and surrounded by a clear region are used to help set up the mask set for alignment.

Figure 3: Top view of alignment marks.

In Figure 4, we see the conventional alignment marks to be used. Mask two should be aligned using the marks with two sets of squares in squares and checkerboard. Mask three uses the row that has three sets of squares in squares and checkerboards. Mask 4 uses the row with four of these features. For convenience, which row to line up to will be printed on the wafer. In addition, the alignment marks for a given mask are spaced differently so that it should be impossible to align to the wrong layer.

Figure 4: Conventional Alignment marks.

PL Test Structures
In Figure 5, we see all the test structures use to check alignment, and registration of the PL process.

Figure 5: Top view of the PL test structures.

In Figure 6, we can see the LBAR test structures to check how well the PL process can replicate long features, and corners. The structures are 3, 4, and 8 microns wide.

Figure 6: LBAR PL test structures.

In Figure 7, we see the test features for the proximity effect. The proximity effect can be seen as a narrowing of the middle line sandwiched between the two squares. This set contains 3 micron featrues and four micron features.

Figure 7: Test Structure for Proximity Effect.

In Figure 8, we see structures for contact like structures. Even though these features appear in every layer, they are only really important for the contact layer(Mask 3). In addition, since the contacts for our devices are 16 microns across, these test features are too small to optimize our =8m process. It should also be noted that one can not optimize the CONTACT PL and the LBAR PL at the same time. The features are there so that a comparison can be made between contacts form with optimized and non-optimized conditions. One should also compare the contacts formed in the center of the mass of contacts and the insolated contacts. This set contains features of 3, 4, and 8 microns.

Figure 8: Contact Test Structure.

In Figure 9, we see a standard needle structure used for measuring how close two objects can be placed. The needle will disappear if the PL process is not working for a particular separation. The needles start at 7 microns separation and progress down wards from 6, 5, 4, and 3 microns.

Figure 9: Needle Test Structure for Registration.

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In Figure 10, we see a test structure used to monitor how well the metal lines are able to go over steps in oxide thickness. The structures are the same width a the LBAR cell.

Figure 10: Step Coverage Test Structure.

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In Figure 11, we see test structures use to measure the resolution of the PL process. As long as the 8-micron features are present and not washed out the devices will work. On Mask 1 it would be best if at least the 6 microns features came our properly, other wise the short channel effect devices will not work.

Figure 11: Conventional Registration Marks.

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In Figure 12, we see the old style alignment check features. It is hard to measure absolute misalignment with these features, although it is easy to see how line width varies from mask to mask.

Figure 12: Alignment Test Structures.

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In Figure 13, we see a Vernier Gage with four-micron resolution. If the alignment is done correctly it will look Figure 13, if not cont how many periods of the gage it takes to line up one bar inside of two bars and multiply by 4 microns. This will tell you how far off the alignment is.

Figure 13: Four Micron Vernier Gages.

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In Figure 14 we see Vernier gages with 1 micron resolution.

Figure 14: 1 Micron Vernier Gages.

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In Figure 15, we see Vernier gages with .5 micron resolution.

Figure 15: .5 Micron Vernier Gages.

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Material Block
The material block consists of devices or structures that can be used to determine material constants electrically. In Figure 16, we see the top view of the MATERIAL block. The pins are labeled. Pin 2 is the common ground for resistors 1 through 6. R1 through R6 are connected to pins 11 down to 6. The MOS capacitors have to be tested with two probes (not the probe card). The Metal Van Der Pauw Structure has the following connections: A to 15, B to 12, C to22, and d to 20. The N+ Van Der Pauw Structure is connected as follows: A to 31, B to 40, C to37, D to 32.

Figure 16: Top View of Material Block.

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In Figure 17, we see the resistor test block the widths and lengths are clearly labeled. Some things to examine (Include in a report.) would be to extract the contact resistance, and the sheet resistance of the resistors. Do these values vary across the wafer? How do these items vary? Do they vary from wafer to wafer? If these items vary, can you see a pattern to it? For a constant resistor width, does the resistance increase with resistor length? For a constant resistor length, does the resistance decrease with decreasing width? Try to come up with an explanation as to why these values vary.

Figure 17: Top View of Resistors.

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In Figure 18, we see a Van Der Pauw test structure to determine sheet resistivity of the metal layer. The sheet resistivity is given by Rs = / ln (2) VCD/IAB . The equation can be programmed into the HP 4145 analyzer and you can extract Rs automatically. The Sheet resistivity is related to the thicknes of the metal layer and the conditions it was applied. Try to find the wafer to wafer, and the on wafer variance of the sheet resistivity. Try to explain why there is a variance to this parameter from wafer to wafer and on wafer.

Figure 18: Metal 1 Van Der Pauw Test Structure.

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In Figure 19, we see the Van Der Pauw test structure for the n+ diffused layer.

Figure 19: Van Der Pauw n+ Test Structure.

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In Figure 20, we see the Field oxide and Gate oxide MOS capacitor test structures. From these devices, you should be able to determine substrate doping, fixed oxide charge, and long channel threshold voltage. Compare the threshold voltage of the gate oxide to that extracted from the transistors. Is it the same? Explain why there are differences. Does this vary from wafer to wafer and on wafer? Is the field oxide MOS VT larger than the gate VT. Explain why or why not. The gate oxide area is 180 by 380 microns. The field oxide area is 200 by 400 microns.

Figure 20: MOS Capacitor Test Structures.

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Device 1 Block
The Device 1 Block contains various sized MOSETS, BJTS and Diodes. In Figure 21 we see the top view of this block. The pins for each device are labeled. The multi labels pins for the diodes are common. The first MOSFET has its Drain connected to pin 1, the gate to pin 2, the source to pin 3 and the body to pin 5. This sequence repeats itself around the chip until the diodes at pins 33 through 40. The BJTs can not be tested with the probe card. This test block can be used to generate MOSFET, BJT and Diode curves. VT, KP and gm can be extracted from the MOSFETS. Current gain can be extracted from the BJTs. Breakdown voltage, ideality factor, reverse saturation current, and series resistance can be extracted from the diodes. Capacitance of the diffused regions can also be extracted.

Figure 21: Device 1 Block.

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In Figure 22, we see a MOSFET with an as drawn channel length of 16 microns and an as drawn channel width of 32 microns.

Figure 22: 32/16 MOSFET.

In Figure 23, we see a MOSFET with an as drawn channel length of 16 microns and an as drawn channel width of 64 microns.

Figure 23: 64/16 MOSFET

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In Figure 24, we see a MOSFET with an as drawn channel length of 16 microns and an as drawn channel width of 128 microns.

Figure 24: 128/16 MOSFET

In Figure 25, we see a MOSFET with an as drawn channel length of 32 microns and an as drawn channel width of 32 microns.

Figure 25: 32/32 MOSFET

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In Figure 26, we see a MOSFET with an as drawn channel length of 32 microns and an as drawn channel width of 64 microns.

Figure 26: 64/32 MOSFET

In Figure 28, we see a MOSFET with an as drawn channel length of 32 microns and an as drawn channel width of 64 microns.

Figure 27: 128/32 MOSFET

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In Figure 26, we see a MOSFET with an as drawn channel length of 32 microns and an as drawn channel width of 256 microns.

Figure 28: 256/32 MOSFET

One thing to check for by testing all these MOSFETS is, does the measured drain current scale properly with the as drawn channel length and width? We know the channel length is reduced by the diffusion of phosphorous, but how much is it reduced? Is is the same over all the wafers?

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In Figure 29, we see BJT test structures. Extract the current gain for each BJT. Does the gain change with orientation of the BJT? Does it change from wafer to wafer? For the two emitter BJT, what is the relationship between the collector current and each emitter current?

Figure 29: BJT Test Structure.

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In we see diode test structures. One is opened up to act as a photo detector, and the other is covered in metal. What are the differences is reverse saturation current and RS. Are there any other differences between these two diodes?

Figure 30: Diode Test Structure.

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Device 2 Block
The Device 2 Block contains various sized MOSETS arranged with a common ground are oriented 90 degrees to one another. The test to perform here is weather you can find any change in threshold voltage, KP or gm for devices oriented in different directions. Figure 31 shows the layout of the block. The pins are labeled and the transistor channel lengths are 16 microns. C

Figure 31: Device 2 Block

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In Figure 32, we see how the transistors are wired and laid out.

Figure 32: 16 Micron Channel Length MOSFET Test Structure.

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Device 3 Block
The Device 3 Block contains various sized MOSETS arranged with a common ground are oriented 90 degrees to one another. The test to perform here is weather you can find any change in threshold voltage, KP or gm for devices oriented in different directions. Figure 31 shows the layout of the block. The pins are labeled and the transistor channel lengths are 32 microns.

Figure 33: Device 3 Block

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In we see the 32-micron channel length transistors.

Figure 34: 32-micron Channel Length MOSFETs

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Device 4 Block
The Device 4 Block contains various sized MOSETS arranged with the source and grounds pre-wired as well as the gates and drains. This means that you only need to apply a voltage and measure a current with only two pins. It also means that one the gate voltage is above the threshold voltage the devices will only operate in saturation mode. VT, KP can be quickly determined from this type of measurement. Furthermore, the gate length is varied from 6 microns to 14 in steps of 2 microns. You should be able to extract how the threshold voltage changes with channel length. The are four sets of devices oriented at 0 , 90, 180 and 270 degrees to check for orientation effects due to alignment errors.

Figure 35: Device 4 Block

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In Figure 36, we see how the transistors are wired and laid out. Notice how the gate and drain metal are connected.

Figure 36: MOSFETS wired up for saturation mode operation.

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Logic Block
The Logic Block contains inverters, nand gates and ring oscillators in enhancement mode load logic. The load resistor of a nmos inverter is replaced with a MOSFET with gate and drains tied together. Things to test the inverters, and nands gates for are: what voltage does vout equal vin, vout when the logic is high, vout when the logic is low, and check that the logic is correct. The pins are all labeled. A, B, and C are input pins, while Y is all way an output pin. Figure 37, shows all the gates in the block. You can extract propagation delay from the ring oscillator.

Figure 37: Logic Block.

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In Figure 38, we see an inverter.

Figure 38: Inverter 1 Gate.

In Figure 39, we see an inverter with the same load to driver ratio, but the channel lengths and widths are doubled.

Figure 39: Inverter 2 Gate

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In Figure 40, we see a two input nand gate.

Figure 40: 2 input nand gate

In Figure 41, we see a three input nand gate.

Figure 41: 3 input nand gate

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In Figure 42, we see a ring oscillator test structure. The propagation delay should equal the period of the square wave out put divided by twice the number of inverter stages. Tp=Period/2*33 in this case.

Figure 42: Ring Oscillator Circuit.

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