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SPECIAL ASSIGNMENT SPI Slave VHDL Project

Serial Peripheral Interface, SPI, is a synchronous serial data link standard, designed and developed by MOTOROLA. It is used for serial communication in full duplex mode, i.e. transmission and reception happens simultaneously over two different buses. The devices communicate in master/slave mode where the Master initiates the data frame and supplies the clock to the slave. SPI is also called as four-wired communication Slave clock (SCK), Master Out Slave In (MOSI), Master In Slave Out (MISO) and Slave Select (SS). Multiple slaves can be connected depending upon the availability of SS pins in the Master interface.

Fig. 1: SPI: Single Master and Single Slave

Serial interfaces are preferred over parallel interfaces as they have simpler wiring. A 4 bit communication between two devices would require at least 4 wires between them for parallel communication. Moreover, due to higher wiring, there are more chances of crosstalk between the wires and hence, significantly reduce the signal quality at either end. Basically, the SPI interface contains: SCLK: Serial Clock (Master output) MOSI: Master output, Slave Input MISO: Master Input, Slave Output SS: Slave Select (Master output, active low)

SPI bus can operate with multiple slave devices, although the Master is always one. By keeping the SS pin at LOW, the corresponding slave is selected for communication. The Slave MISO pin has three states HIGH, LOW, HI-Z. When the Slave is not selected, the MISO pin is logically disconnected (HI-Z). This configuration is particularly useful when multiple slaves are to be connected.

To begin communication, the Master first fixes the clock frequency (SCLK). The clock frequency should not be more than what the Slave supports. Generally these frequencies are in the range 1 100 MHz. Next, a logic LOW is transmitted over the SS pin by the master to select the corresponding Slave. This activates the Slave and the hardware is ready for communication. Then, at every triggering edge of the SCLK, full duplex communication occurs: Master sends data on the MOSI line, slave reads it from the same line Slave sends data on the MISO line, master reads it from the same line

Communication involves 2 different registers, one in the master and other in slave. The MSB of memory of each device is transmitted over their corresponding channel while the received bit is moved into the LSB. Transmission occurs for the entire duration of SCLK. When entire data has been interchanged, the master stops toggling SCLK and then deselects the slave.

Fig 2: Full Duplex Communication

In FPGA, it is possible to implement full SPI communication using two different kits one configured as the master and the other as slave. The following code illustrates the VHDL code for configuring CPLD kit as a slave. The slave has been given inputs as SCLK, MOSI, CS and Receive/Transmit. It first defines the mode of operation by EX-ORing cpol and cpha that define the active triggering edge of SCLK. If the Mode is 1 then transmission occurs at falling edge of SCLK while the data is read from MOSI at the rising edge of SCLK and vice versa. When the reset is LOW, the slave is cleared of all the previous data it may have stored and its output MISO pin is disconnected from the circuit. As soon as the reset pin is HIGH and the Slave select (CS) pin is LOW, the internal memory specified by Data_Reg shifts towards MSB while taking input from MOSI to fill LSB or setting it to 0 during receiving or transmitting mode,

respectively. During the immediate next triggering edge, if the slave is in transmit mode, it will move its MSB onto the MISO pin.

-------------------------LIBRARY-----------------------library ieee; use ieee.std_logic_1164.all;

-------------------------ENTITY------------------------entity SPI_Slave is GENERIC (cpol cpha PORT (reset rec0trans1 MOSI, CS, SCK MISO end SPI_Slave; : BIT := '0'; : BIT := '0'); : in std_logic; : in std_logic; : in std_logic; : out std_logic); -- Set clock polarity -- Set clock phase -- Active Low Reset pin -- set '0' for MOSI, '1' for MISO

----------------------ARCHITECTURE---------------------architecture behavioral of SPI_Slave is signal clk signal Mode signal Data_Reg begin Mode <= cpol XOR cpha; -- '1' for reading on falling edge, : BIT ; : std_logic_vector(7 downto 0); -- Internal 8 bit memory : std_logic;

-- '0' for reading on rising edge process (SCK, rec0trans1, Mode) begin if((Mode = '1' AND rec0trans1 = '1') OR (Mode = '0' AND rec0trans1 = '0')) then clk <= not SCK; elsif((Mode = '1' AND rec0trans1 = '0') OR (Mode = '0' AND rec0trans1 = '1')) then clk <= SCK; end if; end process;

process(CS, rec0trans1, clk, reset) begin if (reset = '0') then Data_Reg <= (OTHERS => '0'); MISO <= 'Z'; elsif(CS = '0') then if rising_edge(clk) then Data_Reg <= Data_Reg(6 downto 0) & '0'; if rec0trans1 = '0' then Data_Reg(0) <= MOSI; end if; end if; end if; end process; -- Move MOSI into LSB -- Shift Data elements by 1 bit each -- active LOW chip/slave select -- Active Low Reset Pin -- Clear internal memory

process(CS, clk, reset, rec0trans1) begin if(reset = '0') then MISO <= 'Z'; elsif(CS = '0') then if falling_edge(clk) AND rec0trans1 = '1' then MISO <= Data_Reg(7); end if; end if; end process; end behavioral; -- while transmitting, -- move MSB out of internal memory