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Improved Hysteresis Current Control of a Single

Phase, Three Level, Double PFC Converter


Alberto S Lock, Edison R. da Silva.
IIFIEE, Faculty of Electrical and Electronics Engineering. Dept. of Electr. Engineering/CCT,
University National of Engineering, UNI Lima, Peru Universidade Federal de Campina Grande. Brazil
asoto@uni.edu.pe edison@dee.ufcg.edu.br
Abstract - Single ended, single phase, Power Factor Corrector (PFC)
Boost Converter, is one of the most popular AC/DC converters,
because of a number of advantages i.e. its step up voltage ratio,
simplest topology and high efficiency. However, for high voltage or
high power applications, three level PFC converter is one of the most
promising solutions. For high power applications, current operation
frequency and Bandwidth must be limited to avoid Electromagnetic
EMI interference. This paper presents a fixed frequency hysteresis
current control for Three level Single-Phase, Boost double PFC
Converter. The proposed methodoly presents hysteresis current
control with adaptive band error to constrain switching frequency for
a given range. A fast response, a relative small bandwidth and reduced
harmonic content are qualities of the technique proposed;
furthermore, coupling Output Voltage problem is avoided, by means of
compensating current reference. Simulation results confirm the
proposed technique.
I. INTRODUCTION
Conventional rectifiers have low power factor which produce reactive
power and reduces the power available from the utility grid. At the same
time, high harmonic distortion of the line current causes Electromagnetic
Interference EMI problems and cross-interferences, as well as equipment
overcurrents and overvoltages through the line impedance, among different
systems connected to the same grid. In order to meet the requirements in
the proposed standards, on quality of the input current which can be drawn
by low-power equipment, a PFC circuit is typically added at the utility
interface of an AC/DC switch-mode power supply, as well as
Uninterruptible Power Supplies UPS, Motor Controllers and currently to
any equipment using an AC/DC converter. Power factor correction is being
increasingly required as a feature of new power supply designs. Power
factor correction takes the form of a new "front end" of power supplies,
adding circuitry to shape the input current into an image of the input
voltage and therefore making the power supply input look resistive to the
source, usually the AC mains. Harmonic currents produce costly losses in
main supply. High harmonic currents caused by simple rectifiers, which are
used in great number for TVs, PCs and many more electronic equipment,
can be corrected by PFCs. In case of harmonic currents produced by
controlled rectifiers with inductive loads such as DC control motors or
older solder machinery other solutions can be found. i.e. active or hybrid
power filters or Static VAR Compensators SVCs.
For PFC solutions the most common one is the single-ended boost
converter, because of a number of advantages, i.e. its step up voltage ratio,
simplest topology and high efficiency. The intermediate DC voltage should
be controlled, and the power factor from the main supply must be close to
one. But PFCs solutions need that converter must be introduced into
electronic equipment, so old electronic equipment that not meet the
regulation harmonic norms ought to be released, may be the exception is
UPS feeding old costly and sophisticate electronic equipment. However,
for both high voltage, high power applications, important problems arise
related to voltage stress across the switches, size of the boost inductor and
need to limited high conduction losses. Multilevel converters are an
important alternative because of their ability to meet both high power
ratings and share voltage stress across the switches. The former ones are
generally used for high power renewables[1-3], Flexible AC transmission
Systems FACTS[4-7], Active power filters APF[8-10] and motor
drives[11-12]. Three different topologies have been proposed for multilevel
converters[13,14]: diode-clamped(neutral clamped), capacitor
clamped(flying capacitors) and cascaded multicell with separated dc
sources. Fig.1. shows these topologies for single phase configuration.
Introducing three level (E/2,-E/2 and 0) and four switches and a few
diodes or capacitors per phase are used. For unidirectional three level
single phase AC/DC converter adopted, see Fig..2.b, number of power
switches is reduced to a half[15,16,19,20], switches voltage stresses are
limited to a half of DC bus, inductor boost is one fourth than that of the
conventional single-ended PFC converter[15] and its component number
is reduced, when compared to good performance bidirectional interleaved
converters such as Interleaved Half Bridge Boost converter and Interleaved
Full Bridge Boost converter recently investigated [17]. For high power
applications, high conduction losses and high switching losses are
produced. Furthermore, due to large di/dt and dv/dt, high frequency
harmonics are generated in radio frequency, RF range[18]. Although, soft
switching techniques[15] and switching table with conventional hysteresis
control[19,20] has been proposed for three level PFC converter, operation
frequency and Bandwidth need to be limited, to avoid EMI problems and
high conduction losses. On the other hand, a fixed frequency hysteresis
control has been proposed for driver motors[21-24], Active Power filters
APF[25] and single-ended PFC converter[26]. For driver machines, an
adaptive hysteresis-band current depending of load and supply parameters
is described in [21]. While in [22-24]it has been proposed a programmable
hysteresis-band current by using a phase-locked loop (PLL). A load
independent fixed frequency hysteresis control is proposed in [27], while
for three level single-phase inverter, this technique is proposed in [28].
In this paper, fixed frequency hysteresis control is proposed for single-
phase Unidirectional three level PFC converter, an adaptive hysteresis
band, independent of load and supply parameters is used to constrain
switching frequency to a fixed frequency value. Voltage interference
problem is avoided compensating current reference for isolated input
voltage of diode bridge. The proposed technique is confirmed by
simulation and experimental results. The present work is divided into three
following mains issues: Section II presents three level boost PFC operation
modes, Section III presents full analytical development for fixed frequency
Hysteresis control for adopted converter. Section IV presents simulation
and experimental results
II. THREE LEVEL DOUBLE BOOST PFC
Double PFC converter as show in Fig.2.(a) can be seen as a two level
converter[29] while its equivalent circuit described in Fig.2.(b) can be seen
as a three level converter[15,16,19,20]. Fig.2.(c) shows Operation Regions.
As a three level converter, circuit show in Fig.2.(b) presents four operation
modes:
i) S
1
On, S
2
On
Switches S
1
and S
2
are turned on. Voltages e
1
and e
2
are set to zero. Inductor
current increases due that it is shunted to rectified voltage(V
1
-V
2
). Diodes
D
1
and D
2
are turned off. Capacitor voltages V
01
and V
02
decreases due that
they are discharging on load R
L
.
Fig.1.Three level single phase converters (a)Diode clamped converter
(b)Capacitor clamped converter (c)Cascaded converter.
ii) S
1
On, S
2
Off
Switch S
1
is turned On, while switch S
2
is turned Off. Voltages e
1
and e
2
are
set to zero and V
02
respectively. Inductor voltage V
L
= _V
in
_-V
02
is so
that inductor current I
1
increases when _V
in
_>V
02
and decreases when
_V
in
_<V
02
. Diode D
1
is turned off, while diode D
2
is turned on. Capacitor
voltage V
01
decreases via R
L
and capacitor voltage V
02
increases via
inductor current I
2
=I
1
.
iii) S
1
Off, S
2
On
Switch S
1
is turned Off, while switch S
2
is turned On. Voltages e
1
and e
2
are
set to V
01
and zero respectively.
Inductor voltage V
L
= _V
in
_-V
02
is so that inductor current I
1
increases when
_V
in
_>V
01
and decreases when _V
in
_<V
01
. Diode D
1
is turned Off, while diode
1326 1-4244-0655-2/07/$20.002007 IEEE
Fig.2. Double PFC converter (a) As a two level converter (b) As a three
Level converter (c) Operation Regions.
D
2
is turned On. Capacitor voltage V
01
increases via inductor current I
2
=I
1
and capacitor voltage V
02
decreases via R
L
.
iv) S
1
Off, S
2
Off
Switches S
1
and S
2
are turned Off. Voltages e
1
and e
2
are set to V
01
and V
02
respectably. Inductor current decreases due that ,V
in
,-V
0
. Diodes D
1
and D
2
are turned On. Capacitor voltages V
01
and V
02
increase via (I
1
-V
0
/R
L
)
current.
In addition, this converter can operate in two regions named Region I and
II, according to the output voltage converter be bigger or smaller than two
times the rectifier input voltage, as is show in Fig.2.(c). In Fig.3. it is show
operation waveforms.
a) REGION I (V
0
>2|V
in
|)
In this region, each capacitor voltage V
01
and V
02
must be greater than
rectifier voltage V
in
. As Fig.3.(a) shows, increasing inductor current is
obtained when S
1
On, S
2
On, at time t
0
(capacitor voltages V
01
, V
02
decrease) decreasing inductor current is obtained when S
1
On, S
2
Off or
S
1
Off, S
2
On. Due that inductor voltage is,V
in
, for S
1
On, S
2
On,
capacitor voltages charge via a great stored inductor current when S
1
On,
S
2
Off, at time t
1
, increasing capacitor voltage V
02
(V
01
decreases). Or
when S
1
Off, S
2
On, at time t
3
increasing capacitor voltage V
01
(V
02
decreases). At time t2, operation mode S
1
On, S
2
On must be repeated to
keep Region I.
b) REGION II (V
0
<2|V
in
|)
In Region II, inductor voltage can be ,V
in
,-V
01
or ,V
in
,-V
02
. As Fig.3.(b)
shows, inductor current increases when a) S
1
On, S
2
Off, at time t
0
,
(capacitor voltage V
01
decreases, V
02
increases) b)S
1
Off, S
2
On at time
t
2
, (capacitor voltage V
01
increases, V
02
decreases). Inductor current
decreases when S
1
Off, S
2
Off at time t
1
and t
3
(capacitor voltages V
01
,
V
02
increase)
III. PRINCIPLE OF OPERATION OF HYSTERIC CURRENT
CONTROL WITH FIXED SWITCHING FREQUENCY
As for implementation of the conventional hysteric control it is needed to
sense the current permanently and to compare it with a reference as show
in Fig.3. Current control works in such a way that oscillates between two
limits: an upper limit P
rd1
(until switch S1 is Off) and a lower limit P
rd1
*(1-
H
B
) (until switch S1 is On). H
B
is the hysteresis Band error. Conventional
multiloop control is used, to obtain the PFC major goals: an inner loop for
current control (input current in phase with input voltage) and an outer loop
for DC link voltage control (output capacitor voltage settle to a desired
value). Fig.4. shows a block diagram of this control.
Therefore:
Off S P I
rd
>
1 1 1
:

(1)
On S H P I
B rd
<
1 1 1
: )) 1 ( * (

(2)
)) / ( * ) (( *
01
*
01 1
s K K V V V P
I p in rd
+ =

(3)
K
p
and K
I
are proportional and integral gain respectively.
For hysteresis control of fixed switching frequency, switching period T
S
for
regions I and II is found at first, then conditioned to set of equations (1-3).
As it can be see in Fig.2.(b), neutral point of input rectified voltages are
isolated from output reference, so output converter voltage interact
between them. Consider the load equation:
1
1
1 1
e
dt
di
L ri V V
IS
+ + = +
(4)
2 2
) (
2 1 in
IS
V V V
V =

=
(5)
In order to model the converter, T
S
is found at first from (4) assuming
V
IS
=0, secondly T
S
is found when V
1
=0, and later considering both effects:
i) CASE V
IS
=0
This case is equivalent to assume that middle point of output of diode
bridge is connected to ground, i.e by means of a middle point transformer.
Then, it is obtained from (5):
dt
di
L ri V e
1
1 1 1
=
(6)
Instantaneous values of e
1
, as depends on switch state S
1
, it can take values
of zero and V
01
. But, if a current reference i
1
* is assumed, a voltage
reference e
1
* could exist, to obtain the desired current reference i
1
*
dt
di
L ri V e
*
1
*
1 1
*
1
=
(7)
Subtracting (8) from (7):
dt
d
L r e e
1
1 1
*
1
c
c =
(8)
1
*
1 1
i i = c (9)
If a reasonably high switching frequency is assumed (r<<eL) r ~0 can be
neglected, and as operation of hysteresis current controller, show in Fig.3,
consists of straight lines because of short period of time considered:
t
L
dt
d
L e e
A
A
= =
1 1
1
*
1
c c
(10)
To find T
S
in Region I, (11) is applied to Fig.3.(a):
| |
| |
| |
| |
1 1 1
1 1 1
*
1
0
0
) 0 ( ) (
0
t
LH
t
H
L
t
t
L e
B B
=

=
c c
(11)
| |
| | ) 2 / ( 2 /
) ( ) 2 / (
1 1
1 1 1
01
*
1
S
B
S
S
T t
LH
t T
t T
L V e

=
c c
(12)
Fig.3. (a) Operation modes for Region I (b) Operation modes for Region II
1327
Fig.4. Block diagram of conventional Boost converter
From (11) and (12):
) 1 (
2
01
*
1 *
1
V
e
e
LH
T
B
S

(13)
Therefore, to keep constant f
S
=1/T
S,
H
B
must vary according to:
) / 1 (
01
*
1
*
1
V e e H H
m B B
(14)
H
Bm
is the amplitude of Hysteresis Band error.
To find T
S
in Region II, (11) is applied to Fig.3.(b)
> @
> @
1 1
1 1 1
*
1
0
) 0 ( ) (
0
t
LH
t
t
L e
B


H H
(15)
> @
> @ ) 2 / ( 2 /
) ( ) 2 / (
1 1
1 1 1
01
*
1
S
B
S
S
T t
LH
t T
t T
L V e


H H
(16)
As Expression (11) is equal to (15) and Expression (12) is equal to (16) it
can be seen that Expressions (13) and (14) are satisfied for both of
Regions I and II.
Therefore, switching period T
S
, and Band error width H
B
, are the same for
both of these regions. Substituting (11) into (14):

01
1
1
1
1
/ ) ( 1 ) (
2
V
dt
d
L e
dt
d
L e
LH
T
B
S
H H
(17)
(18) is expressed as a function of voltage across switch S
1
and error
current H
1
. So, H
B
now must have the form:


01
1
1
1
1
/ ) ( 1 ) ( V
dt
d
L e
dt
d
L e H H
m B B
H H
(18)
ii) CASE V
1
=0
In this case it is assumed there is not input voltage (V
in
=0) and middle
point and output of bridge diode is isolated from ground. Then, from
equation (4):
1
1
1
e
dt
di
L ri V
IS

(19)
Substituting (8) into (20):
) (
1
*
1 1
1
e e r
dt
d
L V
IS
H
H
(20)
If current error can be decoupled into two parts:
1 1 1
J [ H (21)
where
1
[ : non interacting error
1
J
: interacting error
Replacing (21) into (20):
) (
1
*
1 1 1
1 1
e e r r
dt
d
L
dt
d
L V
IS
J [
J [
(22)
Ignoring again r|0, and recognizing J
1
as a part of error current due to
isolated neutral point of input voltages:
dt
d
L e e
1
1
*
1
) (
[

(23.a)
dt
d
L V
IS
1
J

(23.b)
> @
in
V
sL
s V s V
sL 2
1
) ( ) (
2
1
2 1 1
J
(23.c)
Replacing
1
[ from (22) and replacing into (24.a) and (24.b):
IS
V e
dt
d
L e
dt
d
L e
*
1
1
1
1
*
1
J H
(24)
Replacing (24) into (17) and (18):
> @
01
*
1
*
1
/ ) ( 1 ) (
2
V V e V e
LH
T
IS IS
B
S

(25)
> @
01
*
1
*
1
/ ) ( 1 ) ( V V e V e H H
IS IS m B B

(26)
(25) gives switching period and once again for keeping fixed T
S
, H
B
must
varies according to (26).
In order to use (25) and (26) it can be useful to identify e*
1
of set of
equations (1)-(3). To keep fixed the switching frequency, hysteresis error
must be variable, therefore we can assume
*
1
e =K*P
rd1
, K is a
proportionality constant that takes the conversion units. Fig.5. shows a
block diagram with the system of control proposed based on the non
interacting error
1 1 1
J H [
IV. SIMULATION RESULTS
It was used PSCAD/EMTDC for simulation. Considering that for real
IGBTs, the maximum operation frequency is about 20KHz, and if
operation frequency is longer than 20KHz, current spikes could appear.
Simulations results are showed respecting the frequency limit. For fixed
hysteresis control, Fig.5. has been simulated with following values:
V
in
=220V(AC), 60Hz, r=0.01, L=1.8mH, C1=C2=820uF, R
L
=1000 .
Fig.6.(a) shows Hysteresis Band error H
B
. Fig.6.(b) shows input Voltage
V
in
and input current I
in
, which are in phase. Fig.6.(c) shows Input currents
I
in
, Fig.6.(d) shows rectifier input currents I1, I2 and its reference P
rd1
.
Fig.6.(e) shows switching frequency for gates of S
1
and S
2
. It is also show
from this figure that IGBTs could normally work without spikes. Fig.7.
shows Output DC voltage start-up, which is kept it without control during
an entire supply period. Fig.8. shows Fast Fourier Transform FFT for
Input current I
in
. For conventional hysteresis control, Fig.5. has been
modified for L=1.4mH. Fig.9. shows main electrical characteristics,
Fig.9.(a) shows Voltage Supply V
in
and input current, note that Fig. 9.(b)
shows switching frequency of switches S
1
and S
2
, but Fig.9.(c) shows this
frequency for a major period of time, trying to focus on their randomize
nature. Fig.10. shows hysteresis band error amplitude step response for
proposed system, note frequency change in Fig.10.(e).
V. CONCLUSIONS
In this paper an improved current control method for a three level PFC
converter has been proposed. Control method is based on fixed frequency
hysteresis current control which ensures low harmonic distortion, and a
limited hysteresis band error. For three level PFC converter, topology
adopted also ensures a good balance of output voltages[15].
For the proposed control method, a completed analytical development of
three level PFC converters and hysteresis current control of fixed
switching frequency is presented, as well as simulation results.
The Control method creates a variable hysteresis band error which
compensates operation current, for coupling between output voltages as
well as for floating voltages.
Fig.5. Block diagram for proposed control system
1328
Fig.6. Fixed frequency Hysteresis Control (a)Hysteresis band error H
B
(b)Input Voltage V
in
and Input Current I
in
(x10) (c)Input current waveform
(x10) (d)Rectifier Input currents I
1
, I
2
and reference current P
rd1
(e) Gates
Switching frequency of S
1
, S
2
(time:sec)
F
Fig.7. Output voltage start up for V
01
and V
02
.(time in sec)
Fig.8. Frequency Spectrum of Input current I
in
for Fixed frequency
Hysteresis Control
Fig.9. Conventional Hysteresis Control (a)Input Voltage V
in
and Input
Current I
in
(x10) (b) Gates Switching frequency of S
1
, S
2
(c) Gates Switching
frequency of S
1
, S
2
through a major period of time(sec)
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