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EE290C Spring 2011

Lecture 3: Basic Transmitters and Receivers

Elad Alon Dept. of EECS

Administrative
Elad will be out of town this Thurs.
Make-up lecture will be held on Mon. 1-31 1:30-3:00pm in 127 Dwinelle Office hours on Thurs. cancelled available over email

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Plain Old Inverters Why Not?

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Outline
Signaling Basics
Single-ended vs. differential Current-mode vs. Voltage-mode signaling Termination

RX Circuit Design
Comparator review Deserialization options

TX Circuit Design
Z control CML, VM drivers Power vs. swing Serialization options

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Single-Ended Signaling
rcvr din Cd ref Cr xmtr dout

RX: comparing against a shared reference


Reference may be implicit (i.e., ground/supply) Mismatch between shared and individual lines

TX: generates large variations on power supply


SSO simultaneous switching outputs

No XTALK immunity
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So Why Even Mention This?

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Classic Debate
Differential must be twice as fast as singleended in order to win Reality more complicated
E.g., power supply to signaling pin ratio higher in S.E.

Short answer
Differential a lot easier to build and get right the first time Can make S.E. work but often a lot more painful

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Voltage-Mode vs. Current-Mode

Transmission line has both voltage and current Terminology unfortunately heavily overloaded
Whether or not Zo of driver is high How Zo of driver is set What sets output swing
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Voltage-Mode vs. Current-Mode

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Another View
Low Impedance
VS

High Impedance

Single Ended

+ -

+ d ref -

VS/2 shared

Differential

+
+ -

d d

RX opposite of TX
Signal integrity implications?
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Why Terminate?

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External vs. Internal Termination

Internal: makes package L, pad C part of T-line External: chip/package become a stub
If want on-die term need to control its value
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Untrimmed Poly Termination


Main issue is variation: +/-20% at one temperature But
Its relatively linear ESD robust Low parasitics

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Ri, Ci, and Pad Complexity


Rs
1.00

L
0.80

Gd

LI CI RI
Ci, Ri typically dominate

Normalized amplitude

0.60

0.40

0.20

"low_CL" "1_drop" "2_drop" "4_drop" "8_drop" 1e+008 Freq (Hz) 1e+009

0.00

LPF at pad can dominate overall channel Example: 500fF ESD, 500fF driver, 500fF wire
Bandwidth ~4GHz with double-terminated link

Even worse in busses (or if add big series R)


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Active Terminations

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AC vs. DC Termination
With diff. can terminate to complement
High Z lower power See more shortly
RAC

Rx

TX sets common-mode
Can be inconvenient May need wide CM range
RAC

VCM RCM

Rx

AC-coupled + AC-term
Places some requirements on data though
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RCM VCM

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TX Design: Series vs. Parallel Termination

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Alphabet Soup
LVDS, CML GTL, GTL+, RSL, VM, CM HCM, LCM All same basic principles
Look at two representative circuits to understand some of the more fundamental tradeoffs

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CML TX + RX Term
VD D 50 VDD 50

Zo = 50

Tx
Zo = 50

Rx

Io = - 21m A Dou ble-term inated on-ch ip

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Side Note: Pre-Driver

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CML Power Consumption

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Differential VM TX + RX
Main motivation: can reduce power for same swing/supply

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Simplified Model And Power

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Bad News: Extra Complexity


Driver impedance (termination) now set totally by devices
Some sort of impedance control is critical

High-swing driver:

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Low-Swing VM Driver
Old standards often required large swings (>1V diff. p2p)
More modern designs use much lower swings (~200-400mV diff. p2p) to save power

Low-swing VM driver:

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Impedance Control

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Another Approach

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Serialization: Input vs. Output


On-chip clocks often slower than off-chip datarates
Need to take a set of parallel on-chip data and serialize it

Can serialize either at input of TX or at final output

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Serialization: Input vs. Output


Input ser. requires on-chip circuitry to run at full line rate
May lead to high power consumption In older technologies (0.35um) was hard to support highfreq. clocks

Output ser. noved burden at pad


At the time was highest BW

D0 D1 D2 data(ck0) clock(ck3) R TERM R TERM ck3 out_b out x8 d0 d0 29

Limit in both designs: edge rate


Either for the clock or for the data
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Basic TX Final Notes


Usually need many peripheral controls
Zo, edge-rate, etc.

Keep tuning out of the high-speed signal path


P(High-speed, low res. + low-speed, high-res.) << P(high-speed, high-res.)

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Basic TX Final Notes


Lots of research focused on reduced signaling power
I.e., power spent by actual final driver

Watch out for overhead (pre-drivers)


Especially with emerging low-swing designs, overhead can actually dominate Psig (400mV diff. p2p): Pdigital (100 min. sized inverters @ 10GHz):

More on this later


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Basic RX
Simplest: RX is just a comparator @ fbit
(Clocking later)

Key things to watch out for:


High sensitivity (low noise, low offset/hysteresis) Common-mode input range Supply/common-mode rejection Max. clock rate Power consumption

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Typical Design

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StrongArm Review

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Higher Speeds

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