The ARM processor is a 32-bit RISC processor, meaning it is built using the reduced instruction set computer (RISC)

instruction set architecture (ISA). ARM processors are microprocessors and are widely used in many of the mobile phones sold each year, as many as 98% of mobile phones. They are also used in personal digital assistants (PDA), digital media and music layers, handheld gaming systems, calculators, and even computer hard drives. The first ARM processor-based computer was the Acorn Archimedes, released in 1987. Apple Computer became involved with helping to improve the ARM technology in the late 1980s, with their work resulting in the ARM6 technology in 1992. Later, Acorn used the ARM6-based ARM 610 processor in their Risc PC computers in 1994. Today, the ARM architecture is licensed for use by many companies, including Apple, Cirrus Logic, Intel, LG, Microsoft, NEC, Nintendo, Nvidia, Sony, Samsung, Sharp, Texas Instruments, Yamaha, and many more. The latest developed ARM processor families include ARM11 and Cortex. ARM processors capable of 64bit processing are currently in development.

ARM processor features include:

Load/store architecture An orthogonal instruction set Mostly single-cycle execution A 16x32-bit register Enhanced power-saving design.

RISC processors (like ARM) have lower power consumption than complex instruction set computer (CISC) processors (like x86), which leads to RISC-based devices having greater battery life (or smaller battery size) and requiring less cooling. Thus, RISC-based devices can be smaller and weigh less.

CPU modes
The ARM architecture specifies the following CPU modes. At any moment in time, the CPU can be in only one mode, but it can switch modes due to external events (interrupts) or programmatically. User mode The only non-privileged mode. System mode The only privileged mode that is not entered by an exception. It can only be entered by executing an instruction that explicitly writes to the mode bits of the CPSR. Supervisor (svc) mode

A privileged mode entered whenever the CPU is reset or when a SWI instruction is executed. Abort mode A privileged mode that is entered whenever a prefetch abort or data abort exception occurs. Undefined mode A privileged mode that is entered whenever an undefined instruction exception occurs. Interrupt mode A privileged mode that is entered whenever the processor accepts an IRQ interrupt. Fast Interrupt mode A privileged mode that is entered whenever the processor accepts an FIQ interrupt. Hyp mode A hypervisor mode introduced in armv-7a for cortex-A15 processor for providing hardware virtualization support.
Conditional execution

The conditional execution feature (called predication) is implemented with a 4-bit condition code selector (the predicate) on every instruction; one of the four-bit codes is reserved as an "escape code" to specify certain unconditional instructions, but nearly all common instructions are conditional. Most CPU architectures only have condition codes on branch instructions. This cuts down significantly on the encoding bits available for displacements in memory access instructions, but on the other hand it avoids branch instructions when generating code for small if statements. The standard example of this is the subtraction-based Euclidean algorithm: ARM address mode In the C programming language, the loop is:
while(i != j) { if (i > j) i -= j; else j -= i; }

In ARM assembly, the loop is:

loop CMP ; set condition "NE" if (i != j), ; "GT" if (i > j), ; or "LT" if (i < j) SUBGT Ri, Ri, Rj ; if "GT" (greater than), i = i-j; SUBLT Rj, Rj, Ri ; if "LT" (less than), j = j-i; BNE loop ; if "NE" (not equal), then loop Ri, Rj

which avoids the branches around the then and else clauses. Note that if Ri and Rj are equal then neither of the SUB instructions will be executed, optimising out the need for a conditional

branch to implement the while check at the top of the loop, for example had SUBLE (less than or equal) been used.

Instruction set
To keep the design clean, simple and fast, the original ARM implementation was hardwired without microcode, like the much simpler 8-bit 6502 processor used in prior Acorn microcomputers. The ARM architecture includes the following RISC features:

Load/store architecture. No support for misaligned memory accesses (although now supported in ARMv6 cores, with some exceptions related to load/store multiple word instructions). Uniform 16 32-bit register file. Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. Later, the Thumb instruction set increased code density. Mostly single clock-cycle execution.

To compensate for the simpler design, compared with contemporary processors like the Intel 80286 and Motorola 68020, some additional design features were used:

Conditional execution of most instructions, reducing branch overhead and compensating for the lack of a branch predictor. Arithmetic instructions alter condition codes only when desired. 32-bit barrel shifter which can be used without performance penalty with most arithmetic instructions and address calculations. Powerful indexed addressing modes. A link register for fast leaf function calls. Simple, but fast, 2-priority-level interrupt subsystem with switched register banks.

Arithmetic instructions
The ARM supports add, subtract, and multiply instructions. The only ARM cores to include integer divide instructions are those implementing the ARMv7-M and ARMv7-R architectures, such as the Cortex-M3 and M4

ARM cores
Main article: List of ARM microprocessor cores Architecture ARMv1 ARMv2 ARMv3 ARMv4 ARMv5 ARMv6 ARMv7 ARMv8 ARM1 ARM2, ARM3 ARM6, ARM7 StrongARM, ARM7TDMI, ARM9TDMI ARM7EJ, ARM9E, ARM10E, XScale ARM11, ARM Cortex-M ARM Cortex-A, ARM Cortex-M, ARM Cortex-R No cores available yet. Will support 64-bit data and addressing[19][20] Family

Debugging
All modern ARM processors include hardware debugging facilities; without them, software debuggers could not perform basic operations like halting, stepping, and breakpointing of code starting from reset. These facilities are built using JTAG support, though some newer cores optionally support ARM's own two-wire "SWD" protocol.

DSP enhancement instructions

To improve the ARM architecture for digital signal processing and multimedia applications, a few new instructions were added to the set.[24] These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures. E-variants also imply T,D,M and I. The new instructions are common in digital signal processor architectures. They are variations on signed multiplyaccumulate, saturated add and subtract, and count leading zeros.

NOTE: The Motorola 68000 names comes from that the CPU has 68000 transistors!!

"Application" profile: Cortex-A series "Real-time" profile: Cortex-R series "Microcontroller" profile: Cortex-M series.